Application of Scientific problem solving method to IC design flow

By Srinivas Siripurapu May 2011 Seer Akademi2011

Scientific method of problem solving :basic steps

State the problem

Formulate a hypothesis
Test the hypothesis Collect the data Analyze the data and decide what to do next.
Srinivas Siripurapu Seer Akademi 2011

Apply these steps to the IC design flow

Step # 1: State the Problem

A problem can't be solved if it isn't understood. Observe that your chip lacks something. It might be not

floor planned, un-routed, or it perhaps it has DRC violations.

Srinivas Siripurapu

Seer Akademi 2011

Step # 2: Form a Hypothesis

This is a possible solution to the problem formed after

gathering information about the problem. The term "research" is properly applied here.
Standard cell overlapping? Possible because core utilization is

specified is more or even the core area is less.

Srinivas Siripurapu

Seer Akademi 2011

Step # 3: Test the Hypothesis

An experiment is performed to determine if the hypothesis

solves the problem or not. Experiments are done to gather data. It is very important that good observations and records are made during an experiment.
Re initialize the floorplan with the constraints that you

thought as near to the solution. Redesign the power / ground straps.

Srinivas Siripurapu

Seer Akademi 2011

Step # 4: Collect the Data

This is where you record your observations,

measurements, or information from experiment.

Collect the data to be analyzed that decides whether

your hypothesis failed or passed. verify_pg_nets -pad_pin_connection all Verify_drc > ../reports/drc_check.rpt Report_congestion > ../reports/congestion.rpt
Srinivas Siripurapu Seer Akademi 2011

Step # 5 : Analyze the Data

Just what does all that data indicate about answering the

problem you are solving?

Information: Reporting global route congestion data from Milkyway... Both Dirs: Overflow = 27 Max = 0 (0 GRCs) GRCs = 0 (34.00%) H routing: Overflow = 27 Max = 27 (0 GRCs) GRCs = 27 (34.00%) V routing: Overflow = Max = 0 (0 GRCs) GRCs = 0 (0.00%)

This report shows that there is congestion in Horizontal sections

Srinivas Siripurapu

Seer Akademi 2011

Step #6 : Draw Conclusions

After examining the data from the experiment,

conclusions can be drawn. In it's simplest form, the conclusion will be "yes" the hypothesis was correct, or "no" the hypothesis was not correct.
Based on the results in previous step you may want to

redesign your floorplan, or to choose another routing options etc..

Srinivas Siripurapu

Seer Akademi 2011

Control your design flow

Chip design is an iterative process. The design flow is run repeatedly as it is extended and

refined into a program that can automatically build the entire chip. Your flow needs software to make sure that only the necessary steps are executed, in the correct order, on the correct data. Different hierarchical blocks must be constructed similarly, yet differently.

Srinivas Siripurapu

Seer Akademi 2011

Flow steps
Dont tempt to write huge script to run EDA tool from

start to finish.
Separate the flow into smaller steps that perform

individual tasks.

Srinivas Siripurapu

Seer Akademi 2011

Reentrant step
Each step must be reentrant. This means that you can safely restart the flow at any step. The most basic requirement for reentrance is that the step

reads data from one database at the beginning, and saves the result in a database with a different name at the end.

Srinivas Siripurapu

Seer Akademi 2011

Descriptive names

Give each step a short, yet descriptive name.

Srinivas Siripurapu

Seer Akademi 2011

Input to Output
Where reasonable and efficient, the inputs and outputs of a

step use independent/proprietary formats.

Tip: Use vendor independent formats like Open-Access, LEF, DEF or Verilog most of the times. But many steps are best saved as a proprietary database, particularly in place and route. Milkyway database in our case.

Srinivas Siripurapu

Seer Akademi 2011

Commit and Exit safely

End steps at points where you have a meaningful, stable

result that will allow you to make an informed decision about what to do next.
For example, produce a legal placement, create a timing

report, and then end the step.

Srinivas Siripurapu

Seer Akademi 2011

Fine grained steps

The more iterations required to get a step right, the

shorter the step should be.

An example of this is power routing, where you often

tweak your power routing script, run, and observe the results several times before it works correctly.
Note: However, starting and stopping EDA tools, reading and writing databases takes time and space. For the sake of economy, you want fewer steps.

Srinivas Siripurapu

Seer Akademi 2011

Flow control architecture

Srinivas Siripurapu

Seer Akademi 2011

Flow controller
Flow controller is the boss. It manages the execution of flow steps like placement or

timing analysis.
It may be a simple shell script or a well organized

software program.
Sample shell script is shown in next slides. See how to

execute the flow iteratively.

Srinivas Siripurapu Seer Akademi 2011

Run the same command over and over

Run the same shell script(flow controller) at any time. Unix % ./run

Comment out the commands that we dont want when

executing a particular step. Once all steps are finished remove comments and execute the full design flow.

Srinivas Siripurapu

Seer Akademi 2011

When floor planning

All other statements are commented
#! /bin/sh export flowPath=../../flow # icc_shell -f ${flowPath}/icc/scr/netlistIn.tcl | tee netlistIn.log icc_shell -f ${flowPath}/icc/scr/floorplan.tcl | tee floorplan.log # icc_shell -f ${flowPath}/icc/scr/pgRoute.tcl | tee pgRoute.log

# icc_shell -f ${flowPath}/icc/scr/setupTiming.tcl | tee setupTiming.log

#icc_shell -f ${flowPath}/icc/scr/placement.tcl | tee placement.log

#icc_shell -f ${flowPath}/icc/scr/cts.tcl | tee cts.log # and so on...

Srinivas Siripurapu Seer Akademi 2011

Now P/G routing

#! /bin/sh export flowPath=../../flow # icc_shell -f ${flowPath}/icc/scr/netlistIn.tcl | tee netlistIn.log # icc_shell -f ${flowPath}/icc/scr/floorplan.tcl | tee floorplan.log icc_shell -f ${flowPath}/icc/scr/pgRoute.tcl | tee pgRoute.log

# icc_shell -f ${flowPath}/icc/scr/setupTiming.tcl | tee setupTiming.log

#icc_shell -f ${flowPath}/icc/scr/placement.tcl | tee placement.log

#icc_shell -f ${flowPath}/icc/scr/cts.tcl | tee cts.log # and so on...

Srinivas Siripurapu Seer Akademi 2011

Now setup timing

#! /bin/sh export flowPath=../../flow # icc_shell -f ${flowPath}/icc/scr/netlistIn.tcl | tee netlistIn.log # icc_shell -f ${flowPath}/icc/scr/floorplan.tcl | tee floorplan.log # icc_shell -f ${flowPath}/icc/scr/pgRoute.tcl | tee pgRoute.log

icc_shell -f ${flowPath}/icc/scr/setupTiming.tcl | tee setupTiming.log

#icc_shell -f ${flowPath}/icc/scr/placement.tcl | tee placement.log

#icc_shell -f ${flowPath}/icc/scr/cts.tcl | tee cts.log # and so on...

Srinivas Siripurapu Seer Akademi 2011

Now placment
#! /bin/sh export flowPath=../../flow # icc_shell -f ${flowPath}/icc/scr/netlistIn.tcl | tee netlistIn.log # icc_shell -f ${flowPath}/icc/scr/floorplan.tcl | tee floorplan.log # icc_shell -f ${flowPath}/icc/scr/pgRoute.tcl | tee pgRoute.log

# icc_shell -f ${flowPath}/icc/scr/setupTiming.tcl | tee setupTiming.log

icc_shell -f ${flowPath}/icc/scr/placement.tcl | tee placement.log

#icc_shell -f ${flowPath}/icc/scr/cts.tcl | tee cts.log # and so on...

Srinivas Siripurapu Seer Akademi 2011

Now clock tree synthesis

#! /bin/sh export flowPath=../../flow # icc_shell -f ${flowPath}/icc/scr/netlistIn.tcl | tee netlistIn.log # icc_shell -f ${flowPath}/icc/scr/floorplan.tcl | tee floorplan.log # icc_shell -f ${flowPath}/icc/scr/pgRoute.tcl | tee pgRoute.log

# icc_shell -f ${flowPath}/icc/scr/setupTiming.tcl | tee setupTiming.log

#icc_shell -f ${flowPath}/icc/scr/placement.tcl | tee placement.log

icc_shell -f ${flowPath}/icc/scr/cts.tcl | tee cts.log # and so on...

Srinivas Siripurapu Seer Akademi 2011

Conclusion
IC design is an iterative process. Scientific method of problem solving applies for

IC design flow too. Use creativity to design your flow.

Srinivas Siripurapu

Seer Akademi 2011

Personal appeal to my friends

Use your common sense to organize your work. Know your problems before starting your work otherwise

you simply wasting your time by running monotonous commands all the time without any results, and results in frustration.
icc_shell icc_shell . Bore Bore ..
Then solve your problems on your time not on others.

Srinivas Siripurapu

Seer Akademi 2011

All the best for your projects

Explore more reference flows

http://www.tsmc.com/english/c_services/c01_design/c01

05_reference.htm (this link is subjected to change) http://www.cadence.com/Community/blogs/di/archive/2 009/01/29/demo-and-interview-the-encounter-foundationflow.aspx http://theasicguy.com/2009/03/16/synopsys-lynx-designsystem-debuts-at-snug

Srinivas Siripurapu

Seer Akademi 2011