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RAJALAKSHMI ENGINEERING COLLEGE

THANDALAM, CHENNAI- 602105

Department of Electronics and Communication Engineering

147352

ELECTRON C C RC! T" L#$ L#$ %#N!#L

Prepared b Mr!"A"A!#a$Mr!"S"S%&a'(#)$Mr!"K"!(e**a

SYLLABUS 147352 ELECTRONIC CIRCUITS LAB I

(Common to ECE & Bio Medical Engineering) Expt No.1 Fixed Bias amplifier circuit using BJT 1. a!eforms at input and output "it#out $ias. %. &etermination of $ias resistance to locate '(point at center of load line. ). Measurement of gain. *. +lot t#e fre,uenc- response & &etermination of .ain Band"idt# +roduct Expt No.% &esign and construct BJT Common Emitter /mplifier using !oltage di!ider $ias (self($ias) "it# and "it#out $-passed emitter resistor. 1. Measurement of gain. %. +lot t#e fre,uenc- response & &etermination of .ain Band"idt# +roduct. Expt No.) &esign and construct BJT Common Collector /mplifier using !oltage &i!ider $ias (self($ias). 1. Measurement of gain. %. +lot t#e fre,uenc- response & &etermination of .ain Band"idt# +roduct. Expt No.* &arlington /mplifier using BJT. 1. Measurement of gain and input resistance. %. Comparison "it# calculated !alues. ). +lot t#e fre,uenc- response & &etermination of .ain Band"idt# +roduct Expt No.0 1ource follo"er "it# Bootstrapped gate resistance 1. Measurement of gain2 input resistance and output resistance "it# and "it#out Bootstrapping. %. Comparison "it# calculated !alues. Expt No.3 &ifferential amplifier using BJT 1. Measurement of CM44. %. Expt No.5 Class / +o"er /mplifier 1. 6$ser!ation of output "a!eform. %. Measurement of maximum po"er output. ). &etermination of efficienc-. *. Comparison "it# calculated !alues. Expt No.7 Class B Complementar- s-mmetr- po"er amplifier 1. 6$ser!ation of t#e output "a!eform "it# crosso!er &istortion. %. Modification of t#e circuit to a!oid crosso!er distortion. ). Measurement of maximum po"er output.

*. &etermination of efficienc-. 0. Comparison "it# calculated !alues. Expt No.8 +o"er 1uppl- circuit ( 9alf "a!e rectifier "it# simple capacitor filter. 1. Measurement of &C !oltage under load and ripple factor2 Comparison "it# calculated !alues. ). +lot t#e :oad regulation c#aracteristics using ;ener diode. Expt No.1< +o"er 1uppl- circuit ( Full "a!e rectifier "it# simple capacitor filter 1. Measurement of &C !oltage under load and ripple factor2 Comparison "it# calculated !alues. %. Measurement of load regulation c#aracteristics. Comparison "it# calculated !alues.

1" +I,ED -IAS AMPLI+IER CIRC.IT 1"1" AIM/

To construct a fixed bias amplifier circuit and to plot the frequency response characteristics. 1"2APPARAT.S RE0.IRED/

S.No. 1. 2. 3. (. -. 6. 7.

Name Transistor Resistor Regu ate! "o#er su"" y Signa )enerator CR. Brea! Boar! Ca"a/itor

Range BC107 10 k,100 k,680 $0%30&' $0%3&*+, 30 *+, (701

Quantity 1 1,1,1 1 1 1 1 2

CIRC.IT DIAGRAM

MODEL GRAPH

f1 TA-"1"1/

+IG"1"2

f2

f (Hz)

+RE0.ENC2 RESPONSE O+ +I,ED -IAS AMPLI+IER

Keep the input voltage constant

(Vin) =

Frequency (in Hz)

Output Voltage (in volts)

Gain = 20 log (Vo / Vin) (in dB)

1"3" +ORM.LA/

a) R2 $ 4R15R26 7 voltage at which operation ta$es place

lass !"

lass # or

lass

b) hfe = %&c ' %&b


1"8" THEOR2/

&n order to operate the transistor in the desired region" we have to apply an external dc voltage of correct polarity and magnitude to the two (unctions of the transistor. This is called biasing of the transistor.

)hen we bias a transistor" we establish certain current and voltage conditions for the transistor. These conditions are called operating conditions or dc operating point or quiescent point. This point must be stable for proper operation of transistor. !n important and common type of biasing is called *ixed #iasing. The circuit is very simple and uses only few components. #ut the circuit does not chec$ the collector current which increases with the rise in temperature.

1"5" PROCED.RE +. onnections are made as per the circuit diagram. ,. The waveforms at the input and output are observed for lass !" lass # and lass operations by varying the input voltages. -. The biasing resistances needed to locate the ./point are determined. 0. 1et the input voltage as +V and by varying the frequency" note the output voltage. 2. alculate gain=,3 log (Vo ' Vin) 4. ! graph is plotted between frequency and gain.

1"6" CALC.LATIONS/

a6

T9 de(er:)'e (#e ;a*%e 9< b)a! re!)!(a'=e R2 $ 4R15 R26

b6

#<e 7> IC$>I-

1"?" RES.LT/ Thus" the *ixed bias amplifier was constructed and the frequency response curve is plotted. The 5ain #andwidth 6roduct is found to be =

2" -JT AMPLI+IER .SING @OLTAGE DI@IDER -IAS

2"1" AIM/

To constant a voltage divider bias amplifier and measure input resistance and gain and also to plot the dc collector current as a function of collector resistance.

2"2" APPARAT.S RE0.IRED/

S.No. 1. 2. 3. (. -. 6. 7.

Name Transistor Resistor Ca"a/itor 1un/tion )enerator CR. Regu ate! "o#er su"" y Brea! Boar!

Range BC 107 -6k2,12k2,2.2k2,(702 0.101, (701 $0%3&*+, 30*+, $0%30&'

Quantity 1 1,1,1,1 2, 1 1 1 1 1

+IG"5"1

MODEL GRAPH

f1

+IG""2

f2

f (Hz)

TA- 2"1/

Keep (#e )'p%( ;9*(a&e =9'!(a'(, @)' 7

Frequency (in Hz)

Output Voltage (in volts)

Gain= 20 log(Vo/Vin) (in dB)

2"3" +ORM.LA/

a) 7in = 8 9 7e b) 5ain = 8 9 7e'7in


2"8" THEOR2/

This type of biasing is otherwise called :mitter #iasing. The necessary biasing is provided using - resistors; 7+" 7, and 7e. The resistors 7+ and 7, act as a potential divider and give a fixed voltage to the base. &f the collector current increases due to change in temperature or change in 8" the emitter current & e also increases and the voltage drop across 7e increases" reducing the voltage difference between the base and the emitter. <ue to reduction in V be" base current &b and

hence collector current &c also reduces. This reduction in V be" base current &b and hence collector current &c also reduces. This reduction in the collector current compensates for the original change in &c. The stability factor 1= (+=8) 9 ((+' (+=8)). To have better stability" we must $eep 7b'7e as small as possible. >ence the value of 7+ 7, must be small. &f the ratio 7b'7e is $ept fixed" 1 increases with 8.

5" PROCED.RE/

+. onnections are given as per the circuit diagram. ,. ?easure the input resistance as 7in=Vin'&in (with output open) and gain by plotting the frequency response. -. ompare the theoretical values with the practical values. 0. 6lot the dc collector current as a function of the collector resistance (ie) plot of Vcc and &c for various values of 7e.

2"6" RES.LT/

Thus the voltage divider bias amplifier was constructed and input resistance and gain were determined. The 5ain #andwidth 6roduct is found to be =

3" COMMON COLLECTOR AMPLI+IER

3"1 AIM/

To construct a common collector amplifier circuit and to plot the frequency response characteristics.

3"2" APPARAT.S RE0.IRED/

S.No. 1. 2. 3. (. -. 6. 7.

Name Transistor Resistor Ca"a/itor 1un/tion )enerator CR. Regu ate! "o#er su"" y Brea! Boar!

Range BC 107 1-k2,10k2,6802,6k2 0.101, (701 $0%3&*+, 30*+, $0%30&'

Quantity 1 1,1,1,1 2, 1 1 1 1 1

CIRC.IT DIAGRAM

MODEL GRAPH

f1

+IG""2

f2

f (Hz)

TA- 3"1/

Keep (#e )'p%( ;9*(a&e =9'!(a'(, @)' 7

Frequency (in Hz)

Output Voltage (in volts)

Gain= 20 log(Vo/Vin) (in dB)

3"3 THEOR2/

The d.c biasing in common collector is provided by 7 +" 7, and 7: .The load resistance is capacitor coupled to the emitter terminal of the transistor. )hen a signal is applied to the base of the transistor "V # is increased and decreased as the signal goes positive and negative" respectively. onsidering V#: is constant the variation in the V# appears at the emitter and emitter voltage V: will vary same as base voltage V# . 1ince the emitter is output terminal" it can be noted that the output voltage from a common collector circuit is the same as its input voltage. >ence the common collector circuit is also $nown as an emitter follower.

3"5 PROCED.RE/

+.

onnect the circuit as per the circuit diagram.

,. 1et Vi =23 mV" using the signal generator. -. Keeping the input voltage constant" vary the frequency from 3 >@ to +? >@ in regular steps and note down the corresponding output voltage. 0. 6lot the graphA 5ain (d#) Vs *requency (>@).

RE@IEA 0.ESTIONS/

+. )hy the common collector amplifier is also called an emitter followerB

,. )hat is the need for coupling capacitorsB

-. )hat will be the input Coutput impedance of common collector amplifierB

0.)rite some applications of common collector amplifier.

2.)hat is the current amplification factor of common collector amplifierB

3"6" RES.LT/ Thus" the ommon collector amplifier was constructed and the frequency response curve is plotted. The 5ain #andwidth 6roduct is found to be =

8" DARLINGTON AMPLI+IER .SING -JT

8"1 AIM/ To construct a <arlington current amplifier circuit and to plot the frequency response characteristics.

8"2" APPARAT.S RE0.IRED/

S.No. 1. 2. 3. (. -. 6. 7.

Name Transistor Resistor Ca"a/itor 1un/tion )enerator CR. Regu ate! "o#er su"" y Brea! Boar!

Range BC 107 1-k2,10k2,6802,6k2 0.101, (701 $0%3&*+, 30*+, $0%30&'

Quantity 1 1,1,1,1 2, 1 1 1 1 1

CIRC.IT DIAGRAM

MODEL GRAPH

f1

+IG""2

f2

f (Hz)

TA- 8"1/

Keep (#e )'p%( ;9*(a&e =9'!(a'(, @)' 7

Frequency (in Hz)

Output Voltage (in volts)

Gain= 20 log(Vo/Vin) (in dB)

THEOR2/

&n <arlington connection of transistors" emitter of the first transistor is directly connected to the base of the second transistor .#ecause of direct coupling dc output current of the first stage is (+=h fe )&b+.&f <arlington connection for n transitor is considered" then due to direct coupling the dc output current foe last stage is (+=hfe ) n times &b+ .<ue to very large amplification factor even two stage <arlington connection has large output current and output stage may have to be a power stage. !s the power amplifiers are not used in the amplifier circuits it is not possible to use more than two transistors in the <arlington connection. &n <arlington transistor connection" the lea$age current of the first transistor is amplified by the second transistor and overall lea$age current may be high" )hich is not desired.

8"8 PROCED.RE/

+.

onnect the circuit as per the circuit diagram.

,. 1et Vi =23 mv" using the signal generator. -. Keeping the input voltage constant" vary the frequency from 3 >@ to +? >@ in regular steps and note down the corresponding output voltage. 0. 6lot the graphA 5ain (d#) vs *requency(>@). 2. alculate the bandwidth from the graph.

8"5" RES.LT/ Thus" the <arlington current amplifier was constructed and the frequency response curve is plotted. . The 5ain #andwidth 6roduct is found to be =

RE@IEA 0.ESTIONS/

+. )hat is meant by <arlington pairB

,. >ow many transistors are used to construct a <arlington amplifier circuitB -. )hat is the advantage of <arlington amplifier circuitB

0.)rite some applications of <arlington amplifier .

5" SO.RCE +OLLOAER AITH -OOTSTRAPPED GATE RESISTANCE 5"1" AIM/ To construct a source follower with bootstrapped gate resistance amplifier and plot its frequency response characteristics.

5"2" APPARAT.S RE0.IRED/

1.Do . +. ,. -. 0.

Dame Transistor 7esistor 7egulated power supply 1ignal 5enerator # +3E

7ange

.uantit y , +"+"+ + +

+$F"++ $F"+? $F (3/-3)V (3/-)?>@

2. 4. E.

7G #read #oard apacitor

-3 ?>@

+ +

3.3+H*

+IG"13"1

MODEL GRAPH

f1 +IG"13"2

f2

f (Hz)

TA-"5"1"

Keep the input voltage constant (Vin) =

Frequency (in Hz)

Output Voltage (in volts)

Gain = 20 log (Vo / Vin) (in dB)

5"3" THEOR2/

Sour/e 3o o#er is simi ar to t4e emitter 3o o#er$ t4e out"ut sour/e 5o tage 3o o# t4e gate in"ut 5o tage&,t4e /ir/uit 4as a 5o tage gain o3 ess t4an unity, no "4ase re5ersa , 4ig4 in"ut im"e!an/e, o# out"ut im"e!an/e. +ere t4e Bootstra""ing is use! to in/rease t4e in"ut resistan/e 6y /onne/ting a resistan/e in 6et#een gate an! sour/e termina s. T4e resister R7 is re8uire! to !e5e o" t4e ne/essary 6ias 3or t4e gate. !"! #$O%&'($&)

+.

onnections are made as per the circuit diagram.

,. The waveforms at the input and output are observed for cascode operations by varying the input frequency. -. The biasing resistances needed to locate the ./point are determined. 0. 1et the input voltage as +V and by varying the frequency" note the output voltage. 2. alculate gain=,3 log (Vo ' Vin.)

4. ! graph is plotted between frequency and gain. RES.LT/

Thus" the 1ource follower with #ootstrapped gate resistance was constructed and the gain was determined.

RE@IEA 0.ESTIONS/

+. )hat is meant by source followerB ,. )hat is meant by #ootstrappingB -. >ow the above circuit is used to provide a good impedance matchingB 0. )hat is the advantage of bootstrapping methodB

6"DI++ERENTIAL AMPLI+IER .SING -JT 6"1A):/ To construct a differential amplifier using #IT and to determine the dc collector current of individual transistors and also to calculate the ?77.

6"2" APPARAT.S RE0.IRED/

S.No. 1. 2. 3. (. -. 6.

Name Transistor Resistor Regu ate! "o#er su"" y 1un/tion )enerator CR. Brea! Boar!

Range BC107 (.7k, 10k $0%30&' $0%3& *+, 30 *+,

Quantity 2 2,1 1 2 1 1

CIRC.IT DIAGRAM

O-SER@ATION @IN 7@O 7AC 7 @O $ @IN +ORM.LA/

ommon mode 5ain

(!c) = VG ' V&D

<ifferential mode 5ain (!d) = V3 ' V&D )here V&D = V+ J V, ommon ?ode 7e(ection 7atio ( ?77) = !d'!c )here" !d is the differential mode gain !c is the common mode gain. THEOR2/ The differential amplifier is a basic stage of an integrated operational amplifier. &t is used to amplify the difference between , signals. &t has excellent stability" high versatility and immunity to noise. &n a practical differential amplifier" the output depends not only upon the difference of the , signals but also depends upon the common mode signal. Transistor .+ and ., have matched characteristics. The values of 7 + and 7 , are equal. 7e+ and 7e, are also equal and this differential amplifier is called emitter coupled differential amplifier. The output is ta$en between the two output terminals.

O-SER@ATION

@IN 7 @1 B @2 @0 7 Ad 7 @0$ @IN *or the differential mode operation the input is ta$en from two different sources and the common mode operation the applied signals are ta$en from the same source ommon ?ode 7e(ection 7atio ( ?77) is an important parameter of the differential amplifier. ?77 is defined as the ratio of the differential mode gain" ! d to the common mode gain" !c.

?77 = !d ' !c &n ideal cases" the value of ?77 is very high.

6"5" PROCED.RE/

+. onnections are given as per the circuit diagram. ,. To determine the common mode gain" we set input signal with voltage

Vin=,V Vo gain" !c=Vo'Vin.


and determine at the collector terminals. alculate common mode

-. To determine the differential mode gain" we set input signals with voltages V+ and V,. ompute Vin=V+/V, and find Vo at the collector terminals. alculate differential mode gain" !d=Vo'Vin. 0. alculate the ?77=!d'!c. 2. ?easure the dc collector current for the individual transistors.

6"6" RES.LT/

Thus" the <ifferential amplifier was constructed and dc collector current for the individual transistors is determined. The ?77 is calculated as

RE@IEA 0.ESTIONS

+. )hat is a differential amplifierB ,. )hat is common mode and differential mode inputs in a differential amplifierB -. <efine ?77.

0. )hat is common mode signalB

2. )rite some applications of <ifferential amplifier. ?" CLASS - A POAER AMPLI+IER

?"1" AIM/

To construct a lass ! power amplifier and observe the waveform and to compute maximum output power and efficiency. ?"2" APPARAT.S RE0.IRED/

S.No. 1. 2. 3. (. -. 6. 7.

Name Transistor Resistor Ca"a/itor Signa )enerator CR. Regu ate! "o#er su"" y Brea! Boar!

Range C9100, BC--8 (7k2,332,220, (7 01 $0%3&*+, 30*+, $0%30&'

Quantity 1,1 2,1 2 1 1 1 1

CIRC.IT DIAGRAM

TA- 2"1/

Keep (#e )'p%( ;9*(a&e =9'!(a'(, @)' 7

Frequency (in Hz)

Output Voltage (in volts)

Gain= 20 log(Vo/Vin) (in dB)

?"3" +ORM.LA

MaC):%: p9Der (ra'!<er 7P9,:aC7@92$RL E<<e=)e'= ,E 7 P9,:aC$P=

?"8" THEOR2/ The power amplifier is said to be lass ! amplifier if the . point and the input signal are selected such that the output signal is obtained for a full input signal cycle. *or all values of input signal" the transistor remains in the active region and never enters into cut/off or saturation region. )hen an a.c signal is applied" the collector voltage varies sinusoidally hence the collector current also varies

sinusoidally.The collector current flows for -43 3 (full cycle) of the input signal. i e the angle of the collector current flow is -43 3 . ?"5 PROCED.RE/ +. onnect the circuit as per the circuit diagram.

,. 1et Vi =23 mv" using the signal generator. -. Keeping the input voltage constant" vary the frequency from +3 >@ to +? >@ in regular steps and note down the corresponding output voltage. 0. 6lot the graphA 5ain (d#) vs *requency(>@). ?"6"RES.LT/ Thus the lass ! power amplifier was constructed. The following parameters were calculated; K a) ?aximum output power= b) :fficiency=

RE@IEA 0.ESTIONS/

+. )hat is meant by 6ower !mplifierB ,. )hat is the maximum efficiency in class J ! amplifier. -. )hat are the disadvantages of lass J! amplifierB

0. )rite some applications of 6ower amplifier. 2. )hat is the position of ./point in lass J! amplifierB

F" CLASS - COMPLEMENTAR2 S2MMETR2 POAER AMPLI+IER F"1" AIM/

To construct a lass # complementary symmetry power amplifier and observe the waveforms with and without cross/over distortion and to compute maximum output power and efficiency.

F"2" APPARAT.S RE0.IRED/

S.No. 1. 2. 3. (. -. 6. 7. 8.

Name Transistor Resistor Ca"a/itor :io!e Signa )enerator CR. Regu ate! "o#er su"" y Brea! Boar!

Range C9100, BC--8 (.7k2,1-k2 10001 ;N(007 $0%3&*+, 30*+, $0%30&'

Quantity 1,1 2,1 2 2 1 1 1 1

CIRC.IT DIAGRAM

F"3" +ORM.LA/

&nput power" 6in=,Vcc&m'L

Gutput power" 6out=Vm&m', 6ower 5ain or efficiency" M=N'0(Vm'Vcc) +33


F"8" THEOR2/ ! power amplifier is said to be lass # amplifier if the ./point and the input signal are selected such that the output signal is obtained only for one half cycle for a full input cycle. The ./point is selected on the O/axis. >ence" the transistor remains in the active region only for the positive half of the input signal. There are two types of lass # power amplifiers; 6ush 6ull amplifier and complementary symmetry amplifier. &n the complementary symmetry amplifier" one n/p/n and another p/n/p transistor is used. The matched pair of transistor are used in the common collector configuration. &n the positive half cycle of the input signal" the n/p/n transistor is driven into active region and starts conducting and in negative half cycle" the p/n/p transistor is driven into conduction. >owever there is a period between the crossing of the half cycles of the input signals" for which none of the transistor is active and output" is @ero CIRC.IT DIAGRAM

+IG"6"2

O-SER@ATION O.TP.T SIGNAL

AMPLIT.DE/ TIME PERIOD /

CALC.LATION

POAER, PIN O.TP.T POAER, PO.T E++ICIENC2, 7

2@CC I:$G

@:I:$2

7 4 G$864 @:$ @CC6 C 100

MODEL GRAPH

+IG"6"3

F"5" PROCED.RE/ +. onnections are given as per the circuit diagram without diodes. ,. Gbserve the waveforms and note the amplitude and time period of the input signal and distorted waveforms. -. onnections are made with diodes. 0. Gbserve the waveforms and note the amplitude and time period of the input signal and output signal. 2. <raw the waveforms for the readings. 4. alculate the maximum output power and efficiency. >ence the nature of the output signal gets distorted and no longer remains the same as the input. This distortion is called cross/over distortion. <ue to this distortion" each transistor conducts for less than half cycle rather than the complete half cycle. To overcome this distortion" we add , diodes to provide a fixed bias and eliminate cross/over distortion. F"6"RES.LT/ Thus the lass # complementary symmetry power amplifier was constructed to observe cross/over distortion and the circuit was modified to avoid the distortion. The following parameters were calculated; a)?aximum output power= b):fficiency= 1" HAL+ AA@E RECTI+IER

1"1" AIM/

To /onstru/t 4a 3 #a5e re/ti3ier #it4 an! #it4out 3i ter an! to !ra# t4eir in"ut an! out"ut #a5e3orms.
1"2" APPARAT.S RE0.IRED/ 1.Do . +. ,. -. 0. 2. 4. Dame Transformer <iode 7esistor apacitor 7G #read #oard 7ange ,-3 V ' 4/3/(/4) &D033E + $F +33H* -3 ?>@ .uantity + + + + + +

CIRC.IT DIAGRAM/ AITHO.T +ILTER/

+IG"13"1

AITH +ILTER/

+IG"13"2

1"3" +ORM.LA .SED/

R)pp*e +a=(9r 7 A#ere I: )! (#e peaH =%rre'(

1"8" THEOR2/

Ha*< Da;e re=()<)er/

! rectifier is a circuit" which uses one or more diodes to convert !. voltage into <. voltage. &n this rectifier during the positive half cycle of the !. input voltage" the diode is forward biased and conducts for all voltages greater than the offset voltage of the semiconductor material used. The voltage produced across the load resistor has same shape as that of the positive input half cycle of !. input voltage.

<uring the negative half cycle" the diode is reverse biased and it does not conduct. 1o there is no current flow or voltage drop across load resistor. The net result is that only the positive half cycle of the input voltage appears at the output.

1"5" PROCED.RE/

+. onnect the circuit as per the circuit diagram. ,. !pply a.c input using transformer. -. ?easure the amplitude and time period for the input and output waveforms. 0. alculate ripple factor. MODEL GRAPH/

+IG"13"5

TA-"1"1/

HAL+ AA@E RECTI+IER/

)ithout filter &nput signal !mplitude(V) Time period

)ith filter Gutput signal !mplitude(V) Time period

1"6" RES.LT/ Thus the half wave rectifier was constructed and its input and output waveforms are drawn. The ripple factor of capacitive filter is calculated as

7ipple factor=

10" +.LL AA@E RECTI+IER 10"1" AIM/ To construct a full wave rectifier and to measure dc voltage under load and to calculate the ripple factor. 10"2" APPARAT.S RE0.IRED/

S.No. 1. 2. 3. (. -. 6.

Name Trans3ormer :io!e Resistor Ca"a/itor CR. Brea! Boar!

Range 230 ' < 6%0%$%6& ;N(007 1 k 10001 30 *+,

Quantity 1 2 1 1 1 1

+.LLAA@E RECTI+IER AITHO.T +ILTER

+IG"F"1

+.LLAA@E RECTI+IER AITH +ILTER

+IG"F"2

10"3" +ORM.LA R)pp*e +a=(9r 7

I J4I:$I26 $ 42KI: $G6L 2-1

A#ere I: )! (#e peaH =%rre'(

10"8" THEOR2/ The full wave rectifier conducts for both the positive and negative half cycles of the input ac supply. &n order to rectify both the half cycles of the ac input" two diodes are used in this circuit. The diodes feed a common load 7P with the help of a centre tapped transformer. The ac voltage is applied through a suitable power transformer with proper turnQs ratio. The rectifierQs dc output is obtained across the load. The dc load current for the full wave rectifier is twice that of the half wave rectifier. The lowest ripple factor is twice that of the full wave rectifier. The efficiency of full wave rectification is twice that of half wave rectification. The ripple factor also for the full wave rectifier is less compared to the half wave rectifier. PROCED.RE/ +. onnections are given as per the circuit diagram wiyhout filter.

,. Dote the amplitude and time period of the input signal at the secondary winding of the transformer and rectified output. -. 7epeat the same steps with the filter and measure Vdc. 0. alculate the ripple factor. 2. <raw the graph for voltage versus time. MODEL GRAPH

RES.LT/ Thus" the full wave rectifier was constructed and the ripple factor was calculated as 7ipple factor =

10"5 RE@IEA 0.ESTIONS/

+. )hat is meant by rectifierB ,. )rite the operation of two diodes during the application of ! -. )hich type of transformer used for the rectifier inputB 0. <efine ripple factor. 2. )rite the efficiency of this rectifier. input signal

11" CASCADE AMPLI+IER CIRC.IT 11"1" AIM/

To construct a cascade amplifier circuit and to plot the frequency response characteristics. 11"2" APPARAT.S RE0.IRED/ 1.Do . +. ,. -. 0. 2. 4. E. Dame Transistor 7esistor 7egulated power supply 1ignal 5enerator 7G #read #oard apacitor 3.3+H* # +3E +3$F"R $F"233 F"+33F (3/-3)V (3/-)?>@ -3 ?>@ 7ange .uantity + +"+"+"+ + + + + 2

11"3" THEOR2/

7 /as/a!e am" i3ier 4as many o3 t4e same 6ene3its as a /as/o!e. 7 /as/a!e is 6asi/a y a !i33erentia am" i3ier #it4 one in"ut groun!e! an! t4e si!e #it4 t4e rea in"ut 4as no oa!. ;t /an a so 6e seen as a /ommon /o e/tor $emitter 3o o#er& 3o o#e! 6y a /ommon 6ase. By /as/a!ing a C= stage 3o o#e! 6y an emitter%3o o#er $CC& stage, a goo! 5o tage am" i3ier resu ts. T4e C= in"ut resistan/e is 4ig4 an! CC out"ut resistan/e is o#. T4e CC /ontri6utes no in/rease in 5o tage gain 6ut "ro5i!es a near 5o tage%sour/e $ o# resistan/e& out"ut so t4at t4e gain is near y in!e"en!ent o3 oa! resistan/e. T4e 4ig4 in"ut resistan/e o3 t4e C= stage makes t4e in"ut 5o tage near y in!e"en!ent o3 in"ut%sour/e resistan/e. *u ti" e C= stages /an 6e /as/a!e! an! CC stages inserte! 6et#een t4em to re!u/e attenuation !ue to inter%stage oa!ing.

+IG"11"1

MODEL GRAPH

f1

+IG"11"2

f2

f (Hz)

11"8" PROCED.RE/

+.

onnections are made as per the circuit diagram.

,. The waveforms at the input and output are observed for cascade operations by varying the input frequency. -. The determined. biasing resistances needed to locate the ./point are

0. 1et the input voltage as +V and by varying the frequency" note the output voltage. 2. alculate gain=,3 log (Vo ' Vin.)

4. ! graph is plotted between frequency and gain. TA-"11"1" +RE0.ENC2 RESPONSE O+ CASCODE AMPLI+IER Keep the input voltage constant (Vin) =
Frequency (in Hz) Output Voltage (in volts) Gain = 20 log (Vo / Vin) (in dB)

11"5" RES.LT/

Thus" the determined.

ascade amplifier was constructed and the gain was

RE@IEA 0.ESTIONS +. )hat is meant by ascadingB

,. )hat is the overall gain of the two stage cascaded amplifierB

-. )hat methods are used for cascadingB

0. )hat is the disadvantage of direct coupled cascade amplifierB 2. )rite some application of cascaded amplifier.

12" CASCODE AMPLI+IER CIRC.IT 12"1" AIM/

To construct a cascode amplifier circuit and to plot the frequency response characteristics.

12"2" APPARAT.S RE0.IRED/

1.Do . +.

Dame Transistor # +3E

7ange

.uantit y , +"+"+"+" +"+"+" + + + + +

,,$F"4 $F"E33 F"0E3F ,. 7esistor +4 $F"4., $F"-.- $F +.+ $F -. 0. 2. 4. E. 7egulated power supply 1ignal 5enerator 7G #read #oard apacitor 3.3+H* (3/-3)V (3/-)?>@ -3 ?>@

12"3" THEOR2/

7 /as/o!e am" i3ier /onsists o3 a /ommon emitter am" i3ier stage in series #it4 a /ommon 6ase am" i3ier stage. ;t it one a""roa/4 to so 5e t4e o# im"e!an/e "ro6 em o3 a /ommon 6ase /ir/uit. Transistor Q1 an! its asso/iate! /om"onents o"erate as a /ommon emitter am" i3ier, #4i e t4e /ir/uit o3 Q2 3un/tions as a /ommon 6ase out"ut stage. T4e /as/a!e am" i3ier gi5es t4e 4ig4 in"ut im"e!an/e o3 a /ommon emitter am" i3ier, as #e as t4e goo! 5o tage gain an! 3re8uen/y "er3orman/e o3 a /ommon 6ase /ir/uit.

+IG"12"1 MODEL GRAPH

f1

+IG"12"2

f2

f (Hz)

*2!"! #$O%&'($&)
+. onnections are made as per the circuit diagram.

,. The waveforms at the input and output are observed for cascode operations by varying the input frequency. -. The biasing resistances needed to locate the ./point are determined. 0. 1et the input voltage as +V and by varying the frequency" note the output voltage.

2.

alculate gain=,3 log (Vo ' Vin.)

4. ! graph is plotted between frequency and gain.

TA-"12"1"

+RE0.ENC2 RESPONSE O+ CASCODE AMPLI+IER Keep the input voltage constant (Vin) =
Frequency (in Hz) Output Voltage (in volts) Gain = 20 log (Vo / Vin) (in dB)

12"5" RES.LT/

Thus" the

ascade amplifier was constructed and the gain was determined.

RE@IEA 0.ESTIONS/ +. )hat is meant by ascodingB

,. )hat is the overall gain of the two stage cascaded amplifierB -. )hat methods are used for cascadingB 0. )hat is the disadvantage of direct coupled cascade amplifierB 2. ompare cascade amplifier with cascade amplifier.

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