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MEE 10203 PROGRAMMABLE ELECTRONICS ASSIGNMENT ONE

PREPARED BY: MATRIX NO: DATE:

NUR UMAIRA BINTI ZULKIFLI GE 130033 8/10/2013

PREPARED FOR: DR. MOHAMAD HAIROL BIN JABBAR

1. Perform an Internet search and find the 74154 4-to-16 decoder datasheet. From the functional description given in the datasheet, write a VHDL description for a 74154 4-to16 decoder. Use only STD_LOGIC and STD_LOGIC_VECTOR data types in constructing your design. Enter the design into the Quartus II software and verify the syntax correctness by compiling the design. The design should compile without error. Use suggested style guidelines for your VHDL source code. Turn in both the datasheet and the VHDL source.

Fig. 1.1: 4-line to 16-line Decoders Truth Table

Fig. 1.2: Logic Diagram

LIBRARY ieee ; USE ieee.std_logic_1164.all ; ENTITY DEC4TO16 IS PORT ( w : IN STD_LOGIC_VECTOR(3 DOWNTO 0) ; En : IN STD_LOGIC_VECTOR(1 DOWNTO 0) ; y : OUT STD_LOGIC_VECTOR(0 TO 15) ) ; END DEC4TO16 ; ARCHITECTURE Behavior OF DEC4TO16 IS SIGNAL Enw : STD_LOGIC_VECTOR(5 DOWNTO 0) ; BEGIN Enw <= En & w ; WITH Enw SELECT y <= "0111111111111111" WHEN "000000", "1011111111111111" WHEN "000001", "1101111111111111" WHEN "000010", "1110111111111111" WHEN "000011", "1111011111111111" WHEN "000100", "1111101111111111" WHEN "000101", "1111110111111111" WHEN "000110", "1111111011111111" WHEN "000111", "1111111101111111" WHEN "001000", "1111111110111111" WHEN "001001", "1111111111011111" WHEN "001010", "1111111111101111" WHEN "001011", "1111111111110111" WHEN "001100", "1111111111111011" WHEN "001101", "1111111111111101" WHEN "001110", "1111111111111110" WHEN "001111", "1111111111111111" WHEN OTHERS ; END Behavior ;

Fig. 1.3: Decoder VHDL Source

Fig. 1.4: Compilation

2. Write a VHDL description for a 4-bit binary-to-gray code converter. Enter the design into the Quartus II software and verify the syntax correctness by compiling the design.

library ieee; use ieee.std_logic_1164.all; entity converter is port( b:in std_logic_vector(3 downto 0); g:out std_logic_vector(3 downto 0)); end converter; architecture binarytogrey of converter is begin g(3)<=b(3); g(2)<=b(3) xor b(2); g(1)<=b(2) xor b(1); g(0)<=b(1) xor b(0); end binarytogrey;

Fig. 2.1: 4-bit Binary to Grey Code Converter VHDL Source Code

Fig. 2.2: Binary to Grey Converter Design Compilation

3. Implement the following truth table-based design in VHDL code A 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 B 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 C 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 D 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Y1 1 1 1 1 1 1 1 1 1 0 0 1 1 1 1 1 Y2 0 0 0 0 0 0 0 0 0 1 1 1 0 0 0 0

Karnaugh map: AB CD 00 01 11 10 Y1 = A + B + CD + CD AB CD 00 01 11 10 Y2 = AB(C+D) 00 1 1 1 1 01 1 1 1 0 11 1 1 1 1 10 1 1 1 0

00 0 0 0 0

01 0 0 0 1

11 0 0 0 1

10 0 0 0 1

library ieee ; use ieee.std_logic_1164.all; entity kmap is port ( a, b, c, d : in std_logic ; y1,y2 : out std_logic); end kmap ;

architecture karnaugh of kmap is signal abcd : std_logic_vector (3 downto 0) ; begin y1 <= (not a) or (b) or (not c and not d) or (c and d); y2 <= a and not b and (d or c); end karnaugh ;

Fig. 3.1: K-Map VHDL source code

Fig. 3.2: VHDL Compilation

Fig. 3.3: Waveform Compilation

Fig. 3.4: Waveform Simulation

4. Perform a functional simulation of the designs for problems 1, 2, 3 and 4. Submit a Vector Waveform File (.vwf) verifying the correctness of the design for each problem. Problem 1: 4 to 16 Decoder

Fig. 4.1: 4-to-16bit Decoder Waveform

Problem 2: 4-bit binary-to-gray code converter

Fig. 4.2: 4bit Binary-to-Grey Code Converter Waveform

Problem 3: Karnaugh Map

Fig. 4.3: K-Map Waveform

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