Physics 3330

Experiment #9

Fall 1999

Digital Logic Elements, Clock, and Memory Elements

Purpose
This experiment introduces the fundamental circuit elements of digital electronics. These include a basic set of three LOGIC GATES which suffice to build anything digital; the 555 TIMER as a source of logic signals, and two types of memory element. Boolean Algebra, the mathematics of two-valued variables, will be used to design digital circuits.

Introduction
Most physical quantities can assume any value within some continuous range; this value varies with time in a dynamic process. The output voltage of a transducer that observes it will change with time in an analogous way. Such continuous signals, V = V(t), are called analog signals, and circuits which preserve the information in this form, such as linear amplifiers and sine-wave oscillators, are collectively known as Analog Electronics. In contrast to this, the voltages in digital circuits have only two states: HIGH and LOW. Information is conveyed by the pattern of HI and LO voltages. These may occur at the same time in a set of parallel wires (parallel or combinational logic); or as a time sequence of HIGHs and LOWs moving along a single wire (sequential logic). Analog information can be translated into digital form by an Analog-to-Digital Converter (ADC). A set of N on/off values or BITS has 2N possible different values. If you try to represent a voltage, V, by a 7 bit sequence, your uncertainty will be about 1%, since there are 27 = 128 possible combinations of digital values. A higher accuracy needs more digits or bits.

Readings
1. D & H, 11.1-11.5, 12.1-12.5. 2. (Optional) (a) Horowitz and Hill Chapter 8. (b) Brophy: Chapter 9 Digital Electronics. Pages 272-290: Digital logic, Boolean Algebra, and Logic circuits. (c) TTL Cookbook, Don Lancaster, SAMS (1974).

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Outline
1. Set up and test the 10-element LEDs as logic state indicators. 2. Verify the truth tables for the NAND, NOR, and INVERT gates. Carry out the INVERT operation by making suitable connections first to a NAND gate, then to a NOR gate. Thus you can dispense with the INVERT gates if only a few are needed. 3. Verify the truth table for an EXCLUSIVE OR (XOR) gate. Design, build, and test your own XOR circuit using only NAND and NOR chips. 4. Design, build, and test a TTL Digital Clock using a 555 timer chip. Convert the clock to an electronic stop-watch. Use a NAND gate to control the flow of pulses and the counter/timer to totalize the number of them in your measured interval. 5. Construct a RESET- SET (RS) memory element using two NOR gates. Derive the truth table by reasoning, then verify it with the LEDs. Demonstrate a complete memory cycle: Set, Store, Reset, Store, Set. Examine the effect of the illegal (S=1, R=1) for both possible previous states. 6. Construct an empirical truth table for the JK flip-flop directly from your observations with LEDs. Does it agree with the Boolean expression for the output in Figure 9.5? With the oscilloscope, look at the toggling action of the flip-flop for clock pulses from your TIMER when J=K=1.

Theory - Electronic Logic and Boolean Algebra

Logic states The voltage in a digital circuit is allowed to be in only one of two states: HIGH and LOW. We usually abbreviate these as HI and LO. HI is taken to mean logical (1) or logical TRUE. LO is taken to mean logical (0) or logical FALSE. In the TTL logic family (see Fig. 9.1 on following page): Any voltage in the range 2.8 to 5.0 V is HI. Any voltage in the 0 to 0.8 V is LO. Any voltage outside this range is undefined, and therefore illegal, except briefly during transitions. We will refer to HI as the 5 volt level, and LO as the 0 volt level.

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Logic operations and logic gates. The flow of digital signals is controlled by transistors which function as switches with just two states: OPEN and CLOSED. The state of a switch is controlled by a digital signal. The switch remains closed so long as a logical (1) signal is applied. A logical (0) control signal keeps it open. Logic signals interact by means of GATES. The three fundamental gates AND, OR, and NOT, are named after the three fundamental operations of logic that they carry out. The AND and OR gates each have two inputs and one output. The output state is determined by the states of the two inputs. The function of each gate is defined by a TRUTH TABLE, which specifies the output state for each possible combination of input states. The physical basis for the truth tables can be understood in terms of two switches. If the switches are in series, you get the AND function. Parallel switches perform the OR operation. The most common gates are shown in the lower table in Fig. 9.1. A bubble after a gate indicates NOT (the function evaluated). Thus, NAND means NOT (AND). The EXCLUSIVE-OR (XOR) contains several basic gates that you will assemble in part 4 of the experiment to make a functional XOR circuit. The basic gates that we will use throughout the logic experiments are two-input NAND and NOR, and INVERT. the NAND and NOR are especially useful when DeMorgans theorems are employed to simplify complex circuits (see discussion below). When several gates are combined to perform a complex logical operation, elegance and economy persuade one to use as few as possible. Boolean Algebra, the mathematics of two valued variables, is the theoretical tool used to accomplish this circuit simplification.

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Figure 9.1. Basic logic operations and gates.

Volts 5.0 HIGH 2.8 Transition from LOW to HIGH 0.8 LOW 0 Time TTL logic levels typical 0.4 V typical 3.5 V

Logical States Logical 1 = YES = TRUE = Switch closed = +5 V (TTL Logic) Logical 0 = NO = FALSE = Switch opened = 0 V (TTL) Basic Logic Operation Operation Switches A AND Series A OR B Parallel NOT Same as invert Other Gates NAND NOR XOR Different switch 1 means open 0 means closed NOT A A A _ A (A OR B is closed) A +B
A B A+B

Condition that circuit is closed (A AND B are closed)

Boolean Notation A B or AB
A B

Symbol
A.B

Truth Table
A B 0 0 0 1 1 0 1 1 A B A.B 0 0 0 1 A+B

0 0 1 1

0 1 0 1
_ A A 0 1 1 0

0 1 1 1

A B A B A B

A.B A+B A+B =AB+AB 9.4 Fall 1999

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Boolean Algebra
Fundamental laws We imagine a logical variable, A, that takes on the values 0 or 1. If A = 0 then A = 1 and if A = 1 then A = 0 OR A +0 = A A +1 = 1 A+A=A A + A =1 Equality Two Boolean expressions are equal if and only if their truth tables are identical. Associative Laws AND A0 = 0 A 1 = A A A = A A A =0 NOT A + A =1 A A =0 A=A

( A + B ) + C = A + ( B + C) ( AB)C = A( BC)
Distributive Laws A(B + C ) = AB + AC Related identities:

( A + A B) = A + B
( A + B) ( A + C ) = ( A + BC )
DeMorgans Theorems A B K = A + B + K A + B +K = A B K Example of Method of Proof: Heres an example of proving theorems by direct comparison of truth tables. We take on DeMorgans first theorem for two variables, AB = A + B : A 0 0 1 1 B 0 1 0 1 AB 0 0 0 1 AB 1 1 1 0 A 0 0 1 1 B 0 1 0 1 A 1 1 0 0 B 1 0 1 0 A+B 1 1 1 0

( A + AB) = A

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The last columns of the truth tables are identical. Thus, the first theorem is proven for two variables . Examples of simplification: Boolean algebra can be used to simplify logical expressions and reduce the number of gates required in a circuit. Here we show two ways to implement the expression, Y = A + A BC :
A) DIRECT IMPLEMENTATION using NOT, NOR, and NAND A A BC B C B) SIMPLIFIED CIRCUIT
Y = A+ABC = A+BC (by identity #2) = A+BC (by property of NOT) = A(BC) (by De Morgan's Law)

A+ABC Y = A+ABC

BC

ABC

ABC

A A B C Y = A+ABC

Fig. 9.2. Boolean simplification Expressions with many input variables. In the next experiments, you will form logic expressions with up to six input variables using logic gates with two inputs each. Here are some examples that illustrate the use of the double complement i.e., A = A , with DeMorgans Theorems for reducing expressions to form that can be implemented only with NAND and NOR, thus reducing the types of gates needed.

AB = AB = A + B ABCD = AB.CD = AB + CD A + B = A + B = A.B A + B + C + D = (A+B) + (C+D) = (A+B).(C+D)

{ {

A B C D A B C D

Y = ABCD

Y = A+B+C+D

Fig. 9.3. Reduction to NAND and NOR via DeMorgans Theorem. The above circuits are examples of combinatorial logic. The output appears almost immediately upon application of the inputs. The logic value of the output depends only upon the present-time combination of a number of parallel inputs and the arrangement of gates. The binary-decimal decoder in Experiment #10 is an example of combinatorial logic.

Memory Elements and Flip Flops

In Sequential Logic circuits the output depends upon previous values of the input signals as well as their present-time values. Such circuits necessarily include memory elements that store the

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logic values of the earlier signals. The fundamental circuit is the RS memory element. The JK flip-flop possesses external controls over the input to an RS memory that lies at its core. RS (Reset-Set Memory) Element

RS MEMORY
Signals R S Q
SET RESET time S

Circuit R Q=R+P R S

Symbol Q Q S 0 1 0 1

Truth Table R Q P=Q 0 Stays the same 0 0 1 1 1 0 1 0 0 P=Q Disallowed

P=S+Q

Fig. 9.4. RS memory element. The truth table shows how the circuit remembers. Suppose that it is originally in a state with Q=0 and R=S=0. A positive pulse, S, at the input sets it into the state Q=1, where it remains after S returns to zero. A later pulse, R, on the other input resets the circuit to Q=0, where it remains until the next S pulse. JK Flip Flops. (74107) There are three kinds of input to the JK flip flop: data inputs J and K the clock input C the direct input CLR ( = clear)

There are two outputs, Q and its complement.

JK Flip Flop (74107) C
Qn Qn+1 time Clock Input

Data inputs J C K Q CLR Direct Input Q

CLR C J 1 1 1 1 0

Qn+1 Qn+1 Qn 1 0 Qn 0 Qn 0 1 Qn 1 Stays the same ( = J) ( = J) Toggle mode Always

Outputs

0 1 0 1

0 0 1 1

anything

Boolean Expression: Qn+1 = (CLR)(JnKn+JnKnQn+JnKnQn)

Fig. 9.5. JK flip-flop description. In the absence of a clock pulse, the output remains unchanged at the previously acquired value, Qn , which is independent of the present-time data inputs J and K. Only on arrival of a clock pulse, C, can the output change to a new value, Qn +1 . The value of Qn +1 depends on the J and K inputs just before the clock pulse in the way specified in the truth table. The change occurs at the

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downward going trailing edge of the clock pulse, as indicated by the downward arrow in the truth table. The direct input, CLR, overrides the clock and data inputs. During normal operation, CLR = 1. At the moment CLR goes to zero, the output goes to zero and remains there so long as CLR = 0. All these options are contained in the Boolean expression in the figure. 555 Timer and digital clock (a) Block diagram of "555" V+ Upper
5 k Comparitor

(b) Pin layout

Output Amplifier

DC supply 8 Control 5 Voltage Threshold 6 Trigger 2

+ 5 k Lower Comp.

R Q

3 Output

1 GND

8 7

555

2 TRIG S Clear 3 OUT 4 RST

DIS

THR 6 BYP 5

Reset

4 5 k Discharge switch

Discharge 7 Ground 1

Figure 9.6 555 Timer chip

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(a) Astable circuit (Digital Clock) +5V

1 GND +
555 DIS THR

8 7 6

RA RB VC

Output

2 TRIG 3 OUT 4 RST

(b) Component values Output High (charge time): T2 = (RA+RB)C ln2 Output Low (discharge): T1 = RBC ln2 Period: T = T1 + T2 (c) Limiting Values Max RA, RB 3.3 M Min RA, RB 1 k Min. C 500pf

BYP 5

0.1uf

C 0V

(d) Voltage outputs

Pin 6 - Capacitor Voltage V c DC Volts V+ .667 V+ .333 V+ Supply Voltage (5V) Threshold Level Trigger Level time t2 DC Volts V+ t1 Pin 3 Output Voltage C charges through RA and RB in series C discharges through RB only Output is positive while C is charging Output is grounded while C is discharging

time

Figure 9.7 Astable circuit using 555 Timer chip

Problems
1. Enter in your lab book the circuit diagrams and truth tables of all the circuits you will test. 2. Prove DeMorgans second theorem by comparing the truth table for both sides of the equation: A +B = A B Use the laws of Boolean algebra (see discussion on following pages) to derive the following:

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A + AB = A A ( A + B) = A A + A B = A+ B 3. Design a circuit to perform the EXCLUSIVE OR function. Try to simplify the circuit so that you use the smallest possible number of NAND and NOR gates. Show your Boolean calculation. Check the result using truth tables. 4. Derive the truth table for a RS memory element made from two NOR gates. (See Fig. 9.4). Show the details of your derivation. 5. Design a 1KHz clock based on the type 555 TIMER chip. Make the low level pulses 1/4 period in length. Arrange that the clock can also be made to run at 1 Hz (for visual observation of LEDs) by substituting a larger capacitor. Predict the output for the NAND gate in Fig. 9.10 for VB=0 or 5 V (see Figs. 9.6 and 9.10) 6. A JK flip-flop with J=K=1 and CLR=1 is driven at the clock input by 1 KHz pulses from the NAND gate following the TIMER. Diagram the waveforms for the clock and the Q output on the same time scale. (See Fig. 9.5 and 9.11).

Experimental Details
7400 Series TTL Chips Logic Levels. For the TTL family, logical 0 is 0 V and logical 1 is 5 V, ideally. In practice, LOW is roughly 0.4 V and HIGH is 3.5 V. DIP Packages. DIP means dual-in-line arrangement of pins. This is the type of chip package that plugs into your circuit board. A DUAL chip means that there are two elements of the same kind in one package, QUAD means four and HEX means six. Straighten the pins gently before you plug into the board. Lever out with a screwdriver. Power supply. Check your power supply before connecting to the circuit board: Normal supply voltage: Absolute maximum: Current: Types 7400, 7402, 7404: Type 7486: +5.0 V +5.5 V 12mA per chip. 30mA per chip.

Output. The output from each individual gate can drive up to ten other TTL inputs. This is called the fan-out number. The output is delayed 10 nsec after the input for the INV, NAND, and NOR gates. The delay is 18 nsec for the EXCLUSIVE OR, and 25 nsec for the JK flip-flop. 9.10 Fall 1999

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Pin Layouts. Each chip has a dot or notch to indicate the ends at which pins 1 and 14 are located. The pin numbers increase sequentially as you go counter-clockwise around the chip in a top view. In 14 pin chips, Pin 7 is always grounded (0 V) and Pin 14 is always connected to the +5 V supply.

Fig. 9.8. Pin arrangements for TTL chips. Suggestions Power Supply. Set the voltage to 5 V BEFORE connecting to the circuit board. A previous user may have left it on 15 V. The logic chips burn out around 6 V. If the voltage drops when you connect to the circuit, DO NOT TRY TO INCREASE V. Increase the current limit instead. Decoupling of Voltage Spikes: Fast voltage spikes originating from electrical machinery in the building, or from other chips on the board, can be transmitted through the power lines to your circuit board and/or other chips, and cause unwanted triggering of the flip flops. As a precaution, always mount a capacitor of at least 0.1 f between the +5V line and ground on your circuit board at each chip. Data Records in the Logic Labs: For the experiments in the logic labs, write in your lab book the circuit, the Boolean equation that expresses its function, and the predicted truth table beforehand. Enter the observed logical values of the outputs in an adjacent, but separate column. It is important to have the observed result along-side the predicted ones. Particular discrepancies can suggest where to look for the wiring errors or damaged gates. Logical inputs and observation of logical outputs with LEDs: Input logical values can be set by connecting wires from the gate inputs to either 0 V (logical 0) or 5 V (logical 1). The logic level of the output can be observed using a light emitting diode (LED) which is connected 9.11 Fall 1999

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from the output to ground. The LED lights up when the output is +5 V and is off when the output on 0 V. The cathode of the LED is grounded, and must always have a 470 to 680 resistor in series to limit the current and prevent burnout. A bank of ten LEDs in a DIP package (type MV57164) is available. We suggest that you keep one bank of LEDs on your board throughout the logic experiments. The pin diagram is given below.

LED Test Circuit

A B Y= A+B LED 1 0 0 0 ON OFF OFF OFF

0 1 0 1

0 0 1 1

A B

MV57164 Outputs from gates connect on this side. 0V is OFF, 5V is ON

10 9 8 7 6 5 4 3 2 1

External resistors 470 to 680 ohms.

Fig. 9.9. LED test circuit.

The Experiment
LED testing

Before doing anything else, check that each LED lights up when the positive end is connected to the 5 V supply. If it fails to light, check the polarity. The truth tables in most parts of the experiment will be verified in this way. Truth tables for the TTL gates Verify the truth tables for the NAND (7400), NOR (7402), and INVERT (7404) gates, using the LED indicators. Connect a NAND gate so that it performs the INVERT function. Do this for a NOR gate also. This trick will be convenient in effecting economies in complex circuits.

Occasionally you will find a non-functioning gate. Label the chip immediately. Throw the complete chip into the trash if an instructor confirms your diagnosis. Remember however, that most problems arise from wiring mistakes. The EXCLUSIVE OR circuit Verify the truth tables for an EXCLUSIVE OR chip (7486). Now build and test the XOR circuit of your own design using only the NANDs and NORs.

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The RS memory Build the RS memory from two NOR gates. Compare the observed truth table with your predicted table, using LED indicators. Demonstrate the memory property by going through a complete memory cycle: Set (R = 0, S = 1), Store (0, 0), Reset (1, 0), Store (0, 0), Set (0, 1). Examine the effect of the illegal input (R = 1, S = 1), for different initial states of the RS system.

The TTL digital clock Build the 1 KHz digital clock using a 555 Timer according to your design in problem 4. Verify with the oscilloscope that the frequency, the pulse length of 250 sec, and the nominal 5 volt amplitude are approximately correct. Check that a suitable large capacitor placed in parallel with the existing one converts the clock to 1 Hz. Set up a NAND gate to control the transmission of clock pulses by means of a DC logical 0 or 1 control voltage. The output pulses for the NAND should be positive. Convert to an electronic stopwatch, using the counter / timer and the front panel switch for start and stop.

10X Probe 555 Clock

SCOPE CH. 4./ Trig. CH. 1.

5V 0V

VB Panel Switch

Counter/ Timer

Set to Totalize

Fig. 9.10. Digital clock and stop-watch. The JK Flip-flop. Construct an empirical truth table for the JK from your observations using the LED indicators. Since the output depends upon the previous state, Q , you will need to tabulate Qn +1 for both possible previous states, Qn = 0 and Qn = 1 . We suggest that you add a redundant column, Qn + 2 , (see truth table in Fig. 9.5)to get a better feel for the behavior of the flip-flop.

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Set CLR = 1 and J = K = 1. Now drive the clock input of the JK with 1 KHz pulses from your TIMER circuit. Use the oscilloscope to observe the clock input (positive pulses out of the NAND gate), and the output, Q, of the JK. What happens when J = K = 0?

Wires from 5V or 0V 555 Clock J C K 5V 0V Panel Switch CLR 5V or 0V Q Q

SCOPE CH. 1.

CH. 4./ Trig.

Fig. 9.11. JK test circuit.

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