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VLSIGuru Online Training Course Brochure

1. Courses offered (Number of sessions(2Hr 15 min), Start date, Course Duration):

a. System Verilog Training (13 Sessions, 9/Sep, 4 Weeks)

a. Introduction to VLSI & SoC Design

b. Introduction to SoC & Module level functional verification

c. System Verilog constructs

d. Standard Protocol Training(AXI, AHB, OCP, etc)

e. Verification IP(VIP) development for above protocol

f. Industry standard SV based verification project from scratch (Memory Controller, bridge protocols, USB2.0, similar complexity projects)

b. Methodology Training (13 Sessions, 20/Aug, 4 Weeks)

a. SoC & Module verification testbench setup using Methodology

b. Methodology(UVM & OVM) constructs

c. Standard Protocol Training(AXI, AHB, OCP, etc)

d. Universal Verification Component(UVC) development for above protocol

e. Industry standard project methodology & SV based verification project from scratch (Memory Controller, bridge protocols, USB, etc of similar complexity)

c. VLSI Training for Functional Verification (35 Sessions, 9/Sep, 11 Weeks)

a. System Verilog Training (#a above)

b. Methodology Training (#b above)

c. SoC Verification concepts

d. ARM architecture concepts

e. Peripheral Bus Protocol Training(PCIe Gen3, USB3.0, etc)

f. Peripheral Bus based design test bench setup concepts

g. PERL Training specific to functional verification

d. Standard Protocol Training(10 Sessions, 9/Sep, 3 Weeks )

a. AXI4.0, OCP3.0, AHB2.0, PCIe Gen3, USB3.0, etc

b. Verification IP development for 1 of above protocols

2. Material & assistance during course:

Access to questasim license installed on our servers

Checklist for each session of course(summary of each session)

Course material softcopy

Course assignment(VIP development, SV & Methodology practice, Industry standard project)

3. What student will be capable at end of course?

Complete understanding on SV, Methodology, Standard Protocol concepts

Verification IP development using SV & Methodology for any standard protocol(AXI, AHB, USB etc)

Ability to drive functional verification for a given module from scratch

4. Online Training Frequency Asked Questions?

Do you organize a demo class for online training?

o Yes, we organize a demo class 1 week prior to course commencement date.

Course prerequisites?

o

Exposure to Verilog HDL, digital design concepts

o

Exposure to OOP is added advantage, but not expected

Does course have practical aspects covered?

o

Course is majorly focused on learning practical aspects of SV, Methodology.

o

Verification environment is build from scratch for Ethernet Frame loopback design. This is done towards learning different aspects of SV & Methodology.

Access to the tools during course and after course completion?

o Student will have access to the required tools both during course and after the course.

Is the Projects executed complex enough to be put in resume?

o

All the projects executed can be put in resume. Industry requires 2-4 engineers working for 4-6 months to complete those projects.

o

Please download Project Execution Flow PDF

Each Session Duration & timings?

o Session duration: 2Hours 15 minutes; Timing is based on student preference.

Do you have online tutor or Recorded lectures?

o All our sessions are done by an online tutor.

Will I benefit from the course?

o Course is framed keeping the current industry requirements in mind; rest depends on your motivation to learn things, practise on assignments.

Missed sessions?

o

We try to compensate by doing an additional session.

o

Student has option to redo whole course for next 1 year at no additional cost.

Will I be perfect with SV, UVM, and Standard protocol after 2months of training?

o

It takes lot of effort from student to get perfection on SV, Methodology and standard protocols. We just give the required guidance in putting student’s efforts in right direction.

o

Student is expected to put required effort in reading the documents provided during course and complete assignments provided during the course.

Online Trainer profile?

o

IIT Graduates, 9+ years exp

o

Wide experience of working in different domains across Chip Design Industry.

Placement assistance?

o We do not give any commitment on placements; however we provide reference in different companies.

5. Fee Payment?

Student should attend demo session one week prior to course commencement date.

Student should register for course by transferring fee online before the course commences.

6. Contact Details

Mail : contact@vlsiguru.in

Phone: +91-9986194191