digital

Number system 1. Decimal number 15 in binary number system can be written as (A) 1111 (B) 1110 (C) 1100 (D) 1000

2. Decimal number 163.875 in binary number system can be written as (A) 10100001.111 (B) 10100011.111 (C) 11100011.111 (D) 10100011.101

3. Decimal number 15 in octal number system can be written as (A) 15 (B) 17 (C) 27 (D) 7

4. Decimal number 15 in octal number system can be written as (A) 15 (B) 17 (C) 27 (D) 7

5. Decimal number 378.93 in octal number system can be written as (A) 572.7342 (B) 573.7341 (C) 572.7341 (D) 570.7341

6. Decimal number 20 in hexadecimal number system can be written as (A) 14 (B) AA (C) A1 (D) D

7. Decimal number 2598.675 in hexadecimal number system can be written as (A) A21.ACCC (B) A26.ACCC (C) A21.ABCC (D) A21.ACC8

8.Binary number 1010 in decimal number system is equivalent to (A)13 (B) 19 (C) 10 (D) 23

9.Binary number 11011.101 in decimal number system is equivalent to (A)27.625 (B) 25.625 (C) 27.615 (D) 27.675

10.Binary number 1011 in octal number system is equivalent to (A)13 (B) 19 (C) 10 (D) 23

11. Binary number 110101.101010 in octal number system is equivalent to (A) 60.52 (B) 60.25 (C) 65.54 (D) 65.52

12.Binary number 10111 in hexadecimal number system is equivalent to (A)13 (B) 19 (C) 17 (D) 23

13 .Binary number 01011111011.011111 in hexadecimal number system is equivalent to (A)2FC.A7 (B)2FB.7C (C) 2AB.C7 (D) 2CF.7A

14. The octal number 16 in decimal number system is equivalent to (A)13 (B) 19 (C) 17 (D) 14

15. The octal number 4057.06 in decimal number system is equivalent to (A)1196.0946 (B) 1095.0948 (C) 2095.0937 (D) 2094.937

16. The octal number 367 in binary number system is equivalent to (A) 11110111 (B) 11110101 (C) 11010111 (D) 111110111

17. The octal number 367.52 in binary number system is equivalent to (A) 11110111.101010 (C) 11010111.1010 (B) 11110101.10110 (D) 111110111.10110

18. The octal number 756.603 in hexadecimal number system is equivalent to (A) 1AE.C18 (B) 1EEE.C18 (C) 11EE.C18 (D) 1EE.C18

19. The hexadecimal number A0F9.0EB in decimal system is equivalent to (A) 41209.0572 (B) 41309.0572 (C) 41219.0572 (D) 41209.0562

20. The hexadecimal number 3A9E.B0D in binary number system is equivalent to (A) 0011101010010110.1011100001101 (C) 0011101010011110.1011100001101 (B) 0011101010011110.1010100001101 (D) 0011101010111110.1011100001101

21. The hexadecimal number B9F.AE in octal number system is equivalent to (A) 5627.534 (B) 5637.544 (C) 5637.634 (D) 5637.534 22. The 9s compliment of the decimal number 782.54 is. (A) 217.45 (B) 217.15 (C) 218.45 (D) 218. 51 23. The 10s compliment of the decimal number 1056.074 is. (A) 8943.924 (B) 8043.926 (C) 8943.926 (D) 8953.926

24.Binary 111.111 when subtract from binary 1010.01, the result in binary is (A) 10.011 (B) 0010.011 (C) 110.011 (D) both (a)&(b)

25. Binary 111 when added to binary 1010 is (A) 101110 (B) 10110 (C) 10001 (D)100010.

26. Binary 1100 multiplied by binary 101 gives (A)111100 (B) 100100 (C) 1000000 (D)10110000

27. Which of the following is not valid in binary system? (A)0 x 0 = 0 (B) 0x1=1 (C) 1 x 1 = 1 (D) All of these

28. Which of the following is not valid in binary system? (A)0 + 0 = 0 (B) 0 +1 = 1 (C) 1 + 1 = 1 (D) All of these

29. Which of the following is not valid in binary system? (A) 0 - 0 = 0 (B) 0 -1 = 1 (C) 1 - 1 = 0 (D) All of these

30. Which binary addition is incorrect? (A) (B) (C) 1001.1 + 1011.01 1000101 + 1000101 0.1011 + 0.1101 = = = 10100.11 1001010 1.1000

(D)

1011.01 + 1001.11

10100

31.The digit 0 with carry of 1 is the sum of binary addition? (A) 1 + 1 (B) 1 + 0 (C) 0 + 1 (D) 0 + 0

32.The digit 1 with borrow of 1 is the result of binary subtraction? (A) 1 + 1 (B) 1 + 0 (C) 0 - 1 (D) 0 + 0 33.Binary number 1011 when converted to its 1s complement will become (A) 0010 (B)0100 (C)1000 (D)1100

34. Find the 2s complement of 100110? a. 011011 b. 011010 c. 01101 d.001101

35.Binary number 11011.01 when converted to its 2s complement will become (A)0101.110 (B)01111.10 (C)01100.10 (D)00100.11

36.The sum of 1110102 and 110112 in decimal form will be (A) 65 (B) 75 (D) 95

37.In decimal system the base or radix is (A)0 (B)1 (C)10 (D)e

38.The radix of a hexadecimal system is (A) 2 (B) 3 (C) 8 (D) 16

39.In octal system the base or radix is (A)2 (B)8 (C)10 (D)e

40. How many 1s are present in the binary representation of 3 x 512 + 7 x 64 + 5 x 8 + 3 = ? a. 8 b. 9 c. 10 d. 11

41. The number of bits in the binary required to represent the decimal number 28 is a) 3 b)4 c) 5 d)6

42. In the binary number 110.101 the fractional part has the value a) 0.125 b) 0.625 c) 0.875 d) 0.5 43. 1s complement representation of decimal number of -17 by using 8 bit representation is (A) 1110 1110 (B) 1101 1101 (C) 1100 1100 (D) 0001 0001 44. The chief reason why digital computers use complemented subtraction is that it (A) Simplifies the circuitry. (B) Is a very simple process. (C) Can handle negative numbers easily. (D) Avoids direct subtraction.

45.The sum of 1110102and 110112 in decimal form will be (A) 65 Binary codes 1. Which one of the following is example for alphanumeric code (A)01011 (B) 01A34 (C)1111 (D) none (B) 75 (C) 85 (D) 95

2. Which one of the following is example for alphanumeric code (A)EBCDIC (B) gray code (C)XS-3 code (D) none 3. A BCD code is .. (A) group of 4 binary bits (B) binary bit (C) group of 3 binary bits (D) none 4. A sequence of binary digits which represents a decimal digit is called. (A) code word (B) BCD code (C) binary bits (D) none 5. In every positively weighted code , the first weight must be (A) 2 (B) 1 (C) 0 (D) any of the above 6. In every positively weighted code , the sum of all the weights must be equal to or greater than . (A) 10 (B) 9 (C) 0 (D) 8 7. The code is example for positively weighted code (A) 642-3 (B) 631-1 (C) 84-2-1 (D) 8421 8. The code is example for non-weighted code (A) Gray code (B) 631-1 (C) 84-2-1 (D) 8421 9. The code is example for sequential code (A) 5211 (B) 2421 (C)642-1 (D) 8421 10. The code is example for self complimenting code (A) 5421 (B) XS-3 (C) 8421 (D)none of the above 11. The code is example for cyclic code (A) 5421 (B) XS-3 (C) gray (D)none of the above

12.10 in 8421 BCD code is represented as (A) 1010 (B) 0001000 (C)010111 (D) None

13. Express the 100000111001.1001 8421 BCD number as decimal (A) 839.9 (B) 939.4 (C)839.5 (D)829.9 14. XS-3 code has invalid states (A) 3 (B) 9 (C) 6 (D)2

15. Express the 247.6 decimal number in the XS-3 code (A) 1101 0111 1010. 1001 (C) 0101 0111 1010. 1001 (B) 0101 0111 1010. 1101 (D) 0101 1111 1010. 1001

16. Express the 0110 1000 1100. 0111 XS-3 code as decimal (A) 559.4 (B) 459.4 (C)449.4 (D)359.4

17.Which of the following statements is correct ? (A) Decimal 9 is represented as 1011 in Excess 3 code (B) Decimal 9 is represented as 1001 in BCD code (C)Decimal 10 is represented as 1100 in Gray code (D)Decimal 10 is represented as 1001 in binary code 18. The equivalent gray code for binary number 1010 is (A) 1101 (B) 1011 (C) 1110 (D) 1111 19. The equivalent binary number for gray code 1011 is (A) 1101 (B) 1011 (C) 1101 (D) 1111

20. Express the decimal number 4 in the XS-3 gray code (A) 0100 (B) 0111 (C) 1010 (D) 0001

21. In an even parity scheme, which of the following words contain an error? (A) 10101010 (B) 11110110 (C) 10111001 (D) 11011011

22. In an odd parity scheme, which of the following words contain an error? (A) 10111010 (B) 11110110 (C) 10111001 (D) 11011001 23. ASCII code basically a. bit code (A) 7 (B) 4 (C) 2 (D) 8

24. Positive logic in a logic circuit is one in which (A) logic 0 and 1 are represented by 0 and positive voltage respectively. (B) logic 0 and 1 are represented by negative and positive voltage respectively (C) logic 0 voltage level is higher than logic 1 voltage level. (D) logic 0 voltage level is lower than logic 1 voltage level. Gates 1. Which logic function has the output low only when both inputs are high? (A)OR (B)NOR (C)AND (D)NAND

2.The Boolean function for the AND gate is (A) A + B = Y (C) = Y (B) AB = Y (C) = Y

3.The Boolean function for the OR gate is (A) A + B = Y (C) = Y (B) AB = Y (C) = Y

4.The Boolean function for the NAND gate is

(A) A + B = Y (C) = Y

(B) AB = Y (C) = Y

5.The Boolean function for the NOR gate is (A) A + B = Y (C) = Y (B) AB = Y (C) = Y

6. Bubbled OR gate is equivalent to. (A)OR (B)NOR (C)AND (D)NAND 7. Bubbled AND gate is equivalent to. (A)OR (B) NOR (C) AND (D)NAND

8.The Boolean function for the X-OR gate is (A) (B) AB = Y (C) (C) = Y (C) = Y (C) = Y

9.The Boolean function for the X- NOR gate is (A) (B)

10. Which one of the following gate shows high output when both the inputs are equal (A)X-NOR (B)X-OR (C)AND (D)NAND

11. Which one of the following gate shows high output when both the inputs are not equal (A)X-NOR (B)X-OR (C)AND (D)NAND 12.The gate that assumes the 1 state, if and only if the input does not take a 1 state is called.. (A) AND gate (C) NOR gate (B) NOT gate (D) Both (B) & (C)

13. When an input signal A=11001 is applied to a NOT gate serially, its output signal is (A) 00111. (B) 00110. (C) 10101. (D) 11001. 14. How many AND gates are required to realize Y = CD+EF+G (A) 4 (B) 5 (C) 3 (D) 2

15.How many two input AND gates and two input OR gates are required to realize Y = BD+CE+AB (A) 1, 1 (B) 4, 2 (C) 3, 2 (D) 2, 3

16. Which logic gate is similar to the function of two parallel switches? (A) AND (B) NAND (C)OR (D)NOR

17. In case of OR gate, no matter what the number of inputs, are (A) 1 at any input cause the output to be at logic 1 (B) 1 at any input cause the output to be at logic 0 (C) 0 at any input causes the output to be at logic 0 (D) 0 at any input causes the output to be at logic I 18. A combination of and function and not function results in

(A)OR gate (C) NAND gate

(B) (D)

inversion NOR gate

19.A logic circuit corresponding to sign is + sign is (A) AND (B) NOR ( c)NAND (d) OR

20. Inverter gate is also known as a) All gate c) OR gate b) NOT gate d) NAND gate

21. Which gate is commonly used as an equality detector? a) AND b) OR c) XOR d) XNOR

22. When one input of a gate is high then output goes to high, the gate is a) NOR b) NAND c) OR d)NOT

23. A NAND & NOR gate is called a universal logic element because (A) it is used by every body (B) any logic function cane be realized by NAND & NOR alone (C) all the minimization techniques are applicable for optimum NAND & NOR gate realization. (D) many digital computers use NAND & NOR gates 24.Thwbubble or small circle, on the output of the NAND gate and NOR gate represents. (A)Addition (C)Product (B) (D) Substraction Complementation

25. The output of a logic gate is 1, when all its input are at logic 0, the gate is either a NAND or an EX -OR gate b. a NOR or an EX-OR gate c. AND or an EX-NOR gate d. a NOR or an EX-NOR gate Boolean algebra 1.A minterm is (A) the minimum term in a Boolean function (B)a prime implicant (C)always smaller than a maxterm (D) each product term in the SOP form 2.According to Boolean algebra which of the following relation is not valid? (A)X + X = X (B) 0. X= 0 (C)1. X= X (D) X . X = 1

3.According to Boolean algebra which of the following relation is not valid?

(A) X (YZ) = (XY) Z (C)X + XZ = X

(B)X (Y +Z) = XY + XZ (D) X (X + Y) = 1

4. According to Boolean algebra which of the following relation is not valid? (A) X (X + Y ) = X (C) X+ XY = X+Y 5.A (A + B) is the same as (A) A (B)B (C)AB (D)A + AB 6.In Boolean algebra. A + A+ A+ A + + A is the same as (A)1 (B)nA (C) A (D) Infinary (B) (X + Y) (X+Z) = X + YZ (D) XY+ Z+YZ= XY+ Z

7.If A = 0.B = 0. Then AB is (A) 1 (B)0 (C) 10 (D) none 8. the Boolean expression A+B=B+A is.. (A) commutative law (C) distributive law (A) = + (A) = + (A) + (B)associative law (D)idempotence law (C) = (C) = (C) + (D) = (D) =

9. De Morgans first law state that (B)= (B)= (B) 10. De Morgans second law state that 11. The De Morganised expression for is (D) P+QR 12. The sum term in the standard POS form is called.. (A) mintern (B)logic expression (C)maxterm (D)All of the above 13. A two variable expression can have . Possible combinations of the input variables A and B (A)4 (B)2 (C)8 (D)16 14. A two variable K map has.. number of cells (A)4 (B)2 (C)8 (D)16 15. A 4- square in K map is called (A) octet (B)quad (C) square (D)pair 16. The bit distance between all odd numbered columns in the K map is a ) not fixed c) always two 17. In logical addition 1+1 is a) 1 b) 0 c) 1 with carry 1 d) 1 with carry0 18. An octet in K map eliminates .. variables b)always one d)not specified

(A)3

(B)2

(C)1

(D)4 (C) . .

19. The dual of the Boolean expression: x + y + z is (A) x .y + z (B) x + yz (D) x.y.z 20. The three variable Boolean expression xy + xyz + y + y z in reduced for is (A) x + yz (B) z+ yz (C) y (D) none 21. A literal in Boolean Algebra means (A) a variable in its uncomplemented form only (B) a variable ORed with its complement (C) a variable in its complemented form only (D) a variable in its complemented or uncomplemented form 22.According to Boolean algebra which of the following relation is not valid? (A)x (y z) = (xy) z (C)x + xz = x (B)x (y + z) = xy + xz (D)x (x + y) = 1

23.The complements of (A + BC + AB) will be (A) (C) B (A +C) A (B + C) (B) ABC

(D) (A+B)C

24. A minterm of the Boolean-function, f(x, y, x) is (A) x + y + z (C) x z (B) x y z (D) (y +z) x

25. Karnaugh map is used for the purpose of (A) Reducing the electronic circuits used. (B) To map the given Boolean logic function. (C) To minimize the terms in a Boolean expression. (D) To maximize the terms of a given a Boolean expression. 26.Write the boolean expression (in sum of products form) a logical circuit when will have all output high when X = 0, Y = 0 and Z = 1 and (A) (C) X+Y+Z XYZ + XYZ (B) (D) X = 1, Y = 1 and Z = 0 and a 0 output for all other input states XYZ + XYZ XYZ

Combinational circuit 1. A half-adder is an arithmetic circuit that adds.. binary digits (A)2 (B)3 (C)5 (D)4 2. A full-adder is an arithmetic circuit that adds.. binary digits (A)2 (B)3 (C)5 (D)4 3. A parallel adder adds two numbers in parallel form and produces the sum bits in .. form

(A)serial

(B)parallel

(C) both in serial and parallel

(D) cannot say

4. The look-ahead carry adder speeds up the process by eliminating the.. (A)sign bit (B) first bit 5. In a full adder, there are a) Two binary number inputs and two outputs b) Three binary digit inputs and two binary outputs c) Three binary inputs and three binary outputs d) None of these 6. . adders are used where circuit minimization is more important than speed (A)parallel (B) ripple carry (C) full (D) serial (C) ripple carry (D) carry

7. The expression for sum in half adder can be made by a) Ex-NOR b) EX- OR c) OR d) AND 8. A .. is a logic circuit that compares the magnitude of 2 binary numbers (A) adder (B) comparator (C)decoder (D) encoder 9. A .. is a logic circuit that converts an n- input binary code into a corresponding single numeric code (A) multiplexer (B) decoder (C)encoder (D) de-multiplexer 10. are used to control the operation of the encoder (A) control input (B) clock (C)enable input (D) none of these

11. The number of full - address in a 4-bill parallel adder will (A)two (B) three (C)four (D) five

12. A half adder includes (A) a NAND with OR gates (C) only AND gate (B) a AND with XOR gates (D) neither OR nor XOR nor AND gates

13. The sum in the half adder can be produced by using . gate (A) AND (B) NAND (C) X-OR (D) X-NOR 14. The carry in the half adder can be produced by using . gate (A) AND (B) NAND (C) X-OR (D) X-NOR 15. The full adder can be realized using (A) 2 half adder & 1 X-OR gate (C) 2 half adder & 1 X-NOR gate (B) 2 half adder & 1 AND gate

(D) 2 half adder & 1 OR gate

16. The number of NOR gate required for realizing a full sub tractor is a) 11 b) 12 c) 5 d) 10

17. The logic circuit is. in which one output line is active at a time for each one of the possible combination of inputs (A) DECODER (C) MULTIPLEXER (C) 2n (B) ENCODER (D) DEMULTIPLXER (D) n2

18. For n input lines there are number of output lines for a decoder circuit A) n (B) 2n 19. The decoder in enabled only when the ENABLE is A) high (B) low (C) inhibit (D) none of these 20. An . is a device whose input are decimal or alphabetic character and outputs are coded representation those inputs (A) DECODER (C) MULTIPLEXER 21. A demultiplexer consist of a) 1 input n selection lines and 2n outputs. b) n inputs, 1 selection line and 2n outputs. c) 1 input,2n selection lines and n outputs d) 2n inputs,1 selection line and n outputs. 22. An octal to binary encoder has . Number of input and . Number of output lines (A) 8,3 (B) 3,8 (C) 4,8 (D) 8,3 23. A .. is a logic circuit that accepts several data inputs and allows only one of them at a time to get through the output (A) multiplexer (B) decoder (C)encoder (D) de-multiplexer 24. The 8 input multiplexer required number of data select inputs (A) 4 (B) 3 (C) 8 (D) 2 25. is a logic circuit that channels its data input to one of several data outputs (A) multiplexer (B) decoder (C)encoder (D) de-multiplexer 26. The 1-line to 8 line de- multiplexer requires number of select inputs (A) 4 (B) 3 (C) 8 (D) 2 (B) ENCODER (D) DEMULTIPLXER

27.The device which changes from serial data to parallel data is (A) COUNTER (B) MULTIPLEXER

(C) DEMULTIPLEXER (D) FLIP-FLOP 28. A device that converts from decimal to binary number is called (A)decoder (B)encoder (C) CPU (D) converter

29. A device which converts BCD to Seven Segment is called (A) Encoder (C) Multiplexer (B) Decoder (D) Demultiplexer

30. Which one of the following used to change data from special code to temporal code a.Shift registers c.A/D converters Flip flops 1. A Flip flops is known more formally as a multivibrator (A) bistable (B) astable (C) monostable (D) none of these 2.In any flip-flip, when the Q output is 1, what is the state of the terminal (A) 0 (B) 1 (C) Either 1 or 0 (D) Q 3. If both the inputs of a SR latch are made low the state of the latch is.. (A)RESET (B)SET (C) No change (D) invalid 4. The active low SR latch can be constructed using.. gates (A)two OR (B)two X-OR (C) two NAND (D) any of the universal 5. The.. flip-flop is the most versatile and most widely using (A)T (B)S-R (C) D (D) J-K b. Counters d. Combinational ckts

6. Which of the following is example for asynchronous inputs? (A) CLOCK & CLEAR. (C) PRESET & CLOCK (B)PRESET & CLEAR (D) data inputs

7. If both the inputs of a JK flip-flop are made high the state of the flip-flop is.. (A)RESET (B)SET (C) No change (D) Toggle

8. A clock pulse may undergo varying degree of delay before it arrives at the flip-flop is called.. (A)delay time (B)race around (C) clock skew (D) race around 9. The propagation delays are usually in the range of.. (A)few ns to 1 s (B) few s to 1ms (C) (D) seconds

10. The MASTER-SLAVE flip-flop are used to avoid (A) propagation delay (B) clock skew (C) logic race (D) none of these 11. A flip-flop can store .. bit(s) of data (A)2 (B)any (C) 1 (D) 4

12. The variables in Boolean algebra can take (A) any number of values

(B) and one of the ten values 0 through 9 (C) one of the two possible values (D) none of the above. 13.The D Flip flop and T flip flop are respectively used as a)Toggle switch and delay gate b) Delay and Toggle switch c) Both used as delay gates D) Both used as toggle switch 14. For NOR circuit SR flip flop the not allowed condition is ________. (A) S=0, R=0. (B) S=0, R=1. (C) S=1, R=1. (D) S=1, R=0. 15. In an unclocked R-S flip-flop made of NOR gates, the forbidden input condition is (A) R = 0, S = 0 (B) R = 1, S = 0 (C) R = 0, S = 1 (D) R = 1, S = 1 16. By replacing an inverter between both input of an S-R flip-flop, it becomes a. JKFF b. DFF c. TFF d. Master slave JKFF

Shift registers Shift registers & Counters 1. A . Register is the simplest of registers (A)PIPO (B)PISO (C) BUFFER (D) n2 (D) SIPO 2. An n bit register can store . bit(s) of data (A) n (B)2n (C) 2n

3. which one of the following shift register convert serial data into parallel form (A)PIPO (B)PISO (C) BUFFER (D) SIPO 4. The number of clock pulses are required to store 4 bit data into 4 bit SISO shift register is (A)two (B) Three (C)Four (D) Eight 4. The number of clock pulses are required to store 4 bit data into 4 bit PISO shift register is (A)two (B) Three (C)Four (D) one 6. A universal shift register is register (A)SISO (B) PISO (C)BIDIRECTINAL (D) SIPO 7. Dynamic shift registers are made up of . (A)flip-flops (B) MOS inverters (C) gates (D) none of these

8. Which of the logic circuit having memory elements a) Encoder b) Shift register Counters c) gates d) comparator

1. asynchronous counter is also called . counter (A) simple (B) ripple (C) ring (D) Johnson 2. Asynchronous counter uses . FFs to perform a counting function A) any flip-flops (B) D (C) SR (D) T 3. Each of the counts of the counter is called of the counter A) modulus (B) state (C) terminal state (D) none of these

4. The number of state through which the counter passes before returning to the starting state is called of the counter A) modulus (B) state (B) 2n (C) 2n (B) 2n (C) 2n (C) terminal state (D) n2 (D) n2 (D) none of these 5. An n bit counter has state A) n 6. An n bit counter has flip flops A) n

7.How many flip-flops are needed for a 4-bit counter? (A)Two (B)Three C) Four (D) Six (D) n2 (D) n2 8. An n bit counter divides input frequency by A) n A) N 2n (B) 2n (C) 2n 9. The number FFs required to construct a mod-N counter is. (B) N2n (C) 2n

Where n is the number of bit 10. A counter which goes through all the possible state before restarting is called.counter A) full modulus (B) variable modulus (C) terminal (D) ripple 11. The final state of the counter sequence is called the. A) modulus (B) state count (C) ripple count (D) terminal count 12. A binary ripple counter is required to count up to 1024, the number of FFs required is A) 10 (B) 8 (B) 2n (C) 2n (B) 2n (C) 2n (C) 14 (D) n2 (D) n2 (D) 20 13. An n bit ring counter has ..number of state A) n 14. An n FF Johnson counter can have number of state A) n

15 When a counter contain 3 flip flop the maximum value of count is A) 1000 b) 11 c) 111 d) 1111 16. A Decade counter is also called counter

A) mod-10

(B) mod -12

(C) mod-14

(D) ripple counter

17. The minimum number of flip-flops required to construct a mod-75 counter is (A) 5 (B) 6 (C) 7 (D) 8

18. A 4-bit synchronous counter uses flip-flops with propagation delay times of 15 ns each. The maximum possible time required for change of state will be (A) 15 ns. (B) 30 ns. (C) 45 ns. (D) 60 ns.

19. How many flip-flop circuits are needed to divide by 16? (A)Two (B) Four (C) Eight (D) Sixteen

20. The minimum number of flip flop required in a counter to count 60 pulses is a) 4 b) 6 c) 8 d) 10

21. A 5 bit up counter after 4 successive clock pulse has an output of 01010. Its output after 5th clock pulse is? a) 01010 b) 01110 c) 01011 d) 01101 edge triggering and clock is connected with

22. In an asynchronous counter design, it uses positive previous flip flop output, then the counter work as A) Decade counters b) up counter Logic families

c) Down counter

d) Synchronous counter

1. The .. is defined as that number of standard loads that the output of the gate can drive (A) threshold voltage (B) propagation delay (C) Fan in (D)Fan out 2. The .. is defined as the maximum umber of the inputs that the gate is designed to handle (A) threshold voltage (B) propagation delay (C) Fan in (D)Fan out 3. A common means for measuring and comparing the overall performance of an IC family is the .. (A) speed power product (C) Fan in (B) figure of merit (D)both (A) & (B)

4. Which of following consume minimum power (A) TTL. (B) CMOS. (C) DTL. (D) RTL. 5. Which of following consume maximum power (A) TTL. (B) CMOS. (C) MOS. (D) ECL. 6. The fan-out of a MOS-logic gate is higher than that of TTL gates because of its (A) low input impedance (B) high output impedance

(C) low output impedance (D) high input impedance 7. Which family of logic circuits uses field effect transistors? (A)TTL (B) CMOS

(C)Bothe TTL and CMOS

(D) Neither TTL nor CMOS

8. Which of the following is the fastest logic (A) TTL (B) ECL (C) CMOS (D) LSI

9. Which of the following is the slowest logic (A) TTL (B) ECL (C) CMOS (D) MOS

10. The digital logic family which has the highest propagation delay time is (A) ECL (B) TTL (C) CMOS (D) PMOS

11. The digital logic family which has the lowest propagation delay time is (A) ECL (B) TTL (C) CMOS (D) PMOS

12. Which of the following is the most widely used bipolar family? (A) DTI (B) TTL (C) ECL (D)All of the above.

13. Which one of the logic family having highest fan in a) TTL b) ECL c) CMOS d) IIL

14. Which one of the logic family having lowest fan in a) TTL b) ECL c) CMOS d) MOS

15. Which one of the logic family having lowest fan out a) TTL b) ECL c) CMOS d) IIL

16. Which one of the logic family having highest fan out a) TTL b) ECL c) CMOS d) IIL

17. Which one of the logic family having lowest noise margin a) TTL b) ECL c) CMOS d) MOS

18. Which one of the logic family having highest noise margin a) TTL b) ECL c) CMOS d) MOS

19. In digital ICs, Schottky transistors are preferred over normal transistors because of their (A) Lower Propagation delay. (B) Higher Propagation delay. (C) Lower Power dissipation. (D) Higher Power dissipation. 20. CMOS circuits are extensively used for ON-chip computers mainly because of their extremely (A) low power dissipation. (B) high noise immunity. (C) large packing density. (D) low cost. 21. The MSI chip 7474 is (A) Dual edge triggered JK flip-flop (TTL). (B) Dual edge triggered D flip-flop (CMOS). (C) Dual edge triggered D flip-flop (TTL). (D) Dual edge triggered JK flip-flop (CMOS).

22. MOS family used extensively where lowest power consumption is necessary is (A) PMOS (B) NMOS (C) CMOS (D) PMOS

23.The propagation delay for TTL gates is. a.1 nanoseconds c.50 nanoseconds ADC & DAC 1. Which of the following changes analog voltage to binary data? (A)A/D converter (C)Both (B) D/A converter (D) None of the above b. 9 nanoseconds d. 10 nanoseconds

2. Which converter has a binary input? (A)A/D (B) D/A (C) both (A) & (B) (D) none 3. The resolution of s 6 bit DAC is (A)1.5625% (B) 1.587% (C) 8.33% (D)2.77% 4. A 4- bit DAC has a step size of 25 mV the full scale output voltage is.. (A) 25 mV (B) 0.1 V (C) 0.8 V (D) 0.75 V 4. An 6 bit DAC produces Vout = 0.05 V for a digital input of 000001, the full scale output is. (A) 3.15 V (B) 0.8 V (C) 1 V (D) 0.75 V 6. An 6 bit DAC produces Vout = 0.05 V for a digital input of 000001, then Vout for 101010 is.. (A) 3.15 V (B) 2.10 V (C) 1 V (D) 0.75 V 7. The most popular DAC is (A) R-2R LADDER (C) SWITCHED -CAPACITOR (B)WEIGHTED-RESISTOR (D) SWITCHED CURRENT-SOURCE

8. Which of the following is the fastest ADC? (A) counter type (C) tracking type (B) flash type (D) successive approximation type

9. Which of the following is the most expensive ADC? (A) counter type (C) tracking type (B) flash type (D) successive approximation type

10. Which of the following is the slowest ADC? (A) counter type (C) tracking type (B) flash type (D) dual slope

11. Which of the following is the most widely used ADC? (A) counter type (C) tracking type (B) flash type (D) successive approximation type

12. The 3- bit flash type ADC requires . Number of comparators & . Number of resistors (A) 7& 8 (B) 8 & 8 (C) 1 & 8 (D) 7 & 1 13. The conversion time for 8 bit SA- type ADC is with the clock frequency of 1 Mhz frequency is. (A) 8ns (B) 8Ms (C) 8ms (D) 8s 14. The conversion time for 8 bit digital ADC is with the clock frequency of 1 MHz frequency is. (A) 255s (B) 8s (C) 255ms (D) 8ns