TA 8.

1 A Fully-Integrated Zero-IF DECT Transceiver

Frank Op t Eynde, Jan Craninckx, Paul Goetschalckx
Alcatel Microelectronics, Zaventem, Belgium This single-chip RF-transceiver for DECT provides a complete transmission and reception radio interface between the antenna and the baseband digital bitstream [1]. Integrated synthesizer, zero-intermediate frequency (zero-IF) receiver topology and digital modulation and demodulation, minimizes the number of external components: only an antenna filter and switch, a power amplifier, and decoupling. The local oscillator (LO) synthesizer uses a doublefrequency voltage-controlled oscillator (VCO) with integrated spiral coils and digital self-calibration for process variations. The integrated phase-locked loop (PLL) synthesizer has a fast settling and stays closed-loop for the direct-upconversion transmitter. This allows non-blind-slot operation in high-end base stations and multislot operation for high-speed asymmetrical data links. The IC is implemented in 0.35m BiCMOS, a technology choice that allows putting a large amount of digital processing on the radio transceiver. The chip includes A-to-D and D-to-A converters and digital (de)modulation. This reduces the number of external components by a large amount over known industry solutions. The baseband data is a synchronous bitstream, which gives compatibility with virtually any baseband processor. The IC uses 35mA in receive mode and 70mA in transmit mode from a 2.7 to 3.6V supply. The IC block diagram is shown in Figure 8.1.1. An important aspect in the design is the choice of a double-frequency VCO in the local oscillator PLL. This eliminates DC-offsets in the zero-IF receiver originating from LO-to-RF feedthrough, and avoids frequency pulling of the VCO during transmit. It offers a solution for the generation of quadrature LO signals required for I- and Q-mixing. The VCO resonates at 3.8GHz and uses an optimized symmetrical octagonal coil [2]. Only CMOS transistors are used in the resonator. Its phase noise spectrum is shown in Figure 8.1.2. Measured phase noise is -105dBc/Hz at 1MHz offset and 133dBc/Hz at 10MHz. Analog VCO tuning is with a standard p+/n-well junction diode varicap. At power-up, coarse self-calibrating digital tuning sets the correct center frequency, independent of process variations. The fourth-order, type-2 PLL with 175kHz loop bandwidth and integrated loop filter is capable of selecting 32 DECT channels. This includes the extended DECT frequency band from 1.88 to 1.938GHz. The measured PLL settling time for a 16-channel frequency shift is within 20s, as shown in Figure 8.1.3. From top to bottom the toggling MSB of the frequency control word, the lock indicator, and the VCO control voltage are displayed. This fast settling allows the use of this transceiver in a non-blind slot operation. The total current consumption of the synthesizer is below 10mA. Zero-IF topology is adopted in the receiver to minimize the number of external components. An integrated lowpass filter replaces the external SAW channel filter needed in heterodyne receivers. Received signal demodulation is in digital, eliminating the external components needed for a quadrature demodulation tank [3]. The LNA transistor schematic is shown in Figure 8.1.4. It is a simple cascoded common-emitter input stage, with a feedback resistor for input impedance matching. By using multiple input stages, the gain can be switched between 0, 12 and 24dB. The noise figure at maximum gain is 2.2dB, at 2.5mA consumption. The intermodulation performance of the combination of LNA and Gilbert-cell downconversion mixers is shown in Figure 8.1.5. With -20dBm input IP3, the circuit is within the DECT specification. Concerning the zero-IF offset problem, the DC signal after the mixer is in the

range of only a few mV. This remains well below the capability of the subsequent offset compensation circuit. Most channel filtering is performed in the 4th order 800kHz lowpass filters following the mixers. This large amount of analog filtering allows interferer signals as high as 39dBm in channel M+2 or-33dBm in channel M+3 to coexist with a wanted signal level in channel M of 96dBm. At power-up, the filter cutoff frequency is adjusted for process variations by an on-chip RC time constant calibration. The extremely low noise requirements are fulfilled at the expense of large capacitor values. Next in the receiver chain are the variable-gain amplifiers (VGA), which create signal levels fitted to the ADC input range. Since the accumulated offsets of the previous blocks would saturate the VGA outputs, an offset compensation loop is implemented. This loop, which is active during the DECT guard band time, ensures an offset voltage after amplification of less then 2LSBs. At the VGA outputs, I- and Q-signals are digitized with 8b, 6.9MSample/s ADCs. Further digital processing consists of a final channel filtering, demodulation, clock recovery, and RSSI extraction. With 5dB total receiver chain noise -96dBm sensitivity is obtained for 10-3 BER. This is 10dB better than required by the DECT specification. The total current consumption of the RX chain is 25mA. Direct upconversion topology is used for the transmitter. Compared with direct VCO modulation techniques, this offers the advantage of a synthesizer PLL loop that is never opened. As a result, the transmitter is resistant to parasitic effects such as PA pulling or mixing with the PA harmonics. Digital I- and Q-signals with a gaussian filter shape are derived from the TX input bitstream. The 8b 13.8MSample/s DACs then convert these two signals. Digital offset compensation and amplitude regulation removes LO leakage and mirror signal and set nominal output power. Subsequently, second-order analog low-pass filters with 1.6MHz cutoff frequency are needed to suppress out-of-band transmitted power. The resulting baseband signals are upconverted to RF using Gilbert-cell mixers (Figure 8.1.6). The LO switching transistors are isolated from the baseband input by cascode transistors, to avoid the second harmonic of the LO frequency at their emitters from modulating the baseband input and creating a parasitic component at the RF frequency. The baseband input stages are linearized with unityfeedback opamps and resistors for more than 35dBc harmonic suppression in RF signal. Even without the available offset compensation, both LO leakage and image suppression remain well below 30dBc. Finally, the differential output signals from the mixers are combined and amplified to drive a single-ended 50 load -6dBm. The total transmit chain current consumption is 60mA. A micrograph of the analog part of the 0.35m BiCMOS IC is shown in Figure 8.1.7. The technology provides 25GHz bipolar npn transistors, Metal/Metal capacitors and high-ohmic poly resistors. The VCO is situated in the upper left corner, as far away as possible from the RX input and TX output. The 3.8GHz VCO signal is distributed to the RX and TX mixers, and it is only locally divided to LO frequency. This reduces LO-to-RF coupling. To facilitate production testing, an analog test bus is foreseen. This enables testing most building blocks separately. The total die area is 18mm2, a large part of which is taken up by the RX analog low-pass channel filter.

References:

[1] European Telecommunications Standards Institute, Digital Enhanced Cordless Telecommunications; Common Interface; Part 2: Physical Layer, EN 300 175-2, February 1998. [2] Craninckx, J. and M. Steyaert, A 1.8GHz Low-Phase-Noise CMOS VCO Using Optimized Hollow Inductors, IEEE Journal of Solid-State Circuits, vol. 32, no. 4, pp. 736-744, May 1997. [3] Bopp, M. et al., A DECT Transceiver Chip Set Using SiGe Technology, Proceedings of the IEEE International Solid-State Circuits Conference 1999, pp. 4.2.

2000 IEEE International Solid-State Circuits Conference

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2000 IEEE

Figure 8.1.1: Transceiver block diagram.

Figure 8.1.2: Measured VCO phase noise spectrum.

Figure 8.1.3: Measured PLL settling behavior.

Figure 8.1.4: Low-noise amplifier circuit schematic.

Figure 8.1.6: Upconversion mixer schematic.

Figure 8.1.5: Measured RX intermodulation performance.

2000 IEEE International Solid-State Circuits Conference

07803-5853-8/00

2000 IEEE

Figure 8.1.7: IC micrograph.

2000 IEEE International Solid-State Circuits Conference

07803-5853-8/00

2000 IEEE