Digital Integrated

Digital Integrated
Circuits
Circuits
A Design Perspective
A Design Perspective
Designing Sequential
Designing Sequential
Logic Circuits
Logic Circuits
Mux
Mux
-
-
Based Positive Latch
Based Positive Latch
CLK
CLK
CLK
D
Q
CLK = 1, latch is transparent
CLK = 0, latch retains data
Sizing of transistors is not critical for realizing correct functionality since feedback
loop will be open when sampling data (no contention).
Not power efficient since it presents a load of 4 transistors to the CLK signal
Mux
Mux
-
-
Based Positive Latch
Based Positive Latch
NMOS only
CLK
CLK
Q
M
Q
M
Reduced CLK load to two transistors.
Drawbacks: Use of NMOS-only pass transistors results in a degraded 1 (V
dd
-V
tn
).
This impacts noise margin especially for low V
dd
values w.r.t. V
tn
. It also causes static
power dissipation in the first inverter since PMOS is not fully turned off.
Master Master- -Slave (Positive Edge Slave (Positive Edge- -Triggered) Register Triggered) Register
1
0 D
CLK
Q
M
Master
0
1
CLK
Q
Slave
Q
M
Q
D
CLK
Cascade of two opposite latches trigger on edge
Also called master-slave latch pair
When CLK=0, Master is transparent, and D passes to Q
M
. The slave stage is in hold
mode, keeping the previous value by using feedback.
When CLK=1, the slave stage samples the output of the master stage (Q
M
), while
master goes into hold mode.
The value of Q is the value of D right before the rising edge of the clock, achieving
the (+ve) edge triggered effect.
Master
Master
-
-
Slave Register
Slave Register
Q
M
Q
D
CLK
T
2
I
2
T
1
I
1
I
3
T
4
I
5
T
3
I
4
I
6
Multiplexer-based latch pair
When CLK=0, Master is transparent, and D passes to Q
M
. The slave stage is in hold
mode, keeping the previous value by using feedback.
When CLK=1, the slave stage samples the output of the master stage (Q
M
), while
master goes into hold mode.
Drawback: high load presented to the clock signal (8 transistors) - > high power
dissipation
Master
Master
-
-
Slave Register
Slave Register
Q
M
Q
D
CLK
T
2
I
2
T
1
I
1
I
3
T
4
I
5
T
3
I
4
I
6
Multiplexer-based latch pair
Assuming delay of clock inverter = 0
t
pd_inv
= delay of each inverter, t
pd_tx
= delay of transmission gate
The setup time is the time before the rising edge of the clock that the input D must be valid. How long before
the rising edge of the clock must D be stable such that Q
M
samples the value reliably? Setup time = 3t
pd_inv
+
t
pd_tx
Propagation delay is the time it takes Q
M
to propagate to output Q. t
c-q
= t
pd_tx
+ t
pd_inv
.
The hold time is the time that the input must be held stable after the rising edge of the clock. T
1
turns off when
the clock goes high. Any changes in the input after the clock goes high do not affect the output. Hold time = 0
Reduced Clock Load Master Reduced Clock Load Master- -Slave Register Slave Register
D
Q
T
1
I
1
CLK
CLK
T
2
CLK
CLK
I
2
I
3
I
4
Feedback transmission gate is eliminated by directly cross-coupling the inverters - > lower clock loading.
Drawbacks:
T
1
and its source driver must overpower the feedback inverter (I
2
) to switch state of the cross coupled inverter.
The input of I
1
must be brought below its switching threshold in order to make a transition. I
2
must be made
weak (minimum sized, or increasing its L if T
1
is minimum sized which is desirable to reduce power
dissipation in latches and clock distribution network)
Reverse conduction the second stage can affect the state of the first latch. When slave stage is on, it is
possible for the combination of T
2
and I
4
to influence the data stored in the I
1
-I
2
latch. As long as I
4
is weak,
this is not a major problem.
Avoiding Clock Overlap
Avoiding Clock Overlap
CLK
CLK
A
B
(a) Schematic diagram of negative
master-slave register
(b) Overlapping clock pairs
X
D
Q
CLK
CLK
CLK
CLK
Assumptions: Delay of CLK generating inverter is
zero. No variations exist in wires used to
route the 2 clock signals. This effect is called
clock skew, which causes the clock signals to
overlap.
Two failures:
(1) When CLK goes high, the slave stage should
stop sampling the master stage output and
go into hold mode. With CLK overlap, both
sampling pass transistors conduct and there
is a direct path from D to Q. Thus data at the
output can change on the rising edge of the
clock, which is undesirable for a (-ve edge-
triggered register) Race condition
(2) The primary advantage of the MUX-based
register is that feedback loop is open during
sample period. Thus sizing of devices is not
critical to function correctly. With CLK
overlap, node A can be driven by both D and
B (would impact speed).
Overpowering the Feedback Loop
Overpowering the Feedback Loop
-
-
Cross
Cross
-
-
Coupled Pairs
Coupled Pairs
Forbidden State
S
S
R
Q
Q
Q
Q R S Q
Q 0 0 Q
1 0 1 0
0 1 0 1
0 1 1 0 R
Q
NOR-based set-reset
When both S and R are 0, the flip-flop is in quiescent state and both outputs retain their values (cross coupled
NORs look like cross coupled inverters). If a positive pulse is applied to S, output Q is forced into a 1 state. A
positive pulse applied to R resets the flip-flop, and Q goes to 0.
Asynchronous!
Ratioed
Ratioed
CMOS SR Latch
CMOS SR Latch
M
1
M
2
M
3
M
4
Q
M
5
S
M
6
CLK
M
7
R
M
8
CLK
V
DD
Q
Synchronous It consists of a cross-coupled inverter pair + 4 extra
transistors to drive the flip-flop from one state to
another and to provide synchronization. In steady
state, one inverter resides in high state, while other
in low.
Transistor sizing is essential to ensure that the flip-
flop can transition from one state to the other when
requested.
Case: If Q is 1 and R pulse is applied. In order to
make latch switch, we must bring Q below the
switching threshold of the inverter M1-M2, and
quickly. Once this is achieved, the positive feedback
causes the flip-flop to invert states. Thus, M5, M6,
M7, M8 should be sized up.
The combination between M4, M7, M8 form a ratioed
inverter.
To switch the latch from Q=0 to Q=1, it is essential
that the low level of the ratioed inverter (M5-M6)-M2
be below the switching threshold of M3-M4 (V
DD
/2).
Boundary condition occurs when V
Q
=V
DD
/2.
(W/L)
5-6
is the effective ratio of the series-connected
devices.
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DSATp
DSATp Tp DD p
DSATn
DSATn Tn DD n
V
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