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A Biomedical Sensor Interface With a sinc Filter and Interference Cancellation

Jose L. Bohorquez, Member, IEEE, Marcus Yip, Student Member, IEEE, Anantha P. Chandrakasan, Fellow, IEEE, and Joel L. Dawson, Member, IEEE

AbstractA compact, low-power, digitally-assisted sensor interface for biomedical applications is presented. It exploits oversampling and mixed-signal feedback to reduce system area and power, while making the system more robust to interferers. Antialiasing is achieved using a charge-sampling lter with a sinc frequency response and programmable gain. A mixed-signal feedback loop creates a sharp, programmable notch for interference cancellation. A prototype was implemented in a 0.18- m CMOS process. The on-chip blocks operate from a 1.5-V supply and consume between 255 nW and 2.5 W depending on noise and bandwidth requirements. Index TermsAntialiasing, biomedical, digitally-assisted, interference cancellation, low-noise instrumentation, medical implants, mixed-signal feedback, power line interference, sensors, sinc lter.

Fig. 1. Block diagram of a typical sensor interface including the off-chip and on-chip aggressors which can corrupt the signal of interest.

I. INTRODUCTION LECTROCARDIOGRAMS (ECG), electroencephalograms (EEG), and electromyograms (EMG) are common bio-potential signals measured non-invasively or minimally invasively. Neural eld potentials, in contrast, are measured using medical implants [1], [2]. In most cases, an analog front-end (AFE) comprising an instrumentation amplier (IAMP) and an antialiasing lter is used to process these signals. Bio-potential signals can be as small as a few microvolts in magnitude, and typically reside between 1 Hz and 1 kHz in frequency. This combination of small magnitude and low frequency makes them particularly susceptible to a number of on-and off-chip aggressors as illustrated in Fig. 1. An AFE must be properly designed to prevent thermal and icker noise components in the IAMP from corrupting small input signals. The AFE must also have high differential-mode input impedance to avoid signal attenuation, and high common-

Manuscript received August 24, 2010; revised November 28, 2010; accepted December 15, 2010. Date of publication February 24, 2011; date of current version March 25, 2011. This paper was approved by Guest Editor Ajith Amerasekera. This work was supported by Texas Instruments Inc., DARPA, NSERC, and the Focus Center for Circuit and System Solutions (C2S2), one of ve research centers funded under the Focus Center Research Program, a Semiconductor Research Corporation program. J. L. Bohorquez was with the Microsystems Technology Laboratories, Massachusetts Institute of Technology, Cambridge, MA 02139 USA. He is now with Convergence Medical Devices Inc., Winchester, MA 01890 USA (e-mail: bohorquez@cmdevices.com). M. Yip, A. P. Chandrakasan, and J. L. Dawson are with the Microsystems Technology Laboratories, Massachusetts Institute of Technology, Cambridge, MA 02139 USA (e-mail: yipm@mit.edu; anantha@mtl.mit.edu; jldawson@mtl.mit.edu). Color versions of one or more of the gures in this paper are available online at http://ieeexplore.ieee.org. Digital Object Identier 10.1109/JSSC.2011.2108128

mode input impedance to minimize the conversion of commonmode interferers to differential-mode as a result of electrode impedance mismatch [3]. For many applications, the AFE must also be able to reject up to 300 mV of electrode DC offset [2], [4], [5]. Finally, the AFE must be able to withstand a signicant amount of power line interference (PLI). Coupling from surrounding power lines can inject a large amount of 50/60 Hz displacement current that mostly manifests as common-mode interference. The displacement current and common-mode interference are commonly converted to differential-mode, in-band interference through three main mechanisms: 1) current ow through nite tissue impedances between electrodes; 2) contact impedance mismatch from electrodes; and 3) nite commonmode rejection ratio (CMRR) of the AFE [3]. The differential-mode signal can be larger than the desired signal, and is often in the measurement band. In addition to dealing with on-chip and off-chip aggressors, minimizing power consumption is critical. This is particularly true for implants or systems that use multi-electrode arrays with tens or hundreds of sensors, such as brain-machine interfaces. Additionally, since the electrode pitch can be as small as 400 m, each AFE must be very small [1]. For non-invasive devices that use hundreds of sensors, such as modern EEG systems, there is a nancial incentive to minimize area and power, particularly if consumer products are targeted. Recent state-of-the-art AFEs have achieved very good thermal noise efciency through careful low-noise design [6], [7], while dealing with icker noise through chopper-stabilization [2], [8], [9]. The problem of electrode DC offset is typically addressed through ac-coupling [6], [7], [9], or via a feedback servo loop that integrates the offset and feeds it back to the input [2], [8]. However, current AFEs lack the ability to cancel interference right at the input of the system, where interferers like 50/60 Hz PLI can limit the minimum supply voltage. Eliminating interference at the input of the system, before substantial gain is applied, can relax dynamic range

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Fig. 2. System block diagram showing the on-chip instrumentation amplier, charge-sampling sinc antialiasing lter and charge redistribution feedback DAC; and off-chip ADC and digital signal processor.

requirements for multiple blocks and minimize the supply voltage requirements. This can lead to reduced overall system power consumption and area; both of which are critical for implanted and multi-electrode systems. This paper describes a digitally-assisted sensor interface that uses a mixed-signal feedback scheme to cancel interference right at the front end of the system, while doing so in a low-power, area-efcient manner. The system consists of a custom prototype chip and a commercial ADC and eld-programmable gate array (FPGA). An area-efcient antialiasing lter based on charge-sampling is also presented. The overall system leverages oversampling and digital design to reduce system area and power. The block diagram of the system is shown in Fig. 2. All blocks are fully differential to maximize signal range at a supply voltage of 1.5 V, and to minimize the effect of common-mode noise and interference. The on-chip components consist of a low-noise IAMP which provides 40 dB of midband gain, and a high-pass cut-off of 0.12 Hz to reject electrode DC offset. It is followed by a discrete-time sinc antialiasing lter (SAAF) stage which will be discussed in Section II. An on-chip ADC buffer drives an off-chip ADC which digitizes the samples. An FPGA performs digital signal processing (DSP) to extract interference that is then fed back to the input through an on-chip 8-bit charge-redistribution DAC. Section II motivates the use of oversampling and presents details of the antialiasing lter. Section III motivates the need for interference cancellation and presents details on our mixedsignal feedback scheme. Section IV discusses the IAMP implementation and provides noise analysis. Measurement results are given in Section V and Section VI concludes the paper. II. SINC ANTIALIASING FILTER Modern biomedical systems usually digitize the signal of interest using an ADC as shown in Fig. 1. To avoid corrupting the desired signal, an antialiasing lter is used to attenuate aggressors and noise components that would otherwise be frequency translated to the discrete-time signal band through the sampling process. Since sharp digital lters are typically more area and

Fig. 3. In the continuous-time spectrum, the desired signal band is shown in white, while corrupting aggressors at multiples of the sampling frequency f are shown in dark gray, and broadband aggressors are shown in light gray. The only components that would alias into the signal band after sampling are the corrupting aggressors. The SAAF frequency response effects antialiasing by significantly attenutating the corrupting aggressors. All other broadband aggressors are allowed to alias after sampling without corrupting the signal band. In the discrete-time spectrum (after sampling), a digital lter can then be used to remove the remaining unwanted out-of-band components.

power efcient, it is not necessary to use analog lters to eliminate all aggressors before sampling. It is critical, however, to eliminate aggressors that would otherwise alias into the signal band. Fig. 3 illustrates a continuous-time (CT) lter frequency response that would eliminate corrupting aggressors, but not other broadband ones. The sinc frequency response created by charge sampling creates precisely this type of frequency response since the notches are placed where corrupting aggressors would lie [10], [11]. However, to make the notches wide enough such that sufcient attenuation is achieved on the entire signal bandwidth, oversampling is required. The main cost of oversampling is increased power consumption; particularly in the ADC. However, recent advances in ADC design have led to ultra-low energy-per-conversion step gures-of-merit (FOM) such that the ADC power consumption can be made signicantly lower than other components in a typical narrowband biomedical system. In addition, for a given dynamic range requirement, a lower effective number of bits (ENOB) can be used when oversampling is employed.

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For example, the ADCs described in [12][14] all achieve FOMs of less than 65 fJ/conv-step, which corresponds to power consumption of less than 120 nW for an ENOB of 7.5 and a sampling rate of 10 kS/s. For a typical ECG or EEG sensor with 100 Hz bandwidth, these specications result in a dynamic range of 64 dB because of oversampling. A reduction in the required ENOB can result in a signicantly reduced area consumption by the ADC which can be critical in biomedical systems. A. Filter Architecture In this section we describe a sinc lter that provides programmable gain and achieves antialiasing by exploiting oversampling. The SAAF in Fig. 2 comprises a linear transcon, two capacitor banks , and two reset switches ductor . The input of the SAAF, , is a differential continuous-time signal which is the output of the IAMP. The SAAF , is a differential signal that is digitized by an exoutput, ternal ADC through an on-chip ADC driver. Each period starts by quickly resetting the voltage across each capacitor to the , such that the differential output common-mode voltage voltage is zero. The transconductor converts the lters input , and the current is integrated voltage to a current . At the end of each period, the ADC digitizes onto the lters output. It can be shown that the discrete-time baseis equivalent to band spectrum of (1) where is the sampling period and [10], [11]. The notches of the sinc lter land at integer multiples of , which is precisely what an antialiasing lter should do as shown in Fig. 3. In addition, the SAAF is a linear-phase, non-dispersive lter, so the only effect it has on the phase of the input signal is . The attenuation at multiples of to impart a delay of is theoretically innite, and is substantial in the vicinity of the , the amount of attenuation is approximately notches. At (2) for . Given a particular signal bandwidth and the requirements for aggressor attenuation in the aliasing bands, (2) sets the required sampling ratio to ensure the sinc notches are sufciently wide. and In contrast with classical analog lters, variations of in the SAAF affect only the gain, but not the frequency response. While accurate gain may be important, it can often be calibrated and will not change signicantly in implants due to the inherent temperature regulation of the human body. The gain of the SAAF is (3) and . In adThis allows gain programmability through dition, it allows smaller implementations than classical lters since large R-C constants are not required to achieve a small bandwidth.

is set using a 3-bit switched-resistor In our prototype, . can be tuned digitally between bank , resulting in 20 dB of gain control. is 100 nS and 1 implemented with two 5-bit switched-capacitor banks that can be tuned between 850 fF to 14.6 pF (including parasitics), resulting in 25 dB of additional tuning range. The total gain control is 45 dB. B. Transconductor Circuit Implementation The transconductor in the SAAF was implemented using the circuit in Fig. 4 which is similar to [15]. This fully-differential circuit uses negative feedback to implement a linear transconfor the case when ductance of as in our implementation. In addition to the transconductance of this circuit, the output resistance is also important. The sinc , and lter analysis above assumes that the transconductor, capacitor, , form an integrator. This is only true if the output resistance of the transconductor is innite, which is not possible. However, as long as the integrator time constant is signicantly larger than , the nite output resistance will not affect the performance signicantly. The effective output resistance of the transconductor was made large through cascoding of transistors M9M12, and by using long-channel devices. Acis greater than 50 G for our cording to SPICE simulations, design when each branch in the transconductor is biased with 20 nA (typical value). For the worst case scenario which occurs fF, ms, which is more than 200 when at kS/s. times larger than C. Filter Linear Range and Bias Current Selection Since the IAMP preceding the SAAF provides signicant gain, the noise specications of SAAF are greatly relaxed. The linearity requirements, however, require careful selection of the transconductors bias current. Generally, the transconductor topology in Fig. 4 is very linear due to negative feedback. However, if an insufcient amount of bias current is used, clipping can occur that introduces distortion. To prevent current or clipping, each of the four branches containing should use a bias current , such that (4) represents the largest input signal peak differwhere , should ential amplitude expected. The gain of the SAAF, be as large as possible, while satisfying this condition: (5) To minimize current consumption while preventing distortion, condition (5) can be combined with (4) and (3) which sets the minimum bias current (6) The total current consumption of the transconductor will be . slightly larger than is set As an example, if the SAAF gain is set to 20 dB and to 100 nS, the SAAF can be biased with a total of 150 nA while achieving excellent linearity. Measured results show that the

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Fig. 4. Schematic of the fully differential, linear transconductor used in the SAAF.

total harmonic distortion (THD) of the full system is less than output signal using these settings 0.1% for a differential 1.0 and remains below 1% for output voltages up to 1.75 . III. INTERFERENCE CANCELLATION A. Motivation Power consumption in a signal processing system is often determined by dynamic range requirements. The dynamic range is a measure of the ratio between the largest signal that can be handled by the system without signicant distortion and the minimum detectable signal set by the input-referred noise. The specications for the minimum detectable signal are typically set by the signal being measured, but the largest signal that must be handled is often set by interference. If the high end of the dynamic range is set by an interfering signal and is ltered out near the front end, the dynamic range requirements of subsequent stages can be relaxed and their power consumption reduced. As an example, EEG signals can range in amplitude between and 300 . Power line interference (PLI), on the 5 other hand, can be as large as 5 mV differentially [16]. This corresponds to an increase in the required dynamic range (DR) of almost 25 dB, resulting in unnecessary power consumption. These observations motivate the design of a system that lters out large interferers near the front-end, while minimally impacting the signal band of interest. We emphasize PLI as an important example, but other interferers may be present at different frequencies and of different bandwidths. It is therefore important for the interference cancellation method to be easily congurable. B. Digital Architecture The block diagram of the interference cancellation system introduced in Fig. 2 is shown with full details in Fig. 5(A). It includes an IAMP, SAAF, and ADC in the forward path, and a digital signal processor (DSP) and DAC in the feedback path. The DSP was implemented on an FPGA and is used to create frequency translated integrators to sift and amplify interference so

Fig. 5. Block diagram of mixed-signal system including the custom prototype chip (IAMP, SAAF, DAC), off-chip ADC, and FPGA for notch implementation.

that it can be fed back to the input of the system for cancellation. The DSP includes a direct digital synthesizer (DDS) that generates sinusoidal signals, four multipliers, and two accumulators. The closed-loop frequency response of the system has the form of a sharp notch. The characteristics of the notch are set by the feedback network that is implemented digitally. The input and respecand output of the digital block are labeled tively in Fig. 5. The discrete-time transfer function of the DSP block can be shown to equal (7) where is set by the DDS. This transfer function resembles a frequency-translated accumulator with innite magnitude at .

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C. Closed-Loop Transfer Function Fig. 5(B) shows the block diagram of the system in Fig. 5(A). is the gain of the IAMP ( 100) and is the gain of the SAAF, which is programmable from 0.7 to 130 ( 3 dB to 42 dB). A 16 bit ADC (AD7684 from Analog Devices) was used , where and its gain is dened as is the ADC full-scale reference voltage. Although a lower resolution ADC can be used to meet typical specications, a high resolution ADC was used so that the rest of the system could be characterized without its performance being impacted by aws in the ADC. An on-chip 8 bit DAC was used with gain . The 1/4 term arises from the implementation of the DAC as will be discussed later. In the feedback loop, the SAAF acts as both an antialiasing lter for the continuous-to-discrete-time conversion, and as a reconstruction lter for the discrete-to-continuous-time conversion. Because there is no aliasing, we can treat the interface between the discrete-time and continuous time domains by simply into (7). The resulting equivalent continsubstituting uous-time transfer function of the digital block is given by (8) The loop gain of the system is, therefore, (9) where function from . The closed-loop transfer to is (10) To simplify the analysis, the IAMP and SAAF are modeled as gain stages with a constant frequency response. While these blocks are frequency-dependent, their phase responses are and therefore have a negligible effect on nearly zero near the closed-loop transfer function as will be shown. The 3-dB bandwidth of the notch can be determined by nding the value of for which the loop gain amplitude is unity. This occurs at four frequencies approximately located at (11) for , which implies the notch width is narrow compared with its center frequency. To make the notch narrow, must be very small so that is small. , where the ampliInspection of (10) reveals that at tude of the loop gain is innite, the closed loop response must be zero. In contrast, at frequency offsets beyond 1 Hz from , the loop gain is very small and the closed-loop response is simply . In other words, the closed-loop system will notch out spectral components around without affecting the rest of the spectrum signicantly. Fig. 6 shows a simulation of the magnitude responses of the closed-loop transfer function (taking the ). Clearly, the notch is very narrow, as expected, output at and has a 3-dB corner frequency at the same frequency that the loop gain crosses 0 dB. Importantly, because the loop gain has

Fig. 6. Magnitude of the closed-loop frequency response for . The top plot shows the response from . The middle plot zooms in to to the signal bandwidth of interest, showing a very narrow notch at , and the bottom plot zooms in around . The notch width can be easily programmed by . changing

0f =2 f =2

G =2 f

a maximum phase magnitude of 90 , the system is unconditionally stable. The effect of the feedback on the phase of the signal is minimal for most frequencies except around the notch frequency. However, since these are precisely the frequencies being eliminated it does not have a signicant impact on the desired signal. D. Digital Block Implementation As shown in Fig. 5, the digital block comprises four digital multipliers, two accumulators, a gain block , a direct-digital synthesizer (DDS), and an adder. The prototype uses 16-bit multipliers to minimize quantization noise and 32-bit accumulators to avoid overow. Each accumulator is implemented using a 32-bit adder with the 16 LSBs of its output connected to one is always much smaller than unity (e.g., ) of its inputs. and is implemented in two stages. The rst stage is implemented using multiplexors to select 16 of the 32 accumulator output bits. This allows simple programmability of the gain by factors of 2 , and results in minimal hardware overhead. The second , gain stage is implemented by truncating the 8 LSBs of bringing the data down to 8 bits at the input of the DAC. The DDS comprises a 32-bit accumulator and a 16-bit RAM look-up table (LUT) with 1024 addresses [17]. The frequency resolution , which is less than 2.5 Hz for kHz. is The 10 MSBs of the accumulator are used as the LUTs address is used to choose the for the sine output and an offset of LUTs address for the cosine output. Since the digital blocks were implemented on an FPGA, it is challenging to quantify their area and power cost. However, efforts are underway to implement optimized versions of these blocks in a 0.18- m process using a 1.2 V supply. Power and area estimates indicate that the digital blocks can be implemented efciently both in terms of area and power. The area consumed by the DDS is estimated at 0.06 mm and the simulations including parasitics and leakage predict power consumption below 100 nW. The other blocks are estimated to consume less than 175 nW and 0.06 mm when combined. For

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Fig. 8. (A) Single ended equivalent of IAMP in Fig. 2 including noise sources, and (B) corresponding block diagram.

Fig. 7. (A) Schematic of the combined IAMP and charge redistribution DAC. The DAC is implemented with binary weighted capacitors and switches. A simplied diagram of the switches implementation is shown in (B). (C) shows a simplied, single-ended model of the IAMP with with two inputs: one for the signal v and another for the equivalent DAC voltage signal v .

bits, which results in a dynamic range of 67 dB since an overkS/s, Hz). sampling ratio of 50 is used (i.e. This allows cancellation of sinusoidal interferers as large as of input-referred 5 mV , while introducing only 800 nV noise. F. Summary of Interference Cancellation System The system described above is conceptually similar to [19] in its use of frequency translated integrators in the feedback path. However, this system exploits mixed-signal design to provide four main benets: 1) Area: Unlike analog implementations, no large passives are necessary to create the large time constants required for creating a narrow notch. Instead, area-efcient digital to very small values. While registers are used to set there is some area cost to the necessary digital blocks and feedback DAC, it is signicantly smaller than the cost of adding large passives. 2) Programmability: With the mixed-signal design, the notchs center frequency and width can be easily and arbitrarily reprogrammed. Although we have focused on ltering PLI, other types of interference can be canceled. For example, in closed-loop, deep brain stimulators, stimulation artifacts occuring at a known rate could be notched out by this technique. 3) Reduced power: This technique consumes less power than analog implementations because the main blocks used to implement it are already necessary. Since the ADC and DSP are common blocks, the only additional block is the DAC, which can be designed to consume a small area and negligible power. 4) Flexibility: Although our focus was on implementing a single notch, additional digital feedback blocks can theoretically be used in parallel to notch out multiple blockers. Additionally, digital signal processing could be used to track an interferer and adjust the notch to lter it out. IV. INSTRUMENTATION AMPLIFIER Fig. 8(A) shows the equivalent single-ended model of the IAMP in Fig. 2 including all noise sources. includes the

multi-electrode systems, a single DDS can be used for multiple signal chains, amortizing its power consumption and area, and resulting in even lower costs per channel. E. DAC Implementation The DAC in Fig. 5 uses binary-weighted charge-redistribution and is implemented with switched capacitors. In Fig. 7, (A) shows a simplied schematic of the DAC and its connection to the IAMP, (B) shows the implementation of the switches and (C) shows an equivalent single-ended model of the DAC and IAMP. Charge redistribution DACs usually require an op-amp to convert charge to voltage [18], but since the IAMP already uses an op-amp, the DAC simply reuses it. As a result, only the capacitor power array and switches add to the total area, and only is added. The power consumption is minimal since the reference voltage, sampling frequency, and capacitors are all small. For example, at 10 kS/s and using 2.56 pF of capacitance and a power is less than 3 pW. reference voltage of 10 mV, the As will be discussed in Section IV, shunt capacitance added at the input of the op-amp attenuates the input signal resulting in degraded noise performance. For this reason, it is important to such that the total DAC capacitance is signicantly minimize pF, smaller than . In our implementation, which is approximately . Since the DAC is in the feedback path, its performance sets the dynamic range of the overall system. As discussed in Section III-A, a key motivation for using this interference cancellation technique is that it relaxes the dynamic range requirements of multiple blocks. By eliminating large interference at the front end of the system, dynamic range requirements for the IAMP, lter, and ADC are relaxed, resulting in lower power consumption. The DAC was designed to have an ENOB of 8

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Fig. 9. Simplied schematic of fully differential op-amp used in the IAMP.

DAC total capacitance plus the parasitic input capacitance of the is implemented using fully differential op-amp. MOS-bipolar pseudo-resistor elements as in [6]. The equivalent and the input-referred noise of the op-amp is modeled with thermal noise of is modeled as . Fig. 8(B) shows the equivalent block diagram. The op-amp is modeled with only its for simplicity. Within the bandwidth of indominant pole at terest, the transfer function from to can be closely approximated as (12)
Fig. 10. Die microphotograph of the implemented chip.

which gives the desired high-pass characteristic necessary to lter out the electrode DC offset while achieving a midband gain . The corner frequency is set by and . and of were set to 100 fF and 10 pF respectively, giving a high-pass corner frequency of 120 mHz and a midband gain of 100 V/V. A. Noise From the Op-Amp The input-referred transfer function for the op-amp noise is approximately (13) showing that the input-referred noise of the op-amp is magnied by the ratio of total input capacitance to . To minimize this effect, was chosen to be much larger than and . Fig. 9 shows the full schematic of the fully-differential op-amp implemented in the IAMP. Careful noise analysis for a similar op-amp architectures can be found in [6] and [7]. B. Noise From While the impact of on the noise performance of the IAMP was not discussed in [6] or [7], the following analysis shows that it is a critical component. The input-referred noise transfer function for the feedback resistor is (14)

for is

. As a result, the input-referred noise density due to

(15) Beyond its high-pass corner frequency, the impedance of the . IAMPs feedback network is dominated by the capacitor integrates currents owing into Combined with the op-amp, , giving rise node and therefore shapes the white noise of noise characto a power spectral density (PSD) with a teristic. For applications where important signal information is found at very low frequencies (e.g., 1 Hz), this can present a signicant problem since the only two solutions are increasing or . The noise contribution of was not discussed in noise at low frequencies can be seen in the [6], but the measured noise PSD as in our own measurements. V. MEASUREMENT RESULTS Fig. 10 shows a die microphotograph of a prototype of the proposed system implemented in a 0.18 m CMOS. The total active area is 0.6 mm 0.49 mm, and the critical components (IAMP, SAAF, and DAC) consume 0.225 mm . As mentioned in Section III-D, the digital blocks for this prototype were implemented on an FPGA, so it is challenging to quantify their area and power cost. However, optimized versions of these blocks are being implemented in 0.18- m process with a total area cost of

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TABLE I COMPARISON WITH RECENT PUBLICATIONS

DSP power and area estimates are explained in Section V.

0.12 mm . Simulations including parasitics and leakage predict power consumption below 275 nW for all digital blocks combined. Table I summarizes key performance metrics and compares them with recent publications. A. Frequency Response Fig. 11 shows the frequency response of the system for two different IAMP bias settings using linear and logarithmic frequency scales. For a bias setting of 1.6 , the IAMP has a relatively wide bandwidth and the sinc-shape of the SAAF is clear. At the typical setting of 400 nA, the IAMP itself provides some additional ltering. The middle plot shows the frequency response using a logarithmic frequency scale. The high-pass response of the IAMP is evident as well as the sharp notch centered at 60 Hz. As shown in the bottom plot, the SAAF alone provides more than 39 dB of ltering over a bandwidth of 100 Hz around 10 kHz. At the 400 nA IAMP bias setting, an additional 18 dB of attenuation result in a total of 57 dB of antialiasing ltering. The mixed-signal interference cancellation technique effectively creates a sharp notch with programmable frequency and width. Fig. 12 shows the notch programmed to two different frequencies and three different width settings. For a setting of , the 3-dB notch width is 0.35 Hz, which is equivalent to a quality factor, or , of 170. The analog implementation of a conceptually similar system described in [19] uses 100 capacitors and 10 resistors implemented with discrete components and achieves a bandwidth of 0.5 Hz. The settling time of the interference cancellation loop depends on the notch width setting. It was measured to be as long as 1.5 seconds for the sharpest notch setting in Fig. 12. Natural movement during physiological measurements, however, did not cause noticeable disturbances in the output signal. B. Noise Performance Noise measurements for the system were performed by gathering data from the ADC output and performing FFTs using MATLAB. Fig. 13 shows the input-referred noise of the system for four different bias settings of the IAMP. The SAAF was biased with 150 nA of current, and varying the bias current over a wide range showed no degradation in system noise perfornoise from described in Section IV is evimance. The noise from dent at frequencies below 5 Hz as expected, and

Fig. 11. The top plot shows the combined frequency response of the IAMP and SAAF for two different IAMP bias settings. At the high current setting, the response is dominated by the sinc response. At the low current setting, the IAMP itself provides additional ltering. The middle and bottom plots show the frequency response of the full system including a sharp, programmable notch for interference cancellation and sinc lter notches for antialiasing.

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Fig. 14. (A) Input-referred spectrum of the system with a 5 mV , 60 Hz sinusoidal input with and without the notch lter. (B) Input-referred spectrum of the system when no input signal is applied.

Fig. 12. The top plot shows the notch frequency tuned to two different frequencies, 50 and 60 Hz. The bottom plot shows the notch width programmed to three different notch widths. The notch frequency is programmed through the DDS accumulation word and the width is programmed by modifying .

Fig. 15. Filter gain versus setting for each respond to lower capacitance settings.

setting. The larger gains cor-

Fig. 14(A) shows the input-referred spectrum of the system with a 5 mV , 60 Hz sinusoid input signal. Turning the notch lter on attenuates the interferer by more than 60 dB. Small spurs appear at multiples of 20 Hz that are caused by nonidealities in the DDS including phase truncation, but the largest in amplitude [20]. Fig. 14(B) shows the one is less than 3 spectrum when no input signal is applied and clearly shows that the notch lter does not increase the noise spectral density and in fact lters some of the noise around 60 Hz, although small spurs at 60 Hz and 80 Hz appear. C. SAAF Programmable Gain Fig. 15 shows the gain of the SAAF for different capacitor bank and resistor bank settings. The top line represents the minimum capacitor setting and lower lines represent repreincreasing capacitance. Similarly, higher settings of sent smaller resistance and higher gain. A wide range of gain settings ( 3 dB to 42 dB) was designed to allow maximum exibility during testing, but the lter can be made much smaller by setting the minimum gain to a higher value. As seen in Fig. 10, and compose the bulk of the SAAF area. For a minimum gain of 10 dB, the area can be reduced by more than 70%.

Fig. 13. Input-referred noise of system for multiple IAMP bias settings ( = 150 nA).

the op-amp is seen up to a few hundred Hz depending on bias settings. Thermal noise from the op-amp decreases with higher bias currents as expected.

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ACKNOWLEDGMENT The authors would like to thank P. Mercier, N. Verma, and A. Avestruz for their support and helpful discussion.

REFERENCES
[1] R. R. Harrison, P. T. Watkins, R. J. Kier, R. O. Lovejoy, D. J. Black, B. Greger, and F. Solzbacher, A low-power integrated circuit for a wireless 100-electrode neural recording system, IEEE J. Solid-State Circuits, vol. 42, no. 1, pp. 123133, Jan. 2007. [2] T. Denison, K. Consoer, W. Santa, A. Avestruz, J. Cooley, and A. Kelly, A 2 W 100 nV/rtHz chopper-stabilized instrumentation amplier for chronic measurement of neural eld potentials, IEEE J. Solid-State Circuits, vol. 42, no. 12, pp. 29342945, Dec. 2007. [3] J. C. Huhta and J. G. Webster, 60-Hz interference in electrocardiography, IEEE Trans. Biomed. Eng., vol. BME-20, no. 2, pp. 91101, Mar. 1973. [4] Medical Electrical EquipmentPart 2-47: Particular Requirements for the Safety, Including Essential Performance of Ambulatory Electrocardiographic Systems. International Electrotechnical Commission, 2010. [5] R. Yazicioglu, P. Merken, and C. V. Hoof, Integrated low-power 24-channel EEG front-end, Electronics Lett., vol. 41, no. 8, pp. 457458, 2005. [6] R. Harrison and C. Charles, A low-power low-noise CMOS amplier for neural recording applications, IEEE J. Solid-State Circuits, vol. 38, no. 6, pp. 958965, Jun. 2003. [7] W. Wattanapanitch, M. Fee, and R. Sarpeshkar, An energy-efcient micropower neural recording amplier, IEEE Trans. Biomed. Circuits Syst., vol. 1, no. 2, pp. 136147, Jun. 2007. [8] R. Yazicioglu, P. Merken, R. Puers, and C. V. Hoof, A 200 W eightchannel EEG acquisition ASIC for ambulatory EEG systems, IEEE J. Solid-State Circuits, vol. 43, no. 12, pp. 30253038, Dec. 2008. [9] N. Verma, A. Shoeb, J. Bohorquez, J. Dawson, J. Guttag, and A. P. Chandrakasan, A micro-power EEG acquisition SoC with integrated feature extraction processor for a chronic seizure detection system, IEEE J. Solid-State Circuits, vol. 45, no. 4, pp. 804816, Apr. 2010. [10] L. Carley and T. Mukherjee, High-speed low-power integrating CMOS sample-and-hold amplier architecture, in Proc. IEEE Custom Integrated Circuits Conf., 1995, pp. 543546. [11] G. Xu and J. Yuan, Comparison of charge sampling and voltage sampling, in Proc. 43rd IEEE Midwest Symp. Circuits Syst., 2000, vol. 1, pp. 440443. [12] J. Craninckx and G. Van der Plas, A 65 fJ/conversion-step 0-to-50 MS/s 0-to-0.7 mW 9 b charge-sharing SAR ADC in 90 nm digital CMOS, in IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers, 2007, pp. 246247. [13] A. Agnes, E. Bonizzoni, P. Malcovati, and F. Maloberti, A 9.4-ENOB 1 V 3.8 W 100 kS/s SAR ADC with time-domain comparator, in IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers, 2008, pp. 246247. [14] M. van Elzakker, E. van Tuijl, P. Geraedts, D. Schinkel, E. Klumperink, and B. Nauta, A 10-bit charge-redistribution ADC consuming 1.9 W at 1 MS/s, IEEE J. Solid-State Circuits, vol. 45, no. 5, pp. 10071015, May 2010. [15] M. Koyama, T. Arai, H. Tanimoto, and Y. Yoshida, A 2.5-V active low-pass lter using all-n-p-n gilbert cells with a 1-V linear input range, IEEE J. Solid-State Circuits, vol. 28, no. 12, pp. 12461253, Dec. 1993. [16] J. G. Webster, Medical Instrumentation; Application and Design, 3rd ed. Hoboken, NJ: Wiley, 1998, pp. 186194. [17] J. Tierney, C. Rader, and B. Gold, A digital frequency synthesizer, IEEE Trans. Audio Electroacoust., vol. AU-19, no. 1, pp. 4857, Mar. 1971. [18] D. A. Johns and K. Martin, Analog Integrated Circuit Design, 1st ed. New York: Wiley, 1997, ch. 4, pp. 196200. [19] I. Hwang and J. Webster, Direct interference canceling for two-electrode biopotential amplier, IEEE Trans. Biomed. Eng., vol. 55, no. 11, pp. 26202627, Nov. 2008. [20] L. Cordesses, Direct digital synthesis: A tool for periodic wave generation (part 2), IEEE Signal Process. Mag., vol. 21, no. 5, pp. 110112, Sep. 2004.

Fig. 16. ECG measurements without (A), (C) and with (B), (D) the notch lter nA, I nA). for two normal subjects (I

= 400

= 150

D. Physiological Measurements Fig. 16 shows multiple ECG measurements made with the prototyped system. (A) shows an ECG measurement of a healthy male subject made with the notch lter off using unshielded wires and disposable ECG electrodes. (B) shows the same measurement made with the notch lter on, clearly eliminating all PLI. To exacerbate the effects of PLI, one input resistor to of the IAMP was connected to ground with a 10 intentionally degrade its input impedance and CMRR, inducing more differential-mode interference. Fig. 16(C) shows the ECG for a different healthy male subject using this conguration, clearly showing increased amounts of PLI. Again, as shown in (D), all PLI is removed when the notch lter is turned on.

VI. CONCLUSION This paper presents a compact, digitally-assisted sensor interface for biomedical applications with interference cancellation capabilities. A custom chip comprising a low-power IAMP, sinc antialiasing lter and feedback DAC was used as part of the closed-loop system which also includes an external ADC and FPGA. The use of charge-sampling achieves substantial antialiasing in an area-efcient manner, while providing up to 45 dB of programmable gain and a frequency response that is independent of component parameters. A second focus of this work is the use of digital signal processing and a low-power DAC in the feedback path, which enables a exible closed-loop response that is capable of notching out interferers such as PLI. The use of frequency translated accumulators in the digital domain creates a closed-loop notch that is easily congurable in terms of center freuency and width, which cannot easily be done with conventional analog lters. Furthermore, the notch width can be made arbitrarily narrow by setting simple registers. An analog counterpart would require prohibitively large passives. Finally, by canceling interferers at the front end of the system, the dynamic range requirements of the forward path blocks are relaxed, enabling power savings and low voltage operation.

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Jose L. Bohorquez (S04M09) received the B.S. and M.S. degrees in electrical engineering from the University of Florida, Gainesville, FL, in 2002 and 2004. During that time, he held internships at Lockheed Martin, APA Wireless, and GE Healthcare. He then worked at the startup company BitWave Semiconductor designing analog and RF blocks for a recongurable transceiver until 2006. In 2009 he received the Ph.D. in electrical engineering from the Massachusetts Institute of Technology (MIT), Cambridge, MA, where his research focused on designing ultra-low power circuits and systems for medical devices and implants. Since 2009, he has served as CEO of Convergence Medical Devices, Inc., Winchester, MA, a startup company he co-founded. Dr. Bohorquez has received multiple awards including the International Engineering Consortiums William L. Everitt Student Award of Excellence, the Semiconductor Research Corporation/IBM Fellowship, and the MIT Presidential Fellowship.

Marcus Yip (S05) received the B.A.Sc. degree in engineering science from the University of Toronto, Ontario, Canada, in 2007, and the M.S. degree from the Massachusetts Institute of Technology (MIT), Cambridge, MA, in 2009, where he is currently pursuing the doctoral degree. He has held internships at Actel Corporation, Snowbush Microelectronics, and Texas Instruments. His research interests include low-power analog front-ends and recongurable analog-to-digital converters for medical applications. Mr. Yip received the NSERC Postgraduate Fellowship in 2007 and 2009.

Anantha P. Chandrakasan (M95SM01F04) received the B.S., M.S., and Ph.D. degrees in electrical engineering and computer sciences from the University of California, Berkeley, in 1989, 1990, and 1994, respectively. Since September 1994, he has been with the Massachusetts Institute of Technology, Cambridge, where he is currently the Joseph F. and Nancy P. Keithley Professor of Electrical Engineering. He is the Director of the MIT Microsystems Technology Laboratories. His research interests include low-power digital integrated circuit design, wireless microsensors, ultra-wideband radios, and emerging technologies. He is a coauthor of Low Power Digital CMOS Design (Kluwer Academic, 1995), Digital Integrated Circuits (Pearson Prentice-Hall, 2003, 2nd edition), and Sub-Threshold Design for Ultra-Low Power Systems (Springer, 2006). He is also a co-editor of Low Power CMOS Design (IEEE Press, 1998), Design of High-Performance Microprocessor Circuits (IEEE Press, 2000), and Leakage in Nanometer CMOS Technologies (Springer, 2005). Prof. Chandrakasan was a co-recipient of several awards including the 1993 IEEE Communications Societys Best Tutorial Paper Award, the IEEE Electron Devices Societys 1997 Paul Rappaport Award for the Best Paper in an EDS publication during 1997, the 1999 DAC Design Contest Award, the 2004 DAC/ ISSCC Student Design Contest Award, the 2007 ISSCC Beatrice Winner Award for Editorial Excellence and the 2007 ISSCC Jack Kilby Award for Outstanding Student Paper. He has served as a technical program co-chair for the 1997 International Symposium on Low Power Electronics and Design (ISLPED), VLSI Design 98, and the 1998 IEEE Workshop on Signal Processing Systems. He was the Signal Processing Sub-committee Chair for ISSCC 1999-2001, the Program Vice-Chair for ISSCC 2002, the Program Chair for ISSCC 2003, and the Technology Directions Sub-committee Chair for ISSCC 2004-2008. He was an Associate Editor for the IEEE JOURNAL OF SOLID-STATE CIRCUITS from 1998 to 2001. He served on SSCS AdCom from 2000 to 2007 and he was the meetings committee chair from 2004 to 2007. He is the Technology Directions Chair for ISSCC 2009.

Joel L. Dawson (S97M03) received the S.B. in electrical engineering from the Massachusetts Institute of Technology (MIT), Cambridge, in 1996, and the M.Eng. degree from MIT in electrical engineering and computer science in 1997. He went on to pursue further graduate studies at Stanford University, Stanford, CA, where he received the Ph.D. in electrical engineering for his work on power amplier linearization techniques. He is an Associate Professor in the Department of Electrical Engineering and Computer Science at MIT. Before joining the faculty at MIT, he spent one year at Aspendos Communications, a startup company that he co-founded. He continues to be active in the industry as both a technical and legal consultant. Prof. Dawson received the NSF CAREER award in 2008, and was selected for the Presidential Early Career Award for Scientists and Engineers (PECASE) in 2009.