Project Report on

Design and Development of Maximum Gain Amplifier at 1.57 GHz

Under

Indian National Academy of Engineering Mentoring Program, New Delhi

Submitted to

Prof. Shiban K. Koul

Centre of Applied Research in Electronics Indian Institute of Technology, New Delhi

By

Aniket Kumar
B.Tech (3rd Year), Electronics & Communication Engineering, National Institute Of Technology, Jamshedpur

CERTIFICATE

This is to certify that Mr.Aniket Kumar student of B. Tech (Electronics & Communication Engineering), National Institute of Technology, Jamshedpur has successfully completed his project report entitled Design and development of Maximum gain Amplifier at 1.57 GHz from 14th May 2012 to 13th July 2012 at CARE, New Delhi under my supervision and guidance. I wish him all success in future.

July 2012

Prof.Shiban Kishen Koul C.A.R.E., IIT Delhi

ACKNOWLEDGEMENT
I would like to take this opportunity to express my deep sense of gratitude to my guide Prof. Dr. Shiban Kishen koul for providing me the opportunity to carry out my project at C.A.R.E. IIT, Delhi. His benevolent guidance, apt suggestions and unstinted help have helped me the most in successful completion of the present work. I would like to thank INAE (Indian National Academy of Engineering) for giving me such a good opportunity to work under its mentoring scheme. I am also thankful to CARE Department for allowing me to work in RF and Microwave laboratory and all mentors in the lab. for their guidance and help for their extended support in the present work. I would like to convey my special thanks to Mr.Ritabrata Bhattacharya Sir for his untiring efforts, continuous cooperation and technical support. Without his positive attitude and moral support, the project would have not been completed in time. I convey my appreciation to Mr. Ashok Pramanik for his help. I would also like to thank the other summer interns Prashant sir, Hridesh Sir, Rajkumar Sir, Ankit, Abhishek, Vishaka who made my journey a memorable one.

(ANIKET KUMAR)

Abstract
An RF (Microwave) amplifier is a type of electronic amplifier used to convert a low-power radio-frequency signal into a larger signal of significant power, typically for driving the antenna of a transmitter. It is usually optimized to have high frequency, high output power (P1dB) compression, good return loss on the input and output, good gain and optimum heat dissipation. In this proposed research work, we made a Microwave amplifier that has a maximum gain operating at a particular sharp frequency i.e. 1.57GHz. Firstly, we designed the various circuits in ADS with different type of biasing and got variable gain from different types of circuits after simulation on ADS. The following circuits are fabricated and constructed after soldering on VNA. The biasing circuit with maximum gain is further analysed with matching network and TRL calibration to obtain a good result. Finally, the amplifier circuit module obtained is operated with a single power supply and results obtained on VNA are found to be more accurate with high gain and figure of merit as compare to without matching network & TRL calibration. One of the important applications of project work is for the civic part of GPS frequency. This project introduce to rugged linear, lownoise wireless technology. Linear and rugged lownoise amplifiers are needed in any operational communication system to achieve fast and reliable information transfer while maintaining good ruggedness and linearity even in harsh environments. It can also create a great roll in development of WLAN, Wi-fi Standards, Bluetooth devices. Their applications can also use for weather sensing, RF heating (Microwave oven) and exciting cavity resonators So that we can utilise the Electromagnetic spectrum properly and efficiently.

Contents
Certificate Acknowledgement Design and Development of maximum Gain Amplifier at 2.45 GHz
Abstract 1. Introduction 1.1 Design of Microwave Amplifiers using S Parameters 1.1.1 Power gain 1.1.2 Available Gain 1.1.3 Transducer gain 1.2 Design Methodology 1.3 Stability 1.3.1 Unconditional Stability 1.3.2 Conditional Stability 2. High Electron Mobility Transistor 2.1 Introduction to HEMT 2.2 Electrical Characteristics 2.3 Version of HEMTs 2.3.1 pHEMT 2.3.2 mHEMT 2.4 HEMT Operation 2.5 Applications 2.6 Typical Scattering Parameters Datasheet of HEMT 3. Design Procedure 3.1 Design Environment: ADS 3.2 The Smith Chart 3.3 Basic HEMT mounted on a 50 Impedance line. 4. Different Type of Biasing 4.1 1st type of Biasing 4.2 2nd type of Biasing 4.3 3rd type of Biasing 5. TRL Calibration 6. Optimization on ADS. 7. IntelliCAD 7.1 Generating layout 7.2 Steps in IntelliCAD 7.3 Masking 8. Fabrication 9. Soldering & Testing 10. Operation with a single power supply.

Conclusion References

List of Figures
1. Introduction
Fig 1.1 A two port network with general source and load impedance. Fig 1.2 General transistor amplifier circuit. Fig 1.3 basic amplifier Circuit.

2. High Electron Mobility Transistor

Fig 2.1 Typical structure of HEMT showing outline dimension. Fig 2.2 Table of Electrical Characteristics of HEMT.

3. Design Procedure
Fig 3.1 Circuit designed in ADS for HEMT parameter measurement. Fig 3.2 The Smith Chart showing Impedance and resistance circle. Fig 3.3 Basic HEMT mounted on a 50 Impedance line.

4. Different type of Biasing

Fig 4.1: Schematic Circuit Diagram made in ADS of 1st type of biasing. Fig 4.2: Constructed Circuit. Fig 4.3: Simulated results showing the values of S11, S21, S12, S22 on ADS. Fig 4.4: Tested results showing the values of S11, S21, S12, S22 on VNA. Fig 4.5: Schematic Circuit Diagram made in ADS of 2nd type of biasing. Fig 4.6: Constructed Circuit. Fig 4.7: Simulated results showing the values of S11, S21, S12, S22 on ADS. Fig 4.8: Tested results showing the values of S11, S21, S12, S22 on VNA. Fig 4.9: Schematic Circuit Diagram made in ADS of 3rd type of biasing. Fig 4.10: Simulated results showing the values of S11, S21, S12, S22 on ADS.

5. TRL calibration
Fig 5.1: Circuits after TRL calibration. Fig 5.2: Tested Results showing S11, S21, S12, S22 on VNA after TRL calibration. Fig 5.3: Table of S-parameter after importing data from VNA. Fig 5.4: Schematic Circuit Diagram made in ADS with matching network after TRL calibration. Fig 5.5: Simulated results showing the values of S11, S21, S12, S22 on ADS.

6. Optimization on ADS.
Fig 6.1: Schematic Circuit Diagram made in ADS of 1st type of biasing. Fig 6.2: Simulated results showing the value of S21 on ADS software.

7. Steps in Intellicad for generating Mask.

Fig 7.1: Circuit used for layout generation. Fig 7.2: Method of generating layout. Fig 7.3: layout of the design. Fig 7.4: Method of generating artwork. Fig 7.5: Export to DWG/DXF format. Fig 7.6: Mask prepared on Rubylith Sheet.

8. Fabrication
Fig 8.1: Acetone solution and hot blower. Fig 8.2: A Vacuum spinner. Fig 8.3: Oven. Fig 8.4: UV Exposure. Fig 8.5: Developer and fixer solution Fig 8.6: Pattern shown after applying dye on substrate. Fig 8.7: State in between the Etching. Fig8.8: Final circuit after Etching.

9. Soldering & Testing

Fig 9.1: Constructed circuit after mounting SMDs and HEMT. Fig 9.2: Tested results showing the values of S11, S21, S12, S22 on VNA. Fig 9.3: vector Network analyzer and Power supply.

10. Operation with a single supply

Fig 10.1: Construed circuit for operating by a single power supply. Fig (10.2): Tested results showing the values of S11, S21, S12, S22 on VNA.

1. Introduction
Amplification is one of the most basic and prevalent microwave circuit functions in modern RF and Microwave systems. Early microwave amplifiers relied on tubes, such as klystrons and travelling-wave tubes. Now due to dramatic improvements and innovations in solid-state technology, most RF and microwave amplifiers today used transistor devices such as Si, SiGe BJTs, GaAs HBTs, GaAs or InP FETs, GaAs HEMTs. An amplifier circuit consists mainly of a gain device or devices, and input and output matching or coupling networks. The amplifier should make weak signals larger without adding too much noise or distortion. Ideally, the amplifier would add no noise and would not distort the signal in any way. Electronic devices are not ideal however, and thus degrade the signal to some degree. The amplifier design objective is to minimize the noise added and the distortion created while increasing the amplitude of the signal. Design trade-offs allow one to obtain the best possible performance from a particular active device. Microwave transistor amplifiers are rugged, low-cost, and reliable and can be easily integrated in both hybrid and monolithic integrated circuitry. Transistor amplifiers can be used at frequencies in excess of 100 GHz in a wide range of applications requiring small size, low-noise figure, broad bandwidth, and low to medium power capacity.

1.1 Design of Microwave Transistor Amplifiers Using S Parameters

The objective of the project is to design a high gain amplifier which will rely on the terminal characteristics of transistor represented by S-parameters. At microwave frequencies 50 transmission lines and 50 termination are commonly used to measure the S parameters of a two-port network. Microwave amplifiers combine active elements with passive transmission line circuits to provide functions critical to microwave systems and instruments. The history of microwave amplifiers begins with electron devices using resonant or slow-wave structures to match wave velocity to electron beam velocity. The design techniques used for BJT and FET amplifiers employ the full range of concepts we have developed in the study of microwave transmission lines, two-port networks and Smith chart presentation. The development of S-parameter matrix concepts grew from the need to characterize active devices and amplifiers in a form that recognized the need for matched termination rather than short- or open-circuit termination.

Fig (1.1): A two port network with general source and load impedance

The gain of an amplifier is the ratio of output to input power or amplitude, and is usually measured in decibels. It can be classified as:

1.2.1 Power Gain:

It is the ratio of power dissipated in the load ( Z L ) to the power delivered to the input of the two port network. This gain is independent of ( Zs ). G=PL / Pin It is the ratio of power available from the two port network to the power available from the source. It depends on ( ZS ) but not on ( ZL ). GA =Pavn / Pavs

1.2.2 Available Gain:

1.2.3 Transducer Power Gain:

It is the ratio of the power delivered to the load to the power available from the source. This depends on both ( Zs ) and ( ZL ). GT =PL / Pavs

Fig (1.2): General transistor amplifier circuit

A microwave transistor amplifier can be modelled by the above circuit, where a matching network is used on both sides of the transistor to transform the input and output impedance (Zo) to the source and load impedances (ZS) and (ZL).
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The most useful gain definition for amplifier design is the transducer power gain, which accounts for both source and load mismatch. We can define separate effective gain factors for the input (source) matching network, the transistor itself, and the output (load) matching network as follows:

The overall transducer gain is GT =GS GOGL.

1.1 Design Methodology

An amplifier takes a low or intermediate level signal and significantly boosts its power level. At low frequencies this might be a trivial design which would only involve the careful choice of a DC bias circuit designed for maximum power output. But our chosen amplifier design is designed to operate at the microwave frequency of 2.4 GHz. When operating at this frequency, transmission line theory comes into the picture. The high frequency and short wavelength of microwave energy make for difficulties in analysis and design of microwave components and systems. Matching of the input and output of the transistor must be considered and designed around. A typical block diagram of a single-stage RF amplifier is shown below.

Fig (1.3): Basic Amplifier Circuit

This was the basic topology that we adhered to through our design procedure. The basic design flow for this topology is as follows: Choose an Microwave Transistor based on design specifications.
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 Design a DC Biasing circuit for desired operation. Design the Input and Output Matching Circuits based on the desired type of amplifier: Low-Noise Amp, High-Gain Amp, or High-Power Amp.

1.3 Stability:
In a two-port network, oscillations are possible if the magnitude of either the input or output reflection coefficient is greater than unity, which is equivalent to presenting a negative resistance at the port. This instability is characterized by |in|>1 or |out|>1 Because in and out depend on the source and load matching networks, the stability of the amplifier depends on S and L as presented by the matching networks. Thus, we define two types of stability: 1.3.1 Unconditional Stability: The network is unconditionally stable if |in|< 1 and |out| < 1 for all passive source and load impedances (i.e., |S|< 1 and |L|< 1) and if K > 1, < 1.

||=| S11S22 - S12S21|<1 1.3.2 Conditional Stability: The network is conditionally stable if |in| < 1 and |out| < 1 only for a certain range of passive source and load impedances. This case is also referred to as potentially unstable.

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These are defined by circles, called stability circles, that delimit linl = 1 and lLl= 1 on the Smith chart. The radius and center of the output and input stability circles are derived from the S-parameters. While K - test stated earlier are mathematically rigorous condition for unconditional stability, it cannot be used to compare the relative stability of two or more devices since it involves constraints on two separate parameters. Recently, however, a new criterion has been proposed [7] that combines the S parameters in a test involving only a single parameter, , defined as

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2. High Electron Mobility Transistor

High electron mobility transistor (HEMT), also known as heterostructure FET (HEFT) or modulation-doped FET (MODFET), is a field effect transistor Incorporating a junction between two materials with different band gaps (i.e., a heterojunction) as the channel instead of a doped region, as is generally the case for MOSFET. A commonly used material combination is GaAs with AlGaAs, though there is a wide variation, dependent on the application of the device. Devices incorporating more Indium generally shoe better high-frequency performance, while in recent years nitride HEMTs have attracted attention due to their high-power performance.

Fig.(2.1): Typical Structure of HEMT showing outline dimension

2.1 Introduction to HEMT:

To allow conduction, semi conductors are doped with impurities which donate mobile electrons (or holes). However, these electrons are slowed down through collisions with the impurities (dopants) used to generate them in the first place. HEMTs avoid this through the use of high mobility electrons generated using the heterojunction of a highlydoped wide-band gap n-type donor-supply layer (AlGaAs in our example) and a non-doped narrow-band gap channel layer with no doping impurities.

2.2 Electrical Characteristics:

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PART NUMBER PACKAGE OUTLINE

SYMBOL S GA NF Gm IDSS VP IGSO PARAMETERS ANDF CONDITIONS Associated gain1, VDS=2V, ID=10mA, f=12GHz Noise Figure1, VDS=2V, ID=10mA, f=12GHz Transconductance, VDS=2V, ID=10mA Saturated Drain current, VDS=2V, VGS=0V Gate to Source cut-off voltage,VDS=2V,ID=100uA Gate to source Leakage current, VGS=-3V UNITS dB dB mS mA V uA MIN 12 40 15 -0.2 -

NE3210S01 S01
TYP 13.5 0.35 55 40 -0.7 0.5 MAX 0.45 70 -2.0 10

Fig (2.2): Table of Electrical characteristics of HEMT

2.3 Version of HEMTs 2.3.1 pHEMT

In semiconductors, the discontinuities form deep-level traps, and generally reduce devices performance. A HEMT where this rule is violated is called a PHEMT or pseudomorphic HEMT. This is achieved by using an extremely thin layer of one the materials, so thin that the crystal lattice simply stretches to fit the other material. This technique allows the construction of transistors with larger band gap differences than otherwise possible, giving them better performance.

2.3.2 mHEMT
Another way to use materials of different lattice constants is to a place a buffer layer between them. This is done in the mHEMT or metamorphic HEMT, an advancement of the pHEMT. The buffer layer is made of AlInAs, with the indium concentration graded so that it can match the lattice constant of both the GaAs substrate and the GaInAs channel. This brings the advantage that practically any Indium concentration in the channel can be realized, so the devices can be optimized for different applications.

2.4 HEMT Operation:

Electrons from the n-type region move through the crystal lattice and many remain close to the hetero-junction. These electrons for a layer that is only one layer thick forming what is known as a two dimensional electron gas. Within this region the electrons are able to move freely because there are no other donor electrons or other items with which electrons will collide and the mobility of the electrons in the gas is very high. A bias applied to the gate forms as a schottky diode is used to modulate the number of electrons in the channel formed from the 2-D electron gas and in turn this controls the

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conductivity of the device. This can be compared to the more traditional types of FET where the width of the channel is changed by the gate Bias.

2.5 Applications:
The HEMT was originally developed for high speed applications. They are widely used in low noise small signal amplifiers, power amplifiers, oscillators and mixers operating at frequencies up to 60GHz. In fact HEMT devices are used in a wide range of RF design applications including cellular telecommunications, direct broadcast receivers-DBS, radar, radio astronomy, and any RF design applications that requires a combination of low noise and very High frequency performance. HEMT based MMICs are widely used to provide the required level of performance in many areas.

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3. Design procedure:
The design procedure is based in strictly on small-signal S-parameters for the design of M1 (the input matching circuit) and M2 (the output matching circuit). It also address the proper form of biasing for maximum output power. The design flow is as follows: Obtain the transistor S-parameters for the determined bias values by measuring a transistor (HEMT).This transistor was chosen because it met all of the requirements for our target specifications. Design the Bias circuit for the transistor in order to achieve maximum gain. Define the optimum load line for maximum output power and determine the resistance value, RL and capacitance value CL corresponding to this load line. Design output matching network for maximum output power. Determine S11 with output matching network at output and design input matching circuit for zero reflection. The smith Chart is then used to define the lossless output circuit by matching RL to 50ohm at the design frequency. With the designed output matching circuit, the input matching circuit, it can then be designed using S11. Input matching circuit should be designed for zero input reflection. To do this, the smith chart is used by matching S11 to 50ohm at the designed frequency.

3.1 Design environment: ADS

The amplifier needs to be designed in the software environment if we actually want to build it. There are several software packages in the industry that are used for the design and simulation of RF circuits. The one that we have chosen is ADVANCED DESIGN SYSTEM. The basic circuit for the measurement of the HEMT parameters was first designed in the software and then measured.

Fig (3.1): Circuit designed in ADS for HEMT parameter measurement

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3.2

Smith Chart

The Simulation results of this HEMT are observed in the Software and the value of S11 and S22 in magnitude and phase are taken down. These are then plotted on the Smith chart and the values of transmission line length and stub lengths are calculated.

Fig (3.2): The Smith Chart showing Resistance and impedance circle.

3.3

Basic HEMT mounted on a 50 Impedance line

This Circuit is then fabricated and tested at the required bias for getting the Sparameters.

Fig (3.3) Basic HEMT mounted on a of 50 Impedance line 18

4. Different type of Biasing

There are various bias techniques for obtaining maximum gain of the amplifier which are as follows: 4.1 1st type of biasing: In this biasing, At the Gate terminal, the capacitor C1 is worked as for blocking dc frequency and given allowance to RF frequency. After calculated transmission line lengths, stub lengths, /4 termination lines, 50 lengths and widths, if there was any dc component then capacitor C3 worked as open circuit for RF frequency and short circuit for DC frequency, which in turn faded to the ground. Repeat the Same as in Drain terminal and both sources were properly loop grounded.

Fig (4.1): Schematic Circuit Diagram made in ADS of 1st type of biasing

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The Constructed circuit and their results in ADS and VNA is shown below as:

Fig (4.2): Constructed Circuit

Fig (4.3): Simulated results showing the values of S11, S21, S12, S22 on ADS software.

Fig (4.4): Tested results showing the values of S11, S21, S12, S22 on VNA

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4.2 2nd type of biasing:

Fig (4.5): Schematic Circuit Diagram made in ADS of 2nd type of biasing.

The Constructed circuit and their results in ADS and VNA is shown below as:

Fig (4.6): Constructed Circuit

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Fig (4.7): Simulated results showing the values of S11, S21, S12, S22 on ADS software.

Fig (4.8): Tested results showing the values of S11, S21, S12, S22 on VNA

4.3 3rd type of biasing: In this biasing, we have used fifth order filter formed from micro-strip transmission line for Blocking DC frequency and giving allowance to RF frequency.

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Fig (4.9): Schematic Circuit Diagram made in ADS of 3rd type of biasing.

(4.10): Simulated results showing the values of S11, S21, S12, S22 on VNA

Note: In 3rd type of biasing, the obtained circuit dimension is so large. So, it does not seem to be feasible to make it commercially and practically. (From the above three biasing method done and testing on a VNA, we got the result that implies 1st type of biasing is better than compare to others at 1.57GHz frequency. So, we will work on this module and obtain a maximum gain with matching network.)

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5. TRL Calibration:
For any transistor the data sheet will be provided by the manufacturer. These parameters will be measured in the industry with their measuring instruments and nearly ideal conditions. So we need to model the transistor for our design environment. In this experiment S-parameters of the transistor are extracted at required biasing conditions. whenever S-parameters of any device is measured the reference positions will be at the edge of the coaxial to microstrip connector .For measuring the S-parameters at the edge of the device pads it is required to shift reference plane. There are many techniques to shift reference planes in this experiment TRL(Through-Reflect-Line) technique is used. TRL is an approach to 2-port calibration that relies on transmission lines rather than a set of discrete impedance standards. There are three key advantages gained when using transmission lines as reference standards Transmission lines are among the simplest elements to realize in many non-coaxial media. The impedance of the transmission lines can be accurately determined from physical dimensions and material properties. Transmission lines have traditionally been used as standards and well understood. TRL refers to the three basic standards in the calibration process: THRU: connection of port 1 and port 2 with a short length of transmission line REFLECT: connect identical one port high reflection coefficient devices to each port LINE: insert a short length of transmission line between port 1and 2(different line lengths are required for THRU and LINE). In this experiment modeling is done from f1= 2GHz to f2= 4GHz (f1:f2=1:2 if this is greater than 2.5 then it is required to use more than one kit for calibration). Standards: THRU=Distance between the connectors-Device length; =64mm-2.5mm =61.50mm REFLECT=THRU /2; =30.75mm LINE=THRU+g/4; =61.50mm+29.87mm =91.37mm Where g=/ r (at frequency= (f1+f2)/2, r =2.57). The constructed circuits is shown below as:

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Fig (5.1): Circuits after TRL calibration

Technical Details: Transistor: HJ-FET NE3210S01 Substrate: Dielectric constant=3.2 Height=0.762mm The transistor which is mounted on the micro-strip line is a junction field effect transistor There is a symbol k on the transistor, to the right of k it is gate, and to the left of k it is drain and the other two pins which are opposite to each other are source pins . In this experiment transistor is operated in common source configuration, Give biasing from the network analyzer by connecting required dc voltages at the backside of VNA in proper order. While grounding the transistor source terminal there should be at least three via holes made to ensure the stability, the grounding pads should be closed to device. PROCEDURE: (1). First test the transistor with a multi meter whether it is properly working. The transistor is depletion mode transistor, so without any bias drain & gate is connected to each other. Connect the meter probe as below you will observe the result and keep the meter in diode/beep mode. +ve terminal common terminal result Source Drain Beep sound Drain Source Beep sound Drain Gate 1 Gate Drain 0.75 Source Gate 1 Gate Source 0.75 (2) .Switch on the ROHDE&SCHWARZ ZVB-20 VNA, set the start frequency to 1GHz and stop frequency to 2.145GHz. (3). Connect the transistor circuit to VNA such that gate to 1st terminal and drain to 2nd terminal.

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(4).Connect two cables at back side of VNA, connect the Gate biasing cable to variable supply/battery through potentiometer and initially maintain it at -1 volt. (5).Connect the Drain biasing cable to variable supply/(battery through potentiometer) Through ammeter and initially maintain it at 0 volt. (6).Slowly increase gate biasing voltage (in steps of 0.1volts) to -0.6 volts and drain biasing voltage (in steps of 0.1volts) to 1.8 volts mean while observe S -parameters, observe that they are comparable with data sheet values. (7).If there are any abrupt changes, verify the circuit with spectrum analyzer such that there will be any oscillations occurring in the circuit at those biasing voltages. (8).Connect the three TRL standards one by one and check whether they behave Like nearly ideal elements. (9). Set the power level to -20 dB. (10). Set start and stop frequencies to 2GHz and 4GHz respectively. (11).Press cal button. (12).Do correction off. (13).Go to more . (14).Go to call kits. (15).Avail connection type. (16).Go to user conn1, Remove sex less option, click on TEM. (17).You will get TEM, enter effective r . (18).Add kit, set name. (19).Remove Agilent mode. (20).Copy standards from user standard ideal kit, all, ok. (21).Go to reflect (f), set min and max frequencies to 2GHz and 4GHz respectively (ffemale connector). (22).Go to thru (f-f), set min and max frequencies to 2GHz and 4GHz respectively. (23).Go to line -1(f-f),modify offset, enter g/4 line length, set min and max frequencies. to 2GHz and 4GHz respectively. (24).Go to more (2/2). (25).Start cal, two port p1-p2, TRL. (26). Click on same connector type at all ports. (27). Set userconn1 (m) for port1, and port2, go to next. (28).Connect THRU, click on the box. (29). Connect LINE, click on the box. (30). Connect reflect to port 1, click on the box. (31). Connect reflect to port 2, click on the box. (32).Apply, calibration is completed. (33).To save calibration file, go to file save/ file name, file format .zvx. (34).Again measure transistor S-parameters as explained earlier. (35).Obtain the S parameter data file in magnitude and angle form. (36).For this first add all 4 traces (i.e., s11, s21, s12, s22). (37).Go to file, trace data export complex data, give file name, specify location, select touch stone .S2Pformat Lin-mag phase, save it. (38).Plot the measured S-parameters and parameters given in the data sheet using ORIGIN software.
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(39).write the observations. References: (1).Rajesh Kumar Prabhakaran-M.Tech thesis CARE IIT DELHI GaAs HEMT modelling and design of broadband mmic spdt switch-2006 (2). http://www.cel.com/pdf/datasheets/ne3210s1.pdf (3). http://www.cel.com/pdf/press/TRL.pdf .

After TRL calibration, we had a good result as tested on VNA is shown below as:

Fig (5.2): Tested Results showing S11, S21, S12, S22 on VNA after TRL calibration.

1. After getting the datasheet from VNA, we take the file dat format to import in the
design circuitry. To get the data from VNA, go to: Filetrace dataExport complex data Save it in a certain folder, and then take it in a floppy using following commands:
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cd/ cd <folder name> copy*.*A: The file gets copied in the floppy and can be further used.

Frequency (GHz) 1.00 1.15 1.30 1.45 1.57 1.70 1.85 2.90 2.145

S11 dB -8.44 -7.69 -5.00 -3.04 -2.77 -1.14 -1.13 -1.58 -1.71 Angle 128.87 109.64 80.93 40.89 8.92 -24.04 -64.15 -114.4 -122.9 dB -5.34 -2.84 1.82 7.96 10.55 12.77 12.44 8.87 7.95

S21 Angle -172.7 -165.3 -147.2 -163.1 172.03 142.95 104.72 5.71 50.44

S12 dB Angle -35.36 -36.09 -40.06 105.88 -46.40 -87.89 -35.29 146.45 -31.65 62.88 -40.76 64.99 -34.73 32.97 -3.58 13.35 -36.28 21.53

S22 dB -7.44 -8.02 -5.34 -4.74 -5.66 -4.97 -5.07 -4.99 -5.01 Angle 145.48 126.82 96.69 5.49 2.34 -10.06 -53.51 -103.9 -109.3

Fig (5.3): Table of S-parameter after importing data from VNA.

2. After getting the datasheet from VNA, we once again reconfigured our stub and
transmission line lengths of matching network for the same circuit as calculated from smith Chart to achieve our goal (showing higher gain as compared to the previous circuit).

Fig (5.4): Schematic Circuit Diagram having matching network made in ADS after TRL calibration.

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The simulation result of this circuit in ADS is shown below as:

Fig (5.5): Simulated results showing the values of S11, S21, S12, S22 on ADS software.

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6. Optimization
For accurate result with maximum gain lies at the peak of 1.57 GHz, we optimized the matching network parameters (stub lengths and transmission line lengths) on ADS in which a black box was inserted that had used imported s parameter datasheet from VNA after TRL calibration.

Fig (6.1): Schematic Circuit Diagram made in ADS of 1st type of biasing.

After that, the circuit with new set of matching network parameters is simulated on ADS which had increased value of maximum gain. The result is shown below as:

Fig (6.2): Simulated results showing the values of S11, S21, S12, S22 on ADS software.

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7. IntelliCAD
7.1 Generating Layout After simulation, we got the satisfying result; the layout is generated from the software. But for layout generation we need to remove the resistor, capacitor and bias voltages by replacing them with a 0.2mm thin strip-line as shown below:

Fig (7.1): Circuit used for layout generation.

Fig (7.2): Method of generating layout

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After generating the layout, we remove the ground. The generated layout is as shown:

Fig (7.3): layout of the design

Now we go tofile generate artwork. In the artwork we remove the lines where we need to mount the components and export the file in dxf format.

Fig (7.5): Export to DWG/DXF format.

Fig (7.4): Method of generating artwork

The dxf file is opened in intellicad and then the mask is generated as shown below by removing the line wherever required. 7.2 Steps in the IntelliCAD Ctrl + A Explode (breaks in individual entity)
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 Ctrl + A

Properties Layer (by default) cond change to 0 Click OK Colour of the design will change from Green to White

Ctrl + A Click cond

Settings right click delete

Explore layer delete Modify Break

To remove the unwanted lines, select the line Save as AutoCAD Version 2.5 ASCII DXF (dxf)

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 Fitting the design in a rectangle. Insert Rectangle Now give one corner as (0, 0) and other one as per the requirement, let here (x, y) Now select the full circuit right click move place the design in the rectangle. If some lines remain small then click Modify extendclick on the line till where you need to extend. Ctrl + A explode right click move

Ctrl + A Base point (0, 0) Move to (10, 10) Save the file again.

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 Copy the file to TOOL folder in C drive.

7.3 Masking on Rubylith Sheet The mask is cut on the rubylith and then is fabricated on the substrate using photolithography. The mask is shown as:

Fig (7.6): Mask prepared on Rubylith Sheet

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8. FABRICATION
Steps of fabrication: 1. Cleaning of substrate: Cleaned the substrate thoroughly with cotton using vim powder and washed it under running water. Kept the substrate in acetone to remove moisture and dry it in front of hot blower.

Fig (8.1): Acetone solution and hot blower.

2. Applying Photo Resist: Used a spinner to apply a uniform and precise coating of Photo Resist on the substrate.

Fig (8.2): A Vacuum spinner

3. Prebaking in oven: Putted the substrate in the oven for pre baking for about 5-10 min for pre baking.
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Fig (8.3): Oven

4. UV exposure: We contacted the mask (film side) with coated substrate (PR side) by aligning and fixing it with cello tape, place it in the UV exposure for 2-2.5 min.

Fig (8.4): UV Exposure

5. Developing: After exposing separate the substate. Putted it in the develpoing solution (Trichloro Ethylene) for about 30-45 sec, further putted it in the fixer (Acetone) for about 10-20 sec. Now blow it dry in front of heater.

Fig (8.5): Developer and fixer solution

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6. Applying Dye: Applied dye on the printed side of substate to protect the photoresist at the time of the chemical etching and kept it agin at the oven for post baking for 4-5 minutes.

Fig (8.6): Pattern shown after applying dye on substrate.

7. Etching: The process of etching is carried out using ferric chloride solution till the copper layer gets etched away.

Fig (8.7): State in between the Etching.

8. Removal of Photoresist & Dye: Removal of photoresist and dye can be carried out using acetone.

Fig(8.8): Final circuit after Etching.

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9. Soldering and Testing

After the completion of whole process we had proceed for mounting of SMDs (resistors and capacitors and HEMT).

Fig (9.1): Constructed circuit after mounting SMDs and HEMT

After this, we proceeded for testing of circuit on VNA, the result is shown below as:

Fig (9.2): Tested results showing the values of S11, S21, S12, S22 on VNA.

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Now, adjusted the voltage from power supply and are checked the maximum gain at different frequencies.

Fig (9.3): vector Network analyzer and Power supply.

We got a maximum gain of 17.35 dB at 1.57 GHz .

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10. Operation with a Single power supply

The amplifier circuit module is further developed for operating with a single power supply, which had comprises of diode, capacitors and inductors. The voltage of - 0.7V is feed to the gate through the diode used and +4.3V at the drain by power supply.

Fig (10.1): Construed circuit for operating by a single power supply.

Fig (10.2): Tested results showing the values of S11, S21, S12, S22 on VNA.

Here, we are seeing that we got our maximum gain of 16.12 dB that was our desired resu
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Conclusion
The aim of the project was to design and develop a high gain amplifier at 1.57GHz. The results obtained by initial calculations and with different biasing conditions did not give the satisfactory results. There was a large shift in the value of gain obtained in the simulation due to improper stub lengths used in the matching network design and bias voltages used for testing in VNA. But the values of the stub lengths obtained after end correction, as a TRL calibration gave the result, which was very close to the desired results. Thereafter to get the exact results, the amplifier designed was optimized on ADS. It was observed that with new set of stub lengths and matching network the gain was improved with good figure of merit. The input match also adjusted to improve the input return loss. Finally, the circuit was operated with single power supply with low power of consumption.

Thus, The Maximum Gain Amplifier is successfully designed to give maximum gain with high figure of merit of 16.12 dB at 1.57 GHz with a supply of +4.3V at drain and -0.7V at the gate of the HEMT.

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References
1. Microwave Engineering by David M. Pozar. 2. Microwave Transistor Amplifier Analysis & Design by Rohit Gawande and Richard Bradley. 3. Practical RF Amplifier Design by Ken Payne. 4. Microwave Amplifier Design (part 1) by steve Garcia, Jaime cordoba & Inderpreet Obhi. 5. Microstrip Filters for RF/Microwave Applications by Jia-Shen G.Hong & M.J.Lanaster. 6. Stripline-like Transmission lines for Microwave Integrated Circuits by Bharathi Bhat & S K Koul. 7. Advanced Design System. 8. IntelliCAD. 9. Wikipedia.

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