N e w method to bias CMOS cascode amplifiers

F. Cortigiani S . Rocchi V. Vig no Ii

Indexing terms: Cuscode amplifiers. SPICE simulations

Abstract: The authors present a new method for biasing AC-coupled cascode amplifiers. The proposed design allows the correct DC biasing with a single reference signal as well as a single power supply. A start-up circuit is added for correctly biasing the cascode amplifier at power on. SPICE simulations based on a 0 . 8 CMOS ~ technology are included.

or C~xJJ(z,. Moreover, VXylz,(K) means that the voltage Vxycz, is a function of the quantity K . In Fig. 1, the static CA arrangement is shown, which uses two bias voltages ( Vc, and V,) and a single power supply ( Vdd) to control the bias current I,,,. In this, and in all the following circuits, unless it is differently specified, the p substrates are connected to ground and the n substrates are connected to Vdd.Let us assume that the channellength modulation is neglected and the following condition is verified [2]:

Introduction

Cascode amplifiers (CAS) are widely used in VLSI analogue design to achieve a lower input capacitance and a higher gain (if used with high-impedance loads) than in conventional inverter amplifiers [11. Nevertheless, CAS need an additional DC bias voltage or a dual, unbalanced power supply to ensure the correct performance. This paper proposes a solution using CAS with a single power supply and only one DC reference voltage, although an additional MOS transistor (MOST) and a decoupling capacitance are necessary. Moreover, the presented solution has been completed with a start-up circuit to correctly bias the CA at power on.

Vthn( Vel), L2 and W2are, respectively, where K',,, VthnO, the transconductance parameter, the threshold voltage for Vss = 0, the threshold voltage for V,, = Vel, the channel length and the channel width of the n channel MOST M2. The current I,,, is then given by

vc*+t
I

I'D0

$
'd d

"dd

9 I

V0"t

vc1 o+

+
a

6
b

Fig. 1

CA bias with a unipolar power supply and two control voltages

Fig.2

CA with the proposed biasing circuit

a Vc control-voltage generation circuit b CA with a static feedback between drain and gate of M,,

Circuit design

In this paper, a voltage or a capacitance between terminal x and y of an M , MOST is indicated as Vxylz,
0IEE, 1998
IEE Proceedings online no. 19982388 Paper first received 16th September 1997 and in revised form 18th May 1998 The authors are with Dipartimento di Ingegneria dell Informazione, Universita di Siena, Via Roma. 56 - 53100 Siena, Italy
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where W, and L, are the channel width and channel length of Min. It is difficult to achieve this biasing condition by using a unipolar power supply, owing to the simultaneous need for a high-input impedance for the amplifier as well as a DC decoupling for the dynamic input signal. To solve this problem, the circuits in Fig. 2a and b are proposed. The circuit in Fig. 2a generates a control signal Vc which is applied to the gate of M 2 in Fig. 2b. Vc is sufficient to set the bias current for the circuit in Fig. 2b, thanks to the static feedback due to Mf(whose bulk is connected to the source) that forces
IEE 'roc.-Circuirs Devices Syst., Vol. 145, No. 6 , December 1998

VD9,,,, = 0. In detail, Mf is in the weak inversion region (V,,,, = 0), and therefore the drain current of Mfis ruled by [2]:

where Io and q are process parameters, Vr/l,(VSB(f,) is the threshold voltage of an n channel MOST when VsB - VS,,, and V, is equal to kTlq ( k is the Boltzmann constant, T is the device temperature in degrees Kelvin and q is the electron charge). Thanks to the decoupling capacitance Cl,, fD(f) can be assumed equal to 0, and therefore V,,, = VDGi,, = 0. In these conditions, the control signal VCis steered by the relationship
v C
vGS(C1)

fixed voltage nodes of the circuit (V,,, Gnd). Cp has to be charged at the correct value (- Vc12) before the CA reaches the static conditions described in the previous Section. An NMOS switch, with source and bulk interconnected, was therefore inserted between the Mcl. and Mi, gates to charge Cp, in the start-up phase, with a time constant much lower than the one associated with Cp and the M, current (Fig. 3). The switch must be closed at the start up for a time interval that ensures the C, charging, which depends on Irer, Ci,and the MOST dimensions. It must be highlighted that a careful design of C,, guarantees the circuit biasing against power-supply spike problems: the higher the decoupling capacitance value, the higher the CA immunity to power-supply spikes.

+@F(@+E)
(4)
for the control branch of Fig. 2a, and by the relationship
vC

+ v G S ( C 2 ) = K h n 0 -!r K / L ~ ( ~ S B ( C ~ ) )

liii)

lii)

li)

= vGS(zn)+ V G S ( 2 ) = KhnO

+ Khn(VSB(2))
(5)
Fig.4

1
time, ps

Static current I,, against tinw for the circuit of Fig. 3

The power on and a 2 p . s Res pulse are simulated at f = 50011s (i) Ire, = 2 0 d ; (ii) Ire, = 40pA; (iii) I,<,, = 60p.A; (iv) I.', = XOp.4

for the gain branch of Fig. 2b. If L,lWin = Lcl/WCl and L21W2 = Lc21WO, then ID0 = I,..,and the circuit is correctly biased. This is true because Vthn( VsB,,,) is IJ',,~,~,). In fact, the constraint necessarily equal to Vthn( that VGs(;,,+ VGs12, is equal to a constant value makes ID0 = Zref the unique solution for the static current through Mi, and M2: whenever the value of Vth,z( VsBla,) is different from Vtlln( VsB,21), it forces a static current through Mi, different from the static current through M,. In dynamic conditions Mf, whose channel conductance is virtually zero and whose drain is connected to a low impedance point, does not seriously affect the gain transfer function.

Simulation results

SMin
Vout MC1

Fig.3

CA with biasing and start-up circuits

2.1 Power on phase The proposed analysis is not valid in the start-up phase. In the circuit configuration of Fig. 2, the gate of M , is floating, and a capacitance Cp = C;, + CGs(inI + CGBlin, +C , is present between the Mi, gate and the
IEE Proc.-Circuits Devices Svst., Vol. 145, No. 6, December 1998

The circuit analysis, described in the previous Section, was validated with SPICE simulations on n-channel CAS with different aspect ratios, reference currents and active load configurations (MOSIS HP 0.8 pm parameters were used). Fig. 4 shows the static current ID0 against time for the CA in Fig. 3, when Vs is shorted and Iref varies in the range 20 - S O p A with steps of 20pA. The behaviour reported in Fig. 4 was obtained for the CA configured with a p-channel diode load, with a C,, equal to 30pF (this value of decoupling capacitance C,, is a good choice both for decoupling and for spike immunity purposes) and with the MOST channel sizes shown in Table 1. In this simulation, the power-on occurs at t = 500ns, and a 2p.s pulse (Res pulse) is issued at the same time to the NMOS switch to ensure the Cp charging. The static current ZDo approaches the correct value within the res pulse for each one of the considered frefvalues. The temperature stability of the bias current ID0 is satisfactory: for each working temperature in the standard range 0-1 00C the Res pulse issues the correct VGSlrn, voltage. Problems may arise for a temperature change that occurs after the end of the Res pulse; nevertheless, a second Res pulse can be issued when the circuit reaches the working temperature. In any case, if the circuit design used in the above simulation is considered, a 100C step temperature change can be recovered by the circuit itself in a time interval of a few tens of seconds (in the worst case), with an absolute error lower than 200nA for IDo. Curve (i) of Fig. 5 shows ID(,,,, against time when Vs is a 20MHz sinusoidal signal with a lOOmV peak-topeak value, Irq is equal to 60pA and C,, is equal to 30pF. Curve (ii) of Fig. 5 shows Vddagainst time: the power on occurs at t = 500ns, and two lOns 1V power-

44 1

712

previous Section, do not affect the working of the circuit. In this simulation, a I p s Res pulse is issued at power on (1 ps is enough to charge Cp if I,.ef is equal to 60P.A).
4
Conclusions

1 ,A/.!,
0.0
0.5

j 2

1.5 2.0 2.5 3.0 time,ks ciizd V,,,, czguinst tiniefor the circuit of Fig. 3 Fig.5 l,,,,,,, (i) Drain current of M,, when input signal Vs i s a 20MHz tone with amplitude

1.0

50mV (ii) Vdil: the power on and

ii 1 p Res pulse occur at f = 50011s: two 1 V Ions power supply spikes are applied at f = 2 p and t = 2 . 5 ~

In this paper, a circuit is proposed by which, in the presence of a single power supply, a unique reference voltage is used to set the bias current of AC coupled cascode amplifiers. The working of the circuit is proved both by theoretical discussions and by specific SPICE simulations.
5
Acknowledgments

Table 1: Transistor channel dimensions used in the simulations of Figs. 4 and 5

Mi, M2
1.2 12

The authors wish to thank G. Palmisano and G. Palumbo for their comments and suggestions.
6
References

Mp,
1.2 1.2

Mf 0.8
1.2

Mc,
1.2 12

Ma
1.2 12

NMOSswitch
0.8
12

L, pm

1.2

W.um 12

supply spikes are issued to the CA, respectively, at t = 2p3 and t = 2 . 5 ~ These . spikes, as anticipated in the

1 ABIDI, A.A.: On the operation of cascode gain stages, 1EEE J. Solid-Srute Circuits, 1988, 23, ( 6 ) , pp. 1434-1437 2 GEIGER, R.L., ALLEN, P.E., and S T R A D E R , N.R.: VLSI design techniques for analog and digital circuits (McCraw-Hill, Singapore, 1990)

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I E E Pruc.-Circui/s Devices S y s f . . Vol. 145. N o . 6 , Decer,ihrr 1998