COMPUTER PROGRAMMING I (TA C162) ( )

Lecture 13 Memory y Design g

Todays Agenda

Memory Design by an Example Von Neumann Model

Processor P Memory Input / Output O Control Unit

Saturday, February 13, 2010

Biju K Raveendran@BITS Pilani.

Memory

Is made up of a large number of locations. Each location is uniquely identifiable. Each location has ability to store a value. The unique identifier associated with each memory location l ti i is called ll d as it its address. dd

Saturday, February 13, 2010

Biju K Raveendran@BITS Pilani.

Address

Address Space & Addressability

Unique identifier associated with each memory location Total number of uniquely identifiable locations (usually a power of 2) With N bits; we can uniquely identify 2N locations Number of bits stored in each memory address location (e.g., byte-addressable or word-addressable) Address Space ???

Address Space

Addressability

Example: 16 M Byte Memory (24 bit Address line)

16 x 220

Addressability = ???

(1 Byte)
Biju K Raveendran@BITS Pilani. 4

Saturday, February 13, 2010

Memory

We can build a memory

a logical k m array of stored bits.

Address Space: number of locations (usually ( yap power of 2) )

k = 2n locations

Addressability:
number of bits per location m bits
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Building a Memory

Each bit is a gated Dlatch

WE

A[1:0]

Each location

consists of w bits (here w = 1) n locations l ti means l log2n address bits (here 2 bits) decoder circuit translates address into 1 of n locations

Addressing

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Biju K Raveendran@BITS Pilani.

Memory Example
A 22 by 3 bit memory Two address lines A[1:0] Three Data lines D[2 0] D[2:0] One control line: WE
Od D-latch

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Biju K Raveendran@BITS Pilani.

22 x 3 Bit Memory
address word select word d WE input bits
Write enable

MUX
Address decoder

output bits
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Reading a location in memory

Saturday, February 13, 2010

Biju K Raveendran@BITS Pilani.

22 x 3 Bit Memory

2 bit Addresses

Address space is 4 locations

Addressability is 3 bits Address decoder

Input A[1:0] 4 outputs Selects exactly one of the 4 outputs (corresponding to the wordline being addressed)

Each bit of the memory is ANDed with its wordline and ORed with the corresponding bits of the other words

Multiplexer
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Saturday, February 13, 2010

Primary Memory

Two basic kinds of RAM (Random Access

Memory)

Static RAM (SRAM)

Fast, maintains data as long as power applied i.e. volatile l til Slower b Sl but d denser, bi bit storage d decays must be b periodically refreshed

Dynamic RAM (DRAM)

Also, non-volatile memories: ROM, PROM, flash... flash

Biju K Raveendran@BITS Pilani. 11

Saturday, February 13, 2010