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IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 20, NO.

6, NOVEMBER 2005

1441

TRIAC Dimmable Ballast With Power Equalization


Stephen T. S. Lee, Member, IEEE, Henry Shu-Hung Chung, Senior Member, IEEE, and S. Y. (Ron) Hui, Fellow, IEEE
AbstractA two-stage, two-wire TRIAC dimmable electronic ballast for uorescent lamps is presented in this paper. It is constructed by using a yback converter as the input power factor corrector to supply a half-bridge series-resonant parallel-loaded inverter to ballast the lamp. The yback converter is operated in discontinuous conduction mode so that the ltered input current prole is the same as the TRIAC-controlled voltage waveform. The switches in the inverter are switched at a constant frequency slightly higher than the resonant frequency of the resonant tank. Based on the constant average input current characteristics of the inverter, the dimming operation is simply achieved by pulsewidth modulation control of the magnitude of the yback converter output voltage. No synchronization network is required between the input and output stages. In addition, a linear power equalization scheme is developed so that the dc-link voltage (and hence the lamp power) is in a linear relationship with the ring angle of the TRIAC. The average output voltage of the dimmer controls the equalized yback converter output voltage. Modeling, analysis, and design of the ballast will be described. A prototype was implemented to verify the experimental measurements with the theoretical predictions. Index TermsElectronic ballasts, uorescent lamps.

I. INTRODUCTION

N RECENT years, dimmable electronic ballasts for uorescent lamps are becoming popular. Of particular importance in the design of electronic ballasts are high power factor, low total harmonic distortion (THD), low electromagnetic interference (EMI), low lamp current crest factor, and low ickering [1]. In order to comply with the requirements of IEC1000-3-2 Class C appliances [2], commercially available products usually consist of two cascaded stages for the input power factor correction (PFC) and output high-frequency inversion [3]. A regulated dc voltage, for example 400 V, interlinks the two stages. Some specialized integrated circuits have been developed for this particular application [4], [5] to simplify the circuit schematics. For the input stage, boost- and yback-type preregulators are the most popular choices. For the output stage, either a voltage-fed or current-fed inverter [6] is usually chosen. A resonant tank circuit is used because of its distinct advantages of near-sinusoidal lamp current and high-voltage generation during the ignition period. The dimming operation is based on adjusting the switching frequency of the inverter so that the reactance of the series inductor can be varied and thus the lamp power can be controlled.

Manuscript received April 7, 2004; revised January 14, 2005. This work was supported by a grant from the Research Grant Council of the Hong Kong Special Administrative Region, China (Project CityU 1233/02E). Recommended by Associate Editor J. M. Alonso. The authors are with the Department of Electronic Engineering, City University of Hong Kong, Kowloon, Hong Kong (e-mail: eeshc@cityu.edu.hk). Digital Object Identier 10.1109/TPEL.2005.857560

In order to simplify the overall circuitry and reduce the manufacturing cost, many passive PFC circuits and single-stage electronic ballasts with dimming features have recently been reported [7][14]. Some of them minimize the circuit structure by integrating the switch in the PFC into one of the switches in the inverter. However, their structural elegance is offset by some performance discrepancies, such as high lamp current crest factor [7][9], asymmetrical lamp voltage and current waveforms [10], high dc-link voltage at low luminous level [11], [12], high component stresses [12], and narrow dimming range [11]. In order to achieve a desired dimming range and soft-switching of the switches in the inverter, the switching frequency of the inverter has to be varied in a single-stage system. This could result in lamp current and voltage waveform distortion. The dc-link voltage has to be set to a much higher value, which might be two to three times higher than the rated value of the supply voltage [11] for reducing the above problem. This aspect will be critical for countries having high-voltage mains supply, such as 220 V in Hong Kong, resulting in requiring a very high voltage dc-link capacitor for stabilizing the inverter input. Furthermore, existing dimmable ballasts are generally fourwire systemstwo for the supply mains input and the other two connecting to a variable dc voltage input (for example 010 V) or a variable resistor for dimming control. A TRIAC-based light dimmer itself cannot be used to perform the dimming operation for uorescent lamps. Recently, ballasts that can provide a dimming feature using a TRIAC-based dimmer at the supply mains have been proposed in [13] and [14]. However, the dimmer has to be modied in [13] so that the actual ring angle is varied within few degrees only. In [14], an ordinary dimmer can be used to adjust the luminous level of a compact uorescent lamp. The dc-link voltage is kept at a relatively constant value throughout the dimming range. Again, varying the switching frequency of the inverter changes the output luminous level, but the dimming range is relatively narrow. Concluding the above topologies, a two-stage structure is still considered a robust one because of its excellent operational characteristics. In this paper, a two-stage, two-wire TRIAC dimmable ballast is presented. The control methodology is simple and elegant. The power stage is constructed by using a yback converter as the input power factor corrector to supply a half-bridge series-resonant parallel-loaded inverter (HBSRI) to ballast the lamp. The yback converter is operated in discontinuous conduction mode (DCM) [15] so that the ltered input current prole is the same as the TRIAC-controlled voltage waveform. The switches in the inverter are switched at a constant frequency and duty cycle. Based on the constant dc input current characteristic in the inverter, a dimming operation is achieved by pulsewidth modulation (PWM) control of yback

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IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 20, NO. 6, NOVEMBER 2005

power of the lamp [16][18]. At the ac side, the input power of the ballast is

(1) and are the peak value and where is the rms value of is the input the angular frequency of the ac mains, and resistance of the yback converter at . If is normalized by the input power at , its normalis ized value

(2) is a correction factor for the where power equalization. It can be adjusted by controlling the duty cycle of the switch . Based on (2), one of the feasible approaches of dimming the lamp is to keep the duty cycle of the switch constant (i.e., is a constant and 1 and adjust . The input of the yback converter will be varied accordingly voltage will also be changed. Fig. 2 shows the relationand hence 1 varies from 1 to 0 as increases ships of for from 0 to rad. Due to the nonlinear characteristics, the output lamp power is sensitive to the variation of at the middle of the control range and is less sensitive at the two extremes (i.e., has diminished into 0.2 around 0 and rad). For example, when equals 2 3 rad (67% of the control range). In addition, the useful angular control range is restricted because the lamp might extinguish at a lower value of than the one with linear characteristics. In order to linearize the characteristics and increase the controllable range, a novel power equalization scheme (PEQS) is proposed in the following. A. Power Equalization Scheme The ideal linear Fig. 2. Mathematically characteristic curve is depicted in

Fig. 1. Two-wire TRIAC dimmable electronic ballast. (a) Circuit block diagram. (b) Circuit schematic of the equalization circuit (EQC).

converter output voltage. In addition, a novel linear power equalization scheme is derived so that the luminous level is in a linear relationship with the ring angle of the TRIAC. Modeling, design, and analysis of the ballast will be given. A prototype was implemented to verify the experimental results with the theoretical predictions. II. PRINCIPLES OF OPERATION Fig. 1(a) shows the circuit block diagram of the two-stage electronic ballast supplied from an ordinary TRIAC-based light dimmer. The power conversion stage of the ballast consists of and , ythe acdc diode rectier, input lter formed by back converter operating in DCM, and a HBSRI. The ballast is designed to perform a dimming operation for the ring angle of the dimmer varying from zero to . The input lter is used to smooth the pulsating input current of the yback converter so that the resulting input current of the ballast will follow ). The ythe output voltage prole of the TRIAC (i.e., back converter is designed to provide a dc voltage of low-ripple voltage for ensuring a low current crest factor on the uorescent of the lamp. As discussed in [16], the average input current HBSRI is relatively constant when the inverter is operating at a switching frequency close to the resonant tank frequency. Concan directly adjust the output trolling the dc-link voltage

(3) With this linearization, increases from 2 3 to 0.8 rad reaches (i.e., 144 about 80% of the control range) before 0.2. Extinction of the lamp can then be controlled to occur at a larger value of resulting in a high angular control range. In addition, the output power of the lamp has the same control sensitivity throughout the operating range. The average value of , is equal to

(4)

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Fig. 3. Relationships between V

and V

of the EQC.

Fig. 2.

^ and  with . (a) P ^ . (b)  Relationships of P

0 .

If

is normalized by its value at is equal to

0, its normalized value

Fig. 4. Error K.

" of V

versus

with different values of

and

(5) Consider a generic ring angle , the power is for 1. Its operating point is at point A in Fig. 2. In order to achieve a linear relationship between and , an output power of at should be equalized (i.e., at the point B). This mapping can be achieved by adjusting in (2), so that

equal to , the EQC will generate With the input equal to 1/2 1 . The relationship an output and is shown in Fig. 3. In order to simbetween plify the implementation, the function in Fig. 3 is approximated by the following sigmoid function. The approximated value of , denoted by , is equal to (9) where and are constants that affect the accuracy of the approximation. Fig. 4 shows the error of (9) against under different values of and is dened as

(6) Fig. 2(b) shows the required relationships between and . With the above mapping, the output power of the yback converter will be equal to the power at point C in Fig. 2(a), equivfor 1. Therefore alent to the TRIAC operating at (7) This gives the required linearization mapping of (8) Based on the constant input current characteristics of the is the same as HBSRI, the normalized dc-link voltage because . As shown in Fig. 1(b), an EQC is . designed to implement the mapping in (7) by controlling

(10) As shown in Figs. 3 and 4, the conversion between and is sensitive only at the two extremes (i.e., around 0 and 1). However, it will be shown in the measurements (Fig. 11) that this feature does not introduce adverse effects on the lux output. B. Design of the Flyback Converter Design of and in the yback converter is based on considering the dc-link ripple voltage and ensuring a DCM operation of the converter over the control range of . 1) Design of the Output Capacitor C: The value of is determined by considering the maximum ripple voltage on and in Fig. 1 can be expressed as

(11) where and is the peak input current.

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IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 20, NO. 6, NOVEMBER 2005

The instantaneous input power

is (12)

Its average value

is equal to the dc-link power. Thus

(13) The following instantaneous power-balance equation can also be derived:

(14) If and are angles, at which the rate of change of zero, it can be shown that and (15) By using (12) and (13) to solve (14)
Fig. 5. Input characteristics of the yback converter. (a) Theoretical inductor waveform. (b) Duty cycle versus .

equals

(16) Hence, the peak-to-peak ripple voltage can be approximated by at the dc-link

where and are the duty cycle and the switching period of the main switch. Moreover, the duty cycle of the diode can be shown to be (21)

if if As monotonically increases with -

(17)

Thus the average value of

can be expressed as (22)

(18) By using (16), the minimum value of , that can ensure contains ripple voltage less than throughout the operating range of is (19), shown at the bottom of the page. 2) Design of the Inductor L: Fig. 5(a) shows the theoretical inductor current waveform. Its peak value can be expressed as

If is slow varying and (22) becomes

is relatively xed at a given ,

(23) where is the required duty cycle of the switch at the given . Fig. 5(b) shows the relationships between the duty cycle and . Comparing (23) with (1) (24)

(20)

(19)

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At

0, the duty cycle is (25)

is the maximum input power. where is normalized by , it can be shown that If


Fig. 6. Equivalent model of the input circuit.

(26)
TABLE I SPECIFICATIONS AND COMPONENT VALUES OF THE PROTOTYPE

By using (3),

can be expressed as (27)

Hence, the maximum value of the duty cycle is equal to . In order to ensure that the converter is always operating in 1. Thus, based DCM, it must be assured that on (21) (28) As is required to be in linear relationships with , it can be expressed as (29) where is the maximum value of at 0, normalized by . By using (26) and (27), it can also be observed that

(30) From (23) and (28), it can be shown that

of the low-frequency input current must be owing into the yis inversely proportional to the back converter at all . Since square of the duty cycle, it is required to ensure that (33)

(31) The lower limit of is determined by the maximum current of the main switch and the duty cycle at . rating Thus (32)

Second, most of the high-frequency components of the yback input current must be mostly circulated through . Thus (34) where is the angular switching frequency. III. EXPERIMENTAL VERIFICATIONS An experimental prototype for a 40-W tubular uorescent lamp has been tested. The ac mains supply is 220 V, 50 Hz. Based on the design criteria in Section II, the specications and and the component values used are tabulated in Table I. are chosen to be 4.4 and 0.019, respectively. Figs. 79 show

C. Design of the Input Filter

and

An equivalent model of the input circuit is shown in Fig. 6. The input of the yback converter is modeled by a high-frequency current source while the output of the TRIAC is modeled by a voltage source. The lter has to achieve two objectives. First, the voltage drop across should be small and most

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Fig. 7. Experimental waveforms when = 0 . (a) AC mains voltage (Chi: 200 V/div) and i (Ch2: 500 mA/div). (Timebase: 4 ms/div). (b) v (Chi: 50 V/div). (Timebase: 4 ms/div). (c) Lamp voltage (Ch:l 100 V/div) and lamp current (Ch 2: 500 mA/div). (Timebase: 2 s/div).

Fig. 8. Experimental waveforms when a = 60 .(a) AC mains voltage (Chi: 200 V/div) and i (Ch2: 500 mA/div). (Timebase: 4 ms/div).) (b) v (Chi: 50 V/div). (Timebase: 4 ms/div). (c) Lamp voltage (Ch:l 100 V/div) and lamp current (Ch 2: 200 mA/div). (Timebase: 2 s/div.)

the experimental waveforms for 0 60 , and 120 , respecis in the same prole as the ac mains. Moreover, the tively. is 8 V at 0 , 10 V at 60 , ripple voltage on 120 , which are all at the acceptable levels. and 12 V at

Fig. 10 shows the measured lamp current crest factors versus . It can be seen that the crest factor is low at small and increases with . For less than 90 , the crest factor is less than

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Fig. 10.

Measured lamp current crest factor versus .

Fig. 11.

Measured percentage of output lux level versus .

Fig. 9. Experimental waveforms when a 120 . (a) AC mains voltage (Chi: 200 V/div) and i (Ch2: 500 mA/div). (Timebase: 4 ms/div). (b) v (Chi: 50 V/div). (Timebase: 4 ms/div). (c) Lamp voltage (Ch:l 100 V/div) and lamp current (Ch 2: 50 mA/div). (Timebase: 2 s/div.)

Fig. 12. Power factor and THD versus . (a) Power factor versus . (b) THD versus .

1.5. For 90 110 , the crest factor is less than 1.7. For larger , the crest factor will further increase. The ballast can only extract electric energy from the line when the TRIAC is

on. The dc-link capacitor is responsible for supplying energy to the lamp when the TRIAC is off. When is large, the capacitor requires supplying energy to the lamp for a longer time and the ripple voltage is then large. In order to have a wide dimming

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REFERENCES
[1] S. K. Biswas and R. P. Dhanuka, Design considerations for economical electronic ballasts, in Proc. Int. Conf. Power Electronics Drive Systems, 1995, pp. 411416. [2] International Electrotechnical Commission, Electromagnetic Compatibility(EMC), Part 3, Section 2: Limits for Harmonic Current Emissions, IEC Std. 1000-3-2, Geneva, Switzerland, Apr. 1995. [3] M. Kazimierczuk and W. Szaraniek, Electronic ballast for uorescent lamps, IEEE Trans. Power Electron., vol. 8, no. 4, pp. 386395, Oct. 1993. [4] Micro-Linear, Electronic Dimming Ballast Controller, ML Std. 4832, Apr. 1997. [5] ST Microelectronics, Ballast Driver Preheat and Dimming, CFL/TL Std. L6574, Sep. 1998. [6] D. Tadesse, F. Dawson, and S. Dewan, A comparison of power circuit topologies and control techniques for a high frequency ballast, in Proc. Industry Applications Conf., 1993, pp. 23412347. [7] J. Qian, F. Lee, and T. Yamauchi, Charge pump power-factor-correction dimming electronic ballast, IEEE Trans. Power Electron., vol. 14, no. 3, pp. 461468, May 1999. [8] G. Chae, Y. Youn, and G. Cho, High power factor correction circuit for low-cost electronic ballasts, Electron. Lett., vol. 33, no. 11, pp. 921922, May 1997. [9] C. Licitra, L. Malesani, G. Spiazzi, P. Tenti, and T. Testa, Single-ended soft-switching electronic ballast with unity power factor, IEEE Trans. Ind. Appl., vol. 29, no. 2, pp. 382388, Mar./Apr. 1993. [10] E. Deng and S. Cuk, Single switch, unity power factor, lamp ballasts, in Proc. IEEE Applied Power Electron. Conf., Mar. 1995, pp. 670676. [11] T. Wu, T. Yu, and M. Chiang, Single stage electronic ballast with dimming feature and unity power factor, IEEE Trans. Power Electron., vol. 13, no. 3, pp. 586597, May 1998. [12] E. Deng and S. Cuk, Single stage, high power factor lamp ballast, in Proc. IEEE Applied Power Electronics Conf., Feb. 1994, pp. 441449. [13] W. Ki, J. Shi, E. Yau, P. Mok, and J. Sin, Phase-controlled dimmable electronic ballast for uorescent lamps, in Proc. IEEE Power Electronic Specialty Conf., 1999, pp. 11211124. [14] J. Janczak, TRIAC dimmable integrated compact uorescent lamp, J. Illum. Eng. Soc., pp. 144151, 1998. [15] A. Calleja, J. Alonso, E. Lopez, J. Ribas, J. Martinez, and M. Rico-Secades, Analysis and experimental results of a single-stage high-power-factor electronic ballast based on yback converter, IEEE Trans. Power Electron., vol. 14, no. 6, pp. 9981006, Nov. 1999. [16] Y. Ho, H. Chung, S. Lee, and S. Hui, A comparative study on dimming control methods for electronic ballasts, IEEE Trans. Power Electron., vol. 16, no. 6, pp. 828836, Nov. 2001. [17] S. Hui, Y. Ho, and H. Chung, An electronic ballast with wide dimming range, high PF, and low EMI, IEEE Trans. Power Electron., vol. 16, no. 4, pp. 465472, Jul. 2001. [18] S. Hui and H. Chung, Dimming control of electronic ballasts with low EMI and low switching stress by varying dc converter voltage, U.S. patent led, 1998. [19] R. Bausiere, F. Labrique, and G. Seguier, Power Electronic ConvertersDC-DC Conversion. New York: Springer-Verlag, 1993. [20] C. Sullivan, J. Spira, D. Luchaco, S. Jurell, and E. Motto, Circuit and method for improved dimming of gas discharge lamps, U.S. Patent 5 041 763. [21] A. Okude, A. Ueoka, Y. Kambara, and M. Mitani, Development of an electronic dimming ballast for uorescent lamps, J. Illum. Eng. Soc., pp. 1521, 1992.

Fig. 13.

Appearance of the lamp at 10% brightness.

Fig. 14.

Efciency versus dimming percentage.

range with small ripple (and hence low crest factor), it is necessary to use a large capacitor. In addition, the unsymmetrical current ow in the TRIAC becomes more signicant at larger ring angle, due to the different quadrant of operation [19]. Hence, the dc-link voltage ripple will then be increased. Fig. 11 shows the measured percentage output lux level of the uorescent lamp with respect to with the EQC incorporated and excluded. The output lux level changes from a nonlinear relationship to a linear one with the EQC included. The controllable range is also widened, demonstrating the applicability of the technique. Fig. 12 shows the power factor and THD versus . About the practical challenges, when the lamp is suddenly removed and the lamp current becomes zero, a circuit is needed to turn the entire ballast system off. Moreover, if the position of the TRIAC is not within a dened angle, the ballast may not be possible to generate a sufciently high voltage to ignite the lamp. The ballast function should also be off. Fig. 13 shows a photo of the lamp at low power level. A practice of having an extra winding on the resonant inductor is adopted to introduce a small dc current in the lamp to eliminate striation [20] and [21]. Finally, Fig. 14 shows the efciency curves at different dimming levels. The efciency is high at full power and is reduced at the low dimming levels. It is because the energy loss becomes signicant at low dimming levels. IV. CONCLUSION In this paper, the modeling, design, and analysis of a twostage, two-wire TRIAC-controlled electronic ballast for uorescent lamp with lux level equalization is presented. The PEQS can change the original nonlinear characteristics of the dimming action into a linear one. This not only provides a regular control-to-output lux level sensitivity throughout the dimming range, but also extend the range of the controllability before the extinction of the lamp. The mathematical proofs have been veried with the performance of a prototype.

Stephen T. S. Lee (M04) was born in Hong Kong in 1976. He received the B.Eng. degree (with honors) and the Ph.D. degree in electronic engineering from the City University of Hong Kong (CityU), in 1999 and 2004, respectively. Since 2004, he has been with the Department of Design and Development, e.Energy Technology, Ltd., CityU, where he is an Engineering Manager. His research interest is the design of dimmable electronic ballast for various types of uorescent lamps and energy saving systems for various types of discharge lamps.

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Henry Shu-Hung Chung (M95SM03) received the B.Eng. and Ph.D. degrees in electrical engineering from The Hong Kong Polytechnic University, Hong Kong, in 1991 and 1994, respectively. Since 1995, he has been with the City University of Hong Kong (CityU). He is currently a Professor in the Department of Electronic Engineering and Chief Technical Ofcer of e.Energy Technology Ltd., CityU. He has authored six book chapters, and over 200 technical papers including 90 refereed journal papers in his research areas, and holds four U.S. patents. His research interests include time- and frequency-domain analysis of power electronic circuits, switched-capacitor-based converters, random-switching techniques, control methods, digital audio ampliers, soft-switching converters, photovoltaic systems, and electronic ballast design. Dr. Chung received the Grand Applied Research Excellence Award from the City University of Hong Kong in 2001. He was Associate Editor and Guest Editor of the IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMSPART I: FUNDAMENTAL THEORY AND APPLICATIONS from 1999 to 2003. He is currently Associate Editor of the IEEE TRANSACTIONS ON POWER ELECTRONICS. He was IEEE Student Branch Counselor and was Track Chair of the Technical Committee on Power Electronics Circuits and Power Systems, IEEE Circuits and Systems Society, from 1997 to 1998.

S. Y. (Ron) Hui (F00) was born in Hong Kong in 1961. He received the B.Sc degree (with honors) from the University of Birmingham, Birmingham, U.K., in 1984 and the D.I.C. and Ph.D degrees from the Imperial College of Science and Technology, University of London, London, U.K., in 1987. He was a Lecturer in power electronics at the University of Nottingham, U.K. from 1987 to 1990. In 1990, he took up a lectureship at the University of Technology, Sydney, Australia, where he became a Senior Lecturer in 1991. He joined the University of Sydney in 1993 and was promoted to Reader of Electrical Engineering in 1996. Presently, he is a Chair Professor of Electronic Engineering at the City University of Hong Kong. He has published over 150 technical papers, including over 100 refereed journal publications. Dr. Hui received the Teaching Excellence Award in 1999, the Grand Applied Research Excellence Award in 2001 from the City University of Hong Kong, the Hong Kong Award for Industry, and the Technological Achievement Award and Consumer Design Award, in 2001 and 2004, respectively. He is a Fellow of the IEE and has been an Associate Editor of the IEEE TRANSACTIONS ON POWER ELECTRONICS since 1997. He has been an At-Large member of the IEEE PELS AdCom since October 2002. He was appointed as an IEEE Distinguished Lecturer by IEEE PELS in 2004.

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