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Improved Solid State Valves

1000414

Improved Solid State Valves

1000414 Technical Progress, November 2000

EPRI Project Manager A. Edris

EPRI 3412 Hillview Avenue, Palo Alto, California 94304 PO Box 10412, Palo Alto, California 94303 USA 800.313.3774 650.855.2121 askepri@epri.com www.epri.com

DISCLAIMER OF WARRANTIES AND LIMITATION OF LIABILITIES


THIS DOCUMENT WAS PREPARED BY THE ORGANIZATION(S) NAMED BELOW AS AN ACCOUNT OF WORK SPONSORED OR COSPONSORED BY THE ELECTRIC POWER RESEARCH INSTITUTE, INC. (EPRI). NEITHER EPRI, ANY MEMBER OF EPRI, ANY COSPONSOR, THE ORGANIZATION(S) BELOW, NOR ANY PERSON ACTING ON BEHALF OF ANY OF THEM: (A) MAKES ANY WARRANTY OR REPRESENTATION WHATSOEVER, EXPRESS OR IMPLIED, (I) WITH RESPECT TO THE USE OF ANY INFORMATION, APPARATUS, METHOD, PROCESS, OR SIMILAR ITEM DISCLOSED IN THIS DOCUMENT, INCLUDING MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, OR (II) THAT SUCH USE DOES NOT INFRINGE ON OR INTERFERE WITH PRIVATELY OWNED RIGHTS, INCLUDING ANY PARTY'S INTELLECTUAL PROPERTY, OR (III) THAT THIS DOCUMENT IS SUITABLE TO ANY PARTICULAR USER'S CIRCUMSTANCE; OR (B) ASSUMES RESPONSIBILITY FOR ANY DAMAGES OR OTHER LIABILITY WHATSOEVER (INCLUDING ANY CONSEQUENTIAL DAMAGES, EVEN IF EPRI OR ANY EPRI REPRESENTATIVE HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES) RESULTING FROM YOUR SELECTION OR USE OF THIS DOCUMENT OR ANY INFORMATION, APPARATUS, METHOD, PROCESS, OR SIMILAR ITEM DISCLOSED IN THIS DOCUMENT. ORGANIZATION(S) THAT PREPARED THIS DOCUMENT Siemens Transmission and Distribution, Facts and Power Quailty Division (FPQD)

This is an EPRI Level 2 report. A Level 2 report is intended as an informal report of continuing research, a meeting, or a topical study. It is not a final EPRI technical report.

ORDERING INFORMATION
Requests for copies of this report should be directed to the EPRI Distribution Center, 207 Coggins Drive, P.O. Box 23205, Pleasant Hill, CA 94523, (800) 313-3774. Electric Power Research Institute and EPRI are registered service marks of the Electric Power Research Institute, Inc. EPRI. ELECTRIFY THE WORLD is a service mark of the Electric Power Research Institute, Inc. Copyright 2000 Electric Power Research Institute, Inc. All rights reserved.

CITATIONS
This document was prepared by Siemens Transmission and Distribution, Facts and Power Quailty Division (FPQD) Authors C.D. Schauder E.J. Stacey G.S. Bettencourt M.R. Lund Project Manager L.J.Kovalsky This document describes research sponsored by EPRI. The publication is a corporate document that should be cited in the literature in the following manner: Improved Solid State Valves, EPRI, Palo Alto, CA: 2000. 1000414.

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REPORT SUMARY
Background This report describes the results of a program for the development, design, construction, and evaluation of an advanced, self-commutated, solid-state valve comprising series connected semiconductors for high power switching power converters. The report describes in detail the digital simulations, design, successful prototype testing, and successful field testing of the advanced three-level pole structure. Objectives To develop an advanced high power inverter valve on a pole structure that will improve performance and reduce overall cost for FACTS and HVDC applications. Approach The valves utilize the most advanced power Gate Turn Off Thyristors (GTOs) in novel circuit configurations and a physical structure which will allow the full utilization of the GTOs fast switching capability without appreciable reduction in their voltage and current ratings. The valves are arranged on a multi-level pole structure and is the first one in the world able to provide three-level (positive, negative, and zero) output at substantial power ratings suitable for utility transmission line applications. This is a vital attribute to achieve controllable output voltage and high quality output waveforms without the use of a complex magnetic structures. Results Digital models and simulations were used to determine a feasible circuit design for the multilevel pole. A high power inverter pole prototype was built and was subjected to an extensive series of tests to verify devices stresses, thermal performance, and waveform quality. The pole was then successfully tested in a utility application a part of a 160MVA inverter system for a Unified Power Flow Controller (UPFC). EPRI Perspective The multi-level inverter pole approach is the new standard and will play in increasing role in FACTS and HVDC applications. Keywords Gate Turn-off Thyristor (GTO), Valves, Inverters, Poles, FACTS, HVDC

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ABSTRACT
The new generation FACTS, HVDC, and other power controller and conditioning systems (such as the Static Condenser, Static Synchronous Compensator, Unified Power Flow Controller, selfcommutated HVDC converters, etc.) will have a capability to generate reactive power without ac energy storage components (capacitors or reactors), to provide hitherto unattainable operating characteristics, performance, and flexibility, making extremely high degree utilization of power system assets possible. However, these new generation of power controllers and conditioners cannot be realized without fast, efficient, high power, self-commutated valves which can be configured into switching power converters capable of synthesizing rapidly controllable, closely sinusoidal waveforms at low operating losses and competitive capital cost. This report describes the results of a program for the development, design, construction, and evaluation of an advanced, self-commutated, solid-state valve comprising series connected semiconductors for high power switching power converters. The valves utilize the most advanced power Gate Turn Off Thyristors (GTOs) in novel circuit configurations and a physical structure which will allow the full utilization of the GTOs fast switching capability without appreciable reduction in their voltage and current ratings. The valves are arranged on a multilevel pole structure and is the first one in the world able to provide three-level (positive, negative, and zero) output at substantial power power ratings suitable for utility transmission line applications. This is a vital attribute to achieve controllable output voltage and high quality output waveforms without the use of a complex magnetic structures. The report describes in detail the digital simulations, design, successful prototype testing, and successful field testing of the advanced three-level pole structure. The completion of the advanced valve project is another important milestone in the progress of FACTS technology. The successful new high-voltage inverter design, based on the use of three-level poles, has demonstrated clearly that GTO-based voltage-sourced inverters are practical and effective, and can be applied at very high power levels in wide variety of FACTS applications.

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ACKNOWLEDGMENTS
The authors would like to recognize J. Shirk, M. Weaver, K. Sen, Y. Lin, R. Pape, D. Carrera, K. Hughes, D. Pauli, J. Sullivan, M. Letendre and S. Berkowitz who made valuable contributions to this work.

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CONTENTS
1 INTRODUCTION ..................................................................................1-1 2 DIGITAL MODELING ...........................................................................2-1 3 ADVANCED POLE DESIGN ................................................................3-1 4 ADVANCED POLE TESTING ..............................................................4-1 5 ADVANCED POLE INSTALLATION....................................................5-1 6 TEST RESULTS FROM UTILITY APPLICATION ................................6-1 7 CONCLUSIONS ...................................................................................7-1 A IDEALIZED POLE WAVEFORMS ...................................................... A-1 B ADVANCED POLE BIL TEST REPORT............................................. B-1 C PROTOTYPE TEST DATA ................................................................. C-1 D SAMPLE PRODUCTION POLE TEST REPORT ................................ D-1

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1
INTRODUCTION
This report describes the results of a program for the development, design, construction, and evaluation of an advanced, self-commutated, solid-state valve comprising series connected semiconductors for high power switching power converters. The valves utilized the most advanced presently available and newly emerging power semiconductors in novel circuit configurations and physical structures which will allow the full utilization of their fast switching capability without appreciable reduction in their voltage and current ratings. The solid-state valves developed will provide the basic building blocks for a new generation of advanced high power switching converters which will make the realization of new, sophisticated, and highly efficient power flow controllers, compensators, and converters for Flexible AC Transmission System (FACTS), High Voltage DC (HVDC) Transmission and Intertie Systems, Superconducting Magnet and other Energy Storage Systems, ultra-fast circuit breakers and fault current limiter, as well as for high power, variable speed motor drives, and other industrial power converters and conditioners. The new generation FACTS, HVDC, and other power controller and conditioning systems (such as the Static Synchronous Compensator, Unified Power Flow Controller, self-commutated HVDC converters, etc.) will have a capability to generate reactive power without energy storage components (capacitors or reactors), to provide hitherto unattainable operating characteristics, performance, and flexibility, making extremely high degree utilization of power system assets possible. However, these new generation of power controllers and conditioners cannot be realized without fast, efficient, high power, self-commutated valves which can be configured into switching power converters capable of synthesizing rapidly controllable, closely sinusoidal waveforms at low operating losses and competitive capital cost. The program utilized new generation Gate Turn-off (GTO) thyristor devices as primary switching elements to construct high power valves consistent with the program objectives. These high power valves will be the first ones in the world able to provide three-level (positive, negative, and zero) output, a vital attribute to achieve controllable output voltage and high quality output waveform without the use of a complex magnetic structure. The GTO-based valves feature a novel structural design that dramatically minimizes leakage inductances to fully utilize the given VA ratings of the power semiconductors, efficient thermal management to keep the operating junction temperature low, and a highly sophisticated valve and gating control sub-system with comprehensive operation monitoring and protection to ensure the integrity and proper 1-1

Introduction

operation under all conceivable conditions. The valves were designed to be compatible with appropriate converter structures and be directly interfaced with a digital (processor-based) the central control via optical links to form an operating system. An important objective of the program was to combine four GTO valves into an operational power converter for testing and evaluating their capabilities under actual operating conditions. This program has confirmed the theoretical predictions of the valve concepts and design objectives and also provided a benchmark for state-of-the-art and future valve developments. The three-level inverter design is considerably different from that used in previous high power utility installations. The basic circuit for a three-level pole, together with a typical output voltage waveform, is illustrated in Figure 1-1. In this diagram single GTOs and diodes are used symbolically to represent high power valves that typically comprise several devices connected in series. The three-level pole offers the additional flexibility of a step in the output voltage that can be controlled in duration, either to vary the fundamental output voltage, or to assist in waveform construction. In addition, because the total dc-bus voltage can be double the nominal rating of each of the four GTO valves, the output voltage (and hence the output power) from a single pole is twice that which is obtained from a two-level pole using similar valves. The three-level pole thus permits a higher voltage inverter design with fewer poles and a less complicated, lower current bus for connection to the output transformers.

Output Voltage Waveform v 0

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Figure 1-1 Simplified Representation of a Three-Level Pole

The development of the three-level pole was a major undertaking and involved many challenges. Figure 1.2 shows the complex roadmap laid out at the beginning of the program to develop the three-level pole. This report discusses the various elements of this roadmap as follows:

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Introduction

Figure 1-2 Three-Level Pole Development Roadmap

Section 2 reviews the digital simulations performed to evaluate the voltage and current stress on the advanced 3-level pole during switching operations. Section 3 discusses the electrical, mechanical and physical design considerations to develop the first prototype pole. A utility end application power circuit is also discussed. Section 4 covers the prototype and production testing of the advanced pole design. Section 5 covers the end-application site installation of the advanced pole. Section 6 covers the test results and conclusions from field experience with the advanced pole. Section 7 covers the conclusions and plans for future work.

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DIGITAL MODELING
Development of EMTP Models
Multi-level poles using GTOs have been proposed for use in high voltage inverters to achieve higher power levels and harmonic reduction while eliminating bulky and expensive magnetics. There are significant challenges to address in the design of multi-level poles. One challenge is to limit the voltage overshoot on the devices. The present literature does not sufficiently address this issue, with most authors simply looking at the ideal case where device voltage is clamped by the dc bus capacitors through the midpoint diodes. However, in a practical design, the GTOs require di/dt limiting inductors and dv/dt limiting snubbers. The multi-level pole will also have larger stray loop inductances. With these components considered, large voltage overshoots will occur despite the dc bus capacitors and midpoint diodes. This requires significant derating of the devices or a special clamping arrangement. This section describes the development of an EMTP model to study the switching transitions of a proposed 3 level pole with clamp circuit. To obtain results that are practical, the simulations include stray inductances that have been estimated from the proposed physical layout. The topologies of the circuit during switching are presented to better understand which parameters are important to the design of a 3 level pole and data is extracted from simulation waveforms to assess the effectiveness of the proposed physical layout and clamping scheme. Switching transitions in a 3 level pole with a clamp circuit were simulated using EMTP. This was done to characterize circuit dynamics during switching and evaluate the proposed clamp circuit. Data on peak device stresses for worst case and normal operating conditions were extracted. These results provide practical insight that will aid in the design of a 3 level pole.

Description of the EMTP Model


The switching transitions for a 3 level pole with clamp circuit as shown Figure 2-1 were simulated using EMTP. Simulation files were created using ATPDRAW, a graphical 2-1

Digital Modeling

G DP CS RE DM DC CC RC L

GTO Anti-parallel Diode Snubber Capacitor Voltage Equalizing Resistor Midpoint Diode Clamp Diode Clamp Capacitor Clamp resistor di/dt Inductor

Figure 2-1 3-Level Pole with Clamp

preprocessor to the ATP version of EMTP. The basic 3 level pole ATPDRAW circuit of Figure 2-2 shows the locations of stray inductances added to the circuit. Other elements were added to increase numerical stability without significantly affecting simulation results. Circuit parameters were chosen for a base case and then simulations were run. A large number of output waveforms were generated to help clarify circuit operation during the switching transitions. From these waveforms, diagrams for each switching transition were drawn to show the various topologies during the transition. Finally data was extracted showing peak values of concern in designing a 3 level pole with this configuration.

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500 nH

100 nH

200 nH 700 nH

Figure 2-2 Basic 3-Level Pole Circuit in ATPDRAW

200 nH 500 nH 700 nH 500 nH 100 nH 100 nH 500 nH 700 nH 200 nH 700 nH 200 nH 500 nH

C:\ATP\CASES\3LVLP\DOC\BASIC3

100 nH 100 nH 100 nH

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Base Case Simulation Parameters


Simulation parameters were chosen to correspond to previous simulations of an actual 2 level pole allowing easy comparison of results with actual hardware. Bus voltage for the base case simulation was chosen at 8 kV from the midpoint to each outer rail, resulting in a total bus voltage of 16 kV. For the base case simulation, output current was chosen at a worst-case 4000 A. Component values shown in Table 2-1 were selected such that each valve in the simulation corresponds to a set of five series GTO modules like those used in previous equipment. Values for the upper and lower clamp in the 3 level pole correspond to the value of clamp components used in previous 2level designs. The value of the di/dt inductors is double that used in previous 2-level designs to obtain equivalent di/dt limiting with twice the overall bus voltage.

Stray Inductance
For an accurate simulation, it was necessary to predict as closely as possible the stray inductances in the circuit. This was of particular concern with the turn-off of an inner GTO in the 3 level pole, where preliminary simulations showed that voltage overshoot on the inner device was highly dependent on stray inductance of the pole bus. Thus an effort was made to relate the values for stray inductance to a proposed layout of the 3 level pole and examine how changing physical dimensions of the layout would affect the stray inductance and how this in turn would affect the performance of the 3 level pole.
Table 2-1 Values for Components in EMTP Simulation Component Value

Snubber Capacitor Snubber Resistor Snubber Damping Capacitor Snubber Damping Resistor Voltage Equalizing Resistor Clamp Capacitor Clamp Damper Resistor di/dt Inductor

1.2 F 25 0.044 F 7.5 36.5 k 10 F 0.5 15.2 H

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Digital Modeling

Pole Bus Inductance


Stray inductance of the pole bus was estimated using approximate physical dimensions and a spreadsheet implementation of Equation (1) of Inductance Calculations by F.W. Grover. A proposed bus structure is proposed where each half of the bus is roughly equivalent in length to an existing 2 level pole (10). For calculating stray bus inductance this structure was approximated as three parallel bars 0.25 thick, 10 long and 9 high, with a spacing of 3 from the midpoint bus to each of the outer busses (6 between the outer two busses). The stray inductance associated with the two outer busses (ignoring the midpoint bus which would slightly reduce the inductance) was calculated based on a 6 gap and yielded 1.457 H. The stray inductance associated with the inner bus together with one of the outer busses was based on a 3 gap and yielded 0.922 H. These stray inductances were represented in the simulated circuit by lumped inductances in series with each of the GTO modules and midpoint diodes as shown in the ATPDRAW circuit of Figure 2-2. The lumped inductance in series with each of the GTOs was set at 700 nH, approximately half of the total stray inductance associated with the outer busses. The lumped inductance in series with the midpoint diodes was figured at about 200 nH, approximately the stray inductance associated with the inner and outer bus minus the 700 nH in series with the GTO module. The stray inductance associated with the bus can be reduced by increasing the bus height or decreasing the gap between the busses. The table below shows how changing the bus spacing and height affects the inductance associated with the outer busses. The base case described in the preceding paragraph is shaded.
Table 2-2 Stray Inductance Associated with Pole Busses Bus Height (inches) Spacing of Outer Busses (inches)

2 0.941 H 0.686 H 0.540 H

4 1.475 H 1.125 H 0.909 H

6 1.855 H 1.457 H 1.201 H

8 2.143 H 1.720 H 1.440 H

6 9 12

The snubber loop stray inductance of the individual GTO modules had been previously measured at approximately 85 nH. The equivalent simulated snubber loop inductance (representing five series GTO modules) was set at 500 nH. The stray inductance of the RC damper on the snubber diode was not considered significant in the simulation, and simply set at 100 nH. The stray inductance of the clamp capacitors was set at 200 nH, based on specifications for the internal inductance of the capacitor. Finally, the stray inductance between the dc 2-5

Digital Modeling

bus capacitors (modeled by dc sources) and the pole was roughly estimated based on inductance measurements of the previous dc bus designs. To represent this in the simulation, 500 nH inductors were placed in series with each dc source.

GTO and Diode Models


GTOs were modeled with an ideal switch in series with an ideal diode to block reverse current. Controllable current sources were added so that during turn-off, the GTO appears to be a piecewise linear current source with the characteristics shown in Figure 2-3. The user defined parameters for the GTO model as used in the base case simulation are given in Table 2-3.
Table 2-3 Parameters for GTO Model Parameter Value

Fall Time Tail Time Tail Current (% turn-off current)

500 ns 11 s 15%

Diodes were modeled as ideal diodes in series with a 1 m slope resistance. To avoid disconnected subnetworks in EMTP, a 100 k resistance was added in parallel with each diode and GTO. For numerical stability, an RC numerical snubber was also added in parallel with each diode and GTO. With a simulation stepsize of 10 ns, the RC time constant of the numerical snubbers was set to 30 ns (100 and 0.3 nF) so that unwanted numerical oscillations were damped while circuit dynamics of interest were unaffected.

Switching Transitions
Figure 2-4 shows the six stable states of the 3 level pole: high, mid, and low output for both positive and negative current. Under normal operation, the 3 level pole operation involves four switching transitions: mid-to-high, high-to-mid, mid-to-low, and low-tomid. Modeling each of these transitions for just the positive current case is sufficient to evaluate the operation of the 3 level pole, since each of the transitions for negative current can be shown to be functionally equivalent to a positive current case (for example, the high-to-mid transition for negative current is equivalent to the low-to-mid transition for positive current).

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GTO Tail Current

Figure 2-3 Turn-off Current for GTO Model

Figure 2-4 Stable States for the 3-Level Pole

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Each of the four base case transitions were modeled as a separate EMTP data case. Initial values for inductor currents and capacitor voltages were set, then a 200 s settling time was allowed before initiating the switching transition. The simulation then continued for 300 s to allow the dynamics initiated by the switching transition to settle.

Results
To completely describe circuit operation during the switching transitions, voltage and current waveforms were recorded for all GTOs, diodes, snubber capacitors, clamp capacitors and di/dt inductors. All waveforms for the base case simulation (at 2 x 8000 V, 4000 A) are included in Appendix A. These waveforms cover a time period from 10 s before initiating the transition until 50 s after, the period during which most of the significant dynamics occurred. The results of the base case simulations for each of the four switching cases are presented with a description and diagram of the major topology changes that occur in the circuit during the transition. Occasionally small voltages and currents that appeared in the simulation were ignored if they were not thought to contribute to the major function of the circuit. Note that all labels used in the topology descriptions and waveforms are given in Figure 2-1. Following the description of topology changes are several tables that show peak device stresses of interest in the design of a 3 level pole. These values are given for the base case (4000 A load) and followed by the same data under more normal operating conditions (2000 A load).

Mid-to-High Transition
The major circuit topologies for the 3 level pole as it transitions from the mid to high state are shown in Figure 2-5 with numbered descriptions of each topology given below. The associated ATPDRAW case is shown in Figure 2-6. Simulation waveforms follow in Figures 2-7 through 2-12. 1. In the mid state all load current is carried by DM1 and G2. The transition to the high state is initiated by turning on G1 and turning off G3 (note that current through G3 is zero at turn-off). 2. Current builds linearly in L1-G1 at approximately 500 A/s, with a corresponding linear decrease in current through DM1. Eventually current through DM1 goes to zero and DM1 turns off. At this point L1-G1-G2 support the full 4000 A load current. CS1 is dumping through G1.

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Figure 2-5 Topologies for Mid-to-High Transition

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C:\ATP\CASES\3LVLP\DOC\M2H.PPT

Figure 2-6 ATPDRAW Circuit for Mid-to-High Case

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Figure 2-7 3 Level Pole, Mid-to-High, 8000 V, 4000 A - GTO Waveforms

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Figure 2-8 3 Level Pole, Mid-to-High, 8000 V, 4000 A - Parallel Diode Waveforms

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Figure 2-9 3 Level Pole, Mid-to-High, 8000 V, 4000 A - GTO Waveforms - Clamp Diode and Midpoint Diode Waveforms

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Figure 2-10 3 Level Pole, Mid-to-High, 8000 V, 4000 A - GTO Waveforms - Snubber Diode Waveforms

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Figure 2-11 3 Level Pole, Mid-to-High, 8000 V, 4000 A - GTO Waveforms - Snubber Capacitor Waveforms

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Figure 2-12 3 Level Pole, Mid-to-High, 8000 V, 4000 A - GTO Waveforms - Clamp Capacitor and di/dt Inductor Waveforms

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1. DS3 and DM2 turn on, and current continues to build through L1-G1-G2, with current in excess of the load going to charge CS3. Note that voltage on CS3 increases from zero in a 1-cos fashion as expected from the interaction of L1 and CS3. When this voltage reaches 8 kV, the upper clamp diode DC1 turns on. 2. With DC1 on, current through DS3-CS3-DM2 quickly goes to zero as current in excess of the load is diverted into the upper clamp capacitor CC1. However, during this short time, CS3 has been charged from 8 kV to approximately 10 kV. 3. Clamp current is damped by RC1 and eventually clamp diode DC1 turns off. With excess voltage on CS3 the sum of the voltages on CS3 and CS4 exceeds 16 kV. Thus CS3 and CS4 discharge (in series) through RS3 and RS4, until the sum of their voltages is 16 kV. However, this results in unequal voltage sharing for G3 and G4, with G3 supporting approximately 9 kV, while G4 supports only about 7 kV. Due to RE3 and RE4, these voltages would eventually equalize, but this happens on a much larger time scale since the RC time constant of the equalizing resistor with the snubber capacitor is 43.8 ms. 4. In the high state the load current is supported by G1 and G2.

High-to-Mid Transition
The major circuit topologies for the 3 level pole as it transitions from the high state back to the mid state are shown in Figure 2.13, with numbered descriptions of each topology given below. The associated ATPDRAW circuit is shown in Figure 2-14. Simulation waveforms follow in Figures 2-15 through 2-20. 1. In the high state the load current is supported by G1 and G2. The transition to the mid state is initiated by turning off G1 and turning on G3. Note G1 is turned off while supporting full load current. 2. With G1 off, load current is diverted through DS1 to charge CS1. CS3 dumps through G3. Current starts to build in G3-DM2. Then when voltage on CS1 reaches 8 kV, DC1 and DM1 turn on. 3. With DC1 on, the upper clamp capacitor CC1 acts to limit the voltage overshoot on G1, with current through DS1 quickly falling to zero. 4. RC1 damps the clamp current and eventually DC1 turns off. In the mid state the load current is supported by DM1 and G2.

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Figure 2-13 Topologies for High-to-Mid Transition

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Figure 2-14 ATPDRAW Circuit for High-to-Mid Case

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Figure 2-15 3 Level Pole, High-to-Mid, 8000 V, 4000 A - GTO Waveforms

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Figure 2-16 3 Level Pole, High-to-Mid, 8000 V, 4000 A - Parallel Diode Waveforms

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Figure 2-17 3 Level Pole, High-to-Mid, 8000 V, 4000 A - Clamp Diode and Midpoint Diode Waveforms

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Figure 2-18 3 Level Pole, High-to-Mid, 8000 V, 4000 A - Snubber Diode Waveforms

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Figure 2-19 3 Level Pole, High-to-Mid, 8000 V, 4000 A - Snubber Capacitor Waveforms

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Figure 2-20 3 Level Pole, High-to-Mid, 8000 V, 4000 A - Clamp Capacitor and di/dt Inductor Waveforms

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Mid-to-Low Transition
The major circuit topologies for the 3 level pole as it transitions from the mid to low state are shown in Figure 2-21, with numbered descriptions of each topology given below. The associated ATPDRAW circuit is shown in Figure 2-22. Simulation waveforms follow in Figures 2-23 through 2-28. 1. In the mid state the load current is supported by DM1 and G2. The transition to the low state is initiated by turning off G2 and turning on G4. Note G2 is turned off while supporting full load current. 2. Load current is diverted through DS2, charging CS2. CS4 dumps through G4. Current builds through G3-G4-L2. This happens until voltage on CS2 reaches 8 kV, at which point DC2 turns on. 3. With the lower clamp in play, current through DM1-DS2 starts toward zero. Current through G3-G4 goes to zero even more quickly. 4. Current through DM1-DS2 continues to decrease and DP4-DP3 start to pick up the load current. Current through DM1-DS2 reaches zero and these devices turn off, leaving CS2 charged to approximately 12 kV. 5. Load current is now supported by DP4-DP3. The clamp current is damped by RC2. With excess voltage on CS2, the sum of the voltages on CS1 and CS2 exceed 16 kV. So CS1 and CS2 discharge (in series) through RS1 and RS2, until the sum of their voltages is 16 kV. This results in unequal voltage sharing for G1 and G2, with G1 supporting less than 7 kV and G2 supporting over 9 kV. This voltage will eventually equalize due to RE1 and RE2, but on a much larger time scale. 6. In the low state the load current is supported by DP4 and DP3.

Low-to-Mid Transition
The major circuit topologies for the 3 level pole as it transitions from the low state back to the mid state are shown in Figure 2-29, with numbered descriptions of each topology given below. The associated ATPDRAW circuit is shown in Figure 2-30. Simulation waveforms follow in Figures 2-31 through 2-36. 1. In the low state, the load current is supported by DP3 and DP4. The transition to the mid state is initiated by turning on G2 and turning off G4 (note that current through G4 is zero at the time of turn-off).

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Figure 2-21 Topologies for Mid-to-Low Transition

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Figure 2-22 ATPDRAW Circuit for Mid-to-Low Case

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Figure 2-23 3 Level Pole, Mid-to-Low, 8000 V, 4000 A - GTO Waveforms

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Figure 2-24 3 Level Pole, Mid-to-Low, 8000 V, 4000 A - Parallel Diode Waveforms

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Figure 2-25 3 Level Pole, Mid-to-Low, 8000 V, 4000 A - Clamp Diode and Midpoint Diode Waveforms

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Figure 2-26 3 Level Pole, Mid-to-Low, 8000 V, 4000 A - Snubber Diode Waveforms

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Figure 2-27 3 Level Pole, Mid-to-Low, 8000 V, 4000 A - Snubber Capacitor Waveforms

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Figure 2-28 3 Level Pole, Mid-to-Low, 8000 V, 4000 A - Clamp Capacitor and di/dt Inductor Waveforms

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Figure 2-29 Topologies for Low-to-Mid Transition

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Figure 2-30 ATPDRAW Circuit for Low-to-Mid Case

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Figure 2-31 3 Level Pole, Low-to-Mid, 8000 V, 4000 A - GTO Waveforms

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Figure 2-32 3 Level Pole, Low-to-Mid, 8000 V, 4000 A - Parallel Diode Waveforms

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Figure 2-33 3 Level Pole, Low-to-Mid, 8000 V, 4000 A - Clamp Diode and Midpoint Diode Waveforms

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Figure 2-34 3 Level Pole, Low-to-Mid, 8000 V, 4000 A - Snubber Diode Waveforms

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Figure 2-35 3 Level Pole, Low-to-Mid, 8000 V, 4000 A - Snubber Capacitor Waveforms

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Figure 2-36 3 Level Pole, Low-to-Mid, 8000 V, 4000 A - Clamp Capacitor and di/dt Inductor Waveforms

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Digital Modeling

1. Current decreases linearly in L2-DP4-DP3 at approximately 500 A/s, while building linearly at the same rate through DM1-G2. CS2 dumps through G2. When current in L2-DP4-DP3 reaches zero, DP3 and DP4 turn off. At this point DM1-G2 support full load current. 2. Current builds through G3 and DS4, charging CS4. When voltage on CS4 reaches 8 kV, DC2 and DM2 both turn on. 3. Current through DS4 is quickly driven to zero, but during this time CS4 has been charged up to almost 10 kV. 4. Now RC2 damps the current in the clamp as the clamp voltage returns to 8 kV. There is also a circulating current through DM1-G2-G3-DM2 due to the stray inductance in the loop. It starts at well above 1000 A and dies off due to losses in the devices. However, with the voltage drops of the devices (not modeled in the simulation) this current will die much more quickly than the simulation shows. 5. Finally, in the mid state, DM1 and G2 support the full load current.

Peak Device Stresses


To target certain areas of concern in the design of a 3 level pole, data on peak device stress was extracted and tabulated. The base case simulation with bus voltage of 8000 V from the midpoint to each outer bus and current of 4000 A is a worst-case simulation. For these parameters Table 2-4 gives the di/dt at turn-on and the peak voltage at turnoff for the GTOs. This peak voltage also applies to the antiparallel diodes. Peak reverse voltage for the midpoint and clamp diodes is given in Table 2-5. The shaded areas in the tables show that the highest stress on the GTOs, antiparallel diodes, and midpoint diodes occurs during the mid-to-low (positive current) transition, with GTO 2 and its antiparallel diode experiencing a peak voltage of 10.69 kV (33% overshoot) and the lower midpoint diode DM2 experiencing a reverse voltage peak of 9.86 kV.
Table 2-4 Peak Stress on GTOs - 2 x 8000 V, 4000 A (Worst Case Operation) Turn-on Device Transition di/dt Transition Turn-off Peak Voltage

GTO 1 GTO 2 GTO 3 GTO 4

Mid-to-High Low-to-Mid High-to-Mid Mid-to-Low

507 A/s 495 A/s ---

High-to-Mid Mid-to-Low Mid-to-High Low-to-Mid

9.86 kV 10.69 kV 9.48 kV 8.88 kV

2-43

Digital Modeling

Table 2-5 Peak Stress on Clamp and Midpoint Diodes - 2 x 8000 V, 4000 A (Normal Operation) Peak Reverse

Device DC1 DC2 DM1 DM2

Transition Mid-to-High Low-to-Mid Mid-to-High Mid-to-Low

Voltage 8.0 kV 8.0 kV 8.86 kV 9.86 kV

The same data for peak device stress under more normal operating conditions of 2000 A are given in Table 2-6 and Table 2-7.
Table 2-6 Peak Stress on GTOs - 2 x 8000 V, 2000 A (Normal Operation) Turn-on Device Transition di/dt Transition Turn-off Peak Voltage

GTO 1 GTO 2 GTO 3 GTO 4

Mid-to-High Low-to-Mid High-to-Mid Mid-to-Low

473 A/s 474 A/s ---

High-to-Mid Mid-to-Low Mid-to-High Low-to-Mid

9.24 kV 9.89 kV 9.48 kV 8.88 kV

Table 2-7 Peak Stress on Clamp and Midpoint Diodes - 2 x 8000 V, 2000 A (Normal Operation) Peak Reverse

Device DC1 DC2 DM1 DM2

Transition Mid-to-High Low-to-Mid Mid-to-High Mid-to-Low

Voltage 8.0 kV 8.0 kV 8.86 kV 9.24 kV

2-44

Digital Modeling

Note that device stresses are lower for the 2000 A case as expected. Peak device stresses still occur during the mid-to-low transition, with a peak voltage on GTO 2 of 9.89 kV (24% overshoot) and peak reverse voltage on the lower midpoint diode DM2 of 9.24 With more realistic values for stray bus inductance, the voltage overshoot increases, particularly for the inner devices, showing the importance of minimizing stray inductance in the physical layout of the bus.

Table 2-8 Voltage Overshoot with Bus Inductance - 2 x 8000 V, 4000 A. Voltage developed across inner Voltage on

device (G2) during turn-off Stray Bus Inductance 2 x 100 nH per bus 2 x 400 nH per bus 2 x 700 nH per bus Total Voltage 10.69 kV 12.30 kV 13.60 kV % over 8 kV 34% 54% 70%

G2 300 s after turn-off 9.75 kV 10.4 kV 10.9 kV

2 x 8000 V, 2000 A Voltage developed across inner Voltage on

device (G2) during turn-off Stray Bus Inductance 2 x 100 nH per bus 2 x 400 nH per bus 2 x 700 nH per bus Total Voltage 9.89 kV 10.93 kV 11.78 kV % over 8 kV 24% 37% 47%

G2 300 s after turn-off 9.25 kV 9.74 kV 10.1 kV

Voltage overshoot and unequal voltage sharing that occur with the turn-off of an inner device are also dependent on the snubber loop inductance, but to a lesser degree than the dependence on bus inductance.

2-45

Digital Modeling 2 x 8000 V, 4000 A, bus inductance = 2 x 700 nH Stray snubber loop Voltage developed across inner Voltage on

inductance (for equiv. 5 series modules) 200 nH 500 nH 800 nH

device (G2) during turn-off Total Voltage 13.93 kV 13.60 kV 13.30 kV % over 8 kV 74% 70% 66%

G2 300 s after turn-off 10.77 kV 10.90 kV 10.06 kV

With 2 x 700 nH of stray bus inductance, the voltage overshoot that occurs with the turn-off of an inner device is a major limitation on device utilization. The clamp capacitance was increased from 10 F to 100 F, resulting in the overshoot voltage decreasing only slightly from 13.60 kV (70% over 8 kV) to 13.52 kV (69% over 8 kV).

Conclusions from EMTP Studies


The EMTP simulations indicate that the clamp design chosen for the 3 level pole is effective in limiting the voltage overshoot on the GTOs and antiparallel devices. The clamping action is obvious for the outer GTOs (G1 and G4). Less obvious is the inner GTOs (G2 and G3), where the upper inner GTO (G2) is protected by the lower clamp (DC2) and the lower inner device (G3) is protected by the upper clamp (DC1). However, the inner devices are not as well protected as the outer devices, with the maximum voltage overshoot occurring with the turn-off of an inner device (mid-to-low transition for positive current). The simulations also shows that at the end of the positive current mid-to-low transition, G1 and G2 share voltage unequally. With stray inductance in the snubber loop, current into snubber capacitor CS2 cannot be interrupted instantaneously, thus CS2 is charged beyond 8 kV and when DS2 turns off, CS2 is forced to discharge in series with CS1, resulting in unequal voltage sharing for G1 and G2. A similar situation exists for G3 and G4 and the positive current mid-to-high transition. As expected, device stresses are lower for the 2000 A case with a maximum peak GTO voltage overshoot of 24%, as compared to the base case of 4000 A with a maximum peak GTO voltage overshoot of 33%.

2-46

3
ADVANCED POLE DESIGN
Design Objectives
The design objectives for the advanced pole design were to provide the utility end user with the maximum convenience in the following:

Ease of installation - Design the equipment such that it can be delivered to site in pre-assembled, pre-tested major subassemblies that require minimal assembly work at site. Convenient and practical packaging - Design the equipment so that it provides for easy access and visibility of all subassemblies so that the equipment is easily inspected and repairs are easily implemented. Ease of maintenance - Design the equipment so that the inverter assemblies are modular and can be removed in a short amount of time. The boundaries of what defines a module are selected so that the number of connections that need to be removed to replace modules are minimized. Reliability - Design the inverter equipment with appropriate levels of redundancy to maximize equipment availability.

The inverter pole assemblies are also designed to reduce overall costs to test and manufacture the equipment without affecting electrical or mechanical performance. The inverter pole design that Westinghouse has selected is described in the following sections that discuss how the design criteria will be met.

Advanced Three-level Pole Design


The design of the three-level pole presented a significant technical challenge because of the high dc voltage and the relatively large number of high power circuit components that have to be accommodated. Both of these factors tend to increase the physical size of the pole, but at the same time it is essential to keep the stray inductance of the pole circuit low to avoid transient over-voltage during commutation of current from one path to another. 3-1

Advanced Pole Design

The final design shown in Figure 3.1 is a self-contained modular pole that has proved to be highly effective in all respects. Each 4500 V, 4000 A GTO and its associated antiparallel diode, snubber components, and heatsinks are mounted in a sub-assembly termed a "GTO module". Several of these GTO modules are connected in series to constitute a single valve, and four such valves are mounted symmetrically on a horizontal beam structure to make a pole. Eight GTO modules are used for each of the two valves connecting to the dc bus, and nine modules for each of the two remaining valves. These numbers include a redundant module in each valve, so that the equipment can continue to operate safely under all conditions with one failed module in every valve. The numbers were chosen on the basis of predicted peak voltage excursion, as well as consideration of reliability related to sustained dc blocking voltage. Each GTO module has an associated gate driver circuit, and additional electronics are mounted on the pole to perform all of the control and protection tasks associated with the switching of that particular pole. The pole electronics communicate with the central controls located in the control room by means of an optical fiber cable. Thus the entire pole is self-contained with very few external connections. It has four power terminals (three to the dc bus, one to the ac output), cooling water inlet and return manifolds, the fiber optic cable and a single pair of auxiliary power leads. The modularity of this pole design lends itself to manufacturing and testing, and special testing facilities have been developed for the modules and the poles. GTO modules are individually tested at maximum rated stress before assembly into the poles, then pairs of poles are tested together in a unique test facility where they are subjected to full power operating conditions. The tested poles are easily assembled into the final inverter structure with low assembly cost and high confidence in their functionality. One of the concerns when constructing high-power valves from series-connected GTOs is that the individual devices should share the valve voltage equitably under both steady state and transient conditions. Individual GTOs differ especially in regard to their storage time at turn-off. These differences can result in the fastest device in a string experiencing the highest voltage following turn-off of the valve. To avoid this problem, the pole electronics senses the individual characteristics of each GTO and electronically compensates its gating command so that all devices in a string recover simultaneously.

Major Inverter Pole Subassemblies


Figure 3.2 shows the major modular electrical components and subassemblies on each pole. The pole is liquid cooled and a single inlet and a single outlet cooling manifolds distribute coolant to the various pole assemblies. The central portion of Figure 3.2 follows the physical layout of the pole equipment. All connections to the dc end occur 3-2

Advanced Pole Design

Figure 3-1 Advanced 3-Level Pole

3-3

Advanced Pole Design

Figure 3-2 Advanced Pole Layout

at one end of the pole and the ac connection occurs at the opposite end. This physical layout facilitates the simultaneous requirements to:

Minimize circuit inductance. Maintain proper distances for insulation. Minimize distance of cooling runs.

The function of each of the pole subassemblies identified in Figure 3.2 is as follows: High-Frequency Inverter Assembly: This assembly provides power isolated from ground for all the electronics on the pole including the gate drives and pole electronics assembly. It utilizes 130 V dc input and produces high-frequency ac output that is transmitted on the pole on the high-frequency current loop. High-Frequency Current Loop: Power for the pole assemblies is distributed via the high-frequency current loop. Individual gate drive assemblies and the pole electronics are coupled to the loop via torroidal current transformers. The high-frequency current loop passes through the center of each torroid. GTO Modules: The main elements of the pole are the series-connected GTO modules. Each GTO module contains a GTO with a reverse-parallel diode and associated snubber components together with the GTOs gate drive circuit. The GTOs are rated for 4500 V

3-4

Advanced Pole Design

and 4000 A peak turn-off capability. There are presently several major suppliers of GTOs with this power rating. Figure 3.3 shows the physical details of the GTO module.

Figure 3-3 GTO Module Layout

Gate Drive Electronics: The gate drive electronics assembly connected to each GTO module provides the current pulses required to switch the GTO thyristor off and on. The gate drive circuit has sufficient energy storage capability to provide a gate pulse for switching the GTOs, and to maintain current through the gate for the time the GTO is in conduction. Each gate drive is connected to the pole electronics by fiber optic links. Pole Electronics Assembly: The main function of this unit is to manage the internal control of the pole, including all aspects of each GTO gating and protection. It contains the logic that times the turn-off pulses to assure that the series-connected GTOs in each valve share voltage under dynamic switching conditions. Similarly, the pole electronics can initiate, delay, and inhibit valve gating to ensure that the valves operate within design limits. The pole electronics assembly communicates with the central control system via serial fiber optic links. Although the pole electronics manage all of the critical timing and protective functions associated with switching the valves within the pole, the central control determines the overall switching pattern and the state of the valves. The GTO modules are designed to provide maximum reliability. The module cooling system will be designed to maintain a conservative GTO junction temperature of no more than 90 degrees C under normal operating conditions. Westinghouses unique module heat sinks are de-signed to maintain even contact to the faces of the GTOs. This 3-5

Advanced Pole Design

is very important to main even distribution for current conduction and heat dissipation. GTO manufactures have confirmed this by checking the cathode island imprint inside the GTO after extended operation. Figures 3.4 through 3.6 show the pole structure and how the modular components will be mounted to the pole. According to this concept, the four valves comprising a threelevel pole are mounted on a single unified horizontal beam together with all of the auxiliary power circuit and pole control components. The modular pole offers great advantages with regard to manufacturing, test, maintenance and final assembly of the inverter installation. The complete pole assembly will be designed with the appropriate levels of redundancy to maximize availability. Each inverter valve in the pole is designed to operate safely for extended periods with one failed GTO module, thus enabling the equipment to operate until the next scheduled outage when the module could be replaced. There are redundant light fibers to each GTO gate drive to assure turn-on.

Power System Application


The advanced inverter pole was designed to be employed in the worlds first application of a Unified Power Flow Controller (UPFC) on the American Electric Power (AEP) grid. The UPFC equipment comprises two identical GTO-thyristor-based inverters, each rated at 160 MVA. The anticipated maximum real power exchange between the inverters is 80 MW, although they are designed to accommodate higher real power levels if necessary. Each inverter includes multiple high-power GTO valve structures feeding an intermediate (low voltage) transformer. The inverter output is a three-phase voltage set of nearly-sinusoidal (48-pulse) quality that is coupled to the transmission line by a conventional (3-winding to 3-winding) main coupling transformer. The inverter-side voltage of the main transformer is 37 kV line-line (for both shunt and series transformers.) The shunt-connected transformer has a 138 kV delta-connected primary, and the series transformer has three separate primary windings each rated at 16 percent of the phase voltage. To maximize the versatility of the installation, two identical main shunt transformers and a single main series transformer have been provided. The transformers are connected to the inverters through buswork and

3-6

Advanced Pole Design

Figure 3-4 Advanced Pole Elevation View

3-7

Advanced Pole Design

Figure 3-5 Advanced Pole Sectional View

3-8

Advanced Pole Design

Figure 3-6 Advanced Pole Plan View

3-9

138 kV

SHUNT TFMR

SPARE SHUNT TFMR

SERIES TFMR

INTERMEDIATE TRANSFORMER

INTERMEDIATE TRANSFORMER

INVERTER 1

INVERTER 2

Figure 3-7 UPFC One-Line Diagram

manually operated disconnect switches as indicated in the simplified one-line diagram in Figure 3.7. With this arrangement, a number of power circuit configurations are possible. Inverter 1 can operate as a STATCOM with either one of the two main shunt transformers, while Inverter 2 operates as an SSSC. Alternatively, Inverter 2 can be connected to the spare main shunt transformer and can operate as an additional STATCOM. With the latter configuration a formidable shunt reactive capability of 320 MVA would be available. The power circuit layout thus reflects AEPs emphasis on shunt compensation as the top priority for this location. Under normal operating conditions the installation will be configured as a UPFC with the two inverters connected at their dc terminals. However, in the event that either inverter would be removed from service for any reason, the other inverter can be disconnected by means of dc-bus switches and can operate independently. Of course the single inverter can only negotiate reactive power under this stand-alone condition, since there is no real power source or sink available at its dc terminals.

3-10

Advanced Pole Design

UPFC Power Circuit


A simplified schematic of the inverter power circuit is shown in Figure 3.8 Each inverter uses twelve three-level poles (shown symbolically) with a nominal maximum dc working voltage of 24 kV. The valves in each pole switch at 60 Hz and the phase of the switching is strategically controlled from one pole to the next to facilitate harmonic elimination. The pole ac outputs are fed to an intermediate transformer where harmonics in the rectangular pole voltage waveform are removed by cancellation. The resulting 48-pulse voltage waveform is nearly sinusoidal and is coupled to the transmission line through a conventional main coupling transformer. The total MVA rating of the intermediate transformer is approximately 50 percent of the main transformer rating.
138kV BUS

MAIN TRANSFORMER

INTERMEDIATE TRANSFORMER
DC VOLTAGE CLAMP

Figure 3-8 UPFC Power Circuit

3-11

4
ADVANCED POLE TESTING
Pole Type Tests
The pre-production advanced inverter pole underwent a series of design verification tests in Westinghouses high power inverter pole test facility. A list of these tests is provided in Table 4.1. A significant technical project milestone was reached when the H-bridge was operated at full voltage dc voltage (24kV) and ac current (1400A).

Basic Pole Test Facility Functions


Simplified schematics of the test facility are shown in Figures 4.1 and 4.2. The inverter poles are tested in pairs as H-bridges as shown in these figures. The test facility has a positive and a negative dc-voltage source, the outputs are adjustable to produce output from 0 to 20kVDC. These are connected through high voltage diodes and a 5-Ohm resistors to two 500f DC-Capacitor banks. The dc-capacitors which are similar to those that will be installed at Inez, connect to the pole positive, mid-point(ground) and negative DC-input terminals of the two poles under test. An adjustable 60Hz AC current source, 0 - 2,600Arms (as presently configured) is connected between the ACoutput terminals of these poles. A special control system provides gating signals for the inverter poles so that at any instant both pole output voltages are at the same voltage, i.e. they are both connected to the positive, mid-point(zero) or negative side of the dc source. In the normal switching mode, the two inverter poles are operated exactly in phase with one another in synchronism with the 60Hz current source. Because the poles are exactly in phase, and there is no voltage developed between their ac output terminals, the magnitude of the current can be independently adjusted as required. The ac current flows out of one pole into the other and never through the dc source. By adjusting the magnitudes of the ac current and the dc-voltage independently, and adjusting the phase angle at which the two poles switch relative to the current, the inverter poles can be tested under realistic conditions representative of any steady state or overload operating conditions that will be experienced when they are operate in the shunt or series inverters to be installed at Inez. 4-1

Advanced Pole Testing Table 4-1 Prototype Pole Test Milestones


Milestone Item Description Pole Operation (See Attached Figure) Either both upper valves or both lower valves continuously gated on full time to effectively make a short circuit at the ac input terminals AC Current 0 to 1400A rms DC Voltage 0 Volts Critical Measurements 1. Measure device forward voltage drops 2. Measure Conduction losses 3. Check for heating of valve metal structures due to induced eddy currents 1. Measure static offstate voltage distribution across valves to verify proper sharing 1. Verify ability of valves to switch under low current 2. Check quality of output voltage waveform 1. Verify ability of valves to switch under high voltage and high current 1. Verify capability of valve to operate under overload conditions short term 1. Verify ability of GTO's to turn off 3000A peak current

1 High current/low voltage test

2 Maximum dc voltage All valves off test

0 (AC side Vary from 0 disconnected) up to 24kV

3 No load switching up Alternately switch valves to to full voltage produce 3-level output voltage

0 (AC side Vary from 0 disconnected) up to 24kV

4 Full load tests at rated voltage and current

Alternately switch valves to produce 3-level output voltage

0 to 1400A rms

Vary from 0 up to 24kV

5 Overload tests - Both Alternately switch valves to voltage and current produce 3-level output voltage

Vary from 0 up Vary from 0 to 2500A peak up to 26kV in GTOs

6 Protection tests

Alternately switch valves to produce 3-level output voltage

Vary from 0 up Vary from 0 to 3000A peak up to 24kV in GTOs

4-2

Advanced Pole Testing

Figure 4-1 H-Bridge Test Configuration

4-3

Advanced Pole Testing

Figure 4-2 H-Bridge Test Facility

4-4

Advanced Pole Testing

Because the voltage sources do not have to carry the current, and because the current source is basically shorted by the inverter poles, the voltage sources need only be rated to supply the switching losses and the current source only needs to supply the conduction losses of the two poles. In the event of a pole or control malfunction, the voltage source will trip of at a very low current and the current source loading can never increase. This is therefore a very safe test facility where the inverter poles can be tested at very high power levels with minimal risk to the poles or to the test facility. Figure 4.3 shows the expected conduction patterns in a 3-level inverter pole with real and reactive load. A detailed list of idealized test waveforms is listed in Appendix A.

Operator Interface
Basic functions of the special operator interface enable the GTOs to be gated in one of four operating modes. These operating modes enable the poles to operated either in the normal switching mode, or to operate with continuous gating applied to either the UPPER, MID or LOWER pair of GTO valves in both poles. The operator interface uses two basic control angles and to control the magnitude and phase of the fundamental pole output. To compensate for small differences (1) in switching delays of the poles supplying and receiving ac current, two additional inputs and , are used to finely adjust the control angles used to control one pole relative to the other. This fine adjustment is necessary because the turn-off delays of the GTOs (typically 5 to 15s) vary with the magnitude of current while turn-on delays are much shorter and are relatively constant. If these delays are uncompensated, or da and db improperly adjusted there will be short intervals of time when the pole output voltages are not the same and dc voltage will be is applied to the current source inductor. These differences will cause undesirable rapid step like changes in the sinusoidal current. The operator interface also contains diagnostic displays which are intended to indicate faults in the pole, including failures of individual GTO modules and diodes.

Test Instrumentation
During preliminary tests individual module voltages were monitored on an Oscilloscope using ten Tektronix A6906S Fiber Optic Isolation Systems equipped with Tektronix P6015A High Voltage Probes. High voltage measurements are made using Ross high voltage dividers with 20 meter cables and special frequency compensated custom terminations. Using these dividers, with their outputs connected through a grounded interface panel, voltages to ground can be safely monitored at any point on a pole by jumpering the test point on the panel to a Tektronix DSA602A digitizing signal analyzer. 4-5

Advanced Pole Testing

Figure 4-3 3-Level Pole Conduction Patterns

4-6

Advanced Pole Testing

The dividers are arranged in two sets of ten, each set is spaced to readily connect to across the GTO modules in a valve and mounted on two planks that can be located close to any pair of valves. A third set of eight is mounted vertically on a mobile support to monitor the voltages on any mid-point or clamping diode stack.

BIL Tests
The very first check was to perform a BIL test on the poles to make sure they can withstand the high voltages that will be applied during continuous operation, as well as high voltages that may occur on a transient basis during field operation. All of these tests were successful and are summarized in Appendix B.

Preliminary Tests
Figures 4.4 and 4.5 show the schematics of the first two poles that were tested. A summary of the test steps and results for this first pole is presented in the following. Initially the HF inverters which supply power to the gate drives and the gate drives were tested by monitoring the HF Current loop and the gate drive outputs. Using continuous gating, AC current having a magnitude of 2500 Amperes was circulated between the ac outputs of the poles while the conduction drops and the temperature rise of GTO Module and each Mid-Point diode level were observed. The conduction drops, losses and temperature rises were well within design limits. Preliminary successful switching mode tests were made with the angle set at 90 and the angle set at 90 or 270, where transitions in the voltage were equally separated at 90 intervals and the load current was reactive.

Switching Mode Tests


Dynamic and static voltage distribution across all GTO Valves and Modules on the positive side of the poles, all Mid-Point Diodes, and some clamping diodes were observed looking at families of voltage waveforms from the Ross divider outputs. Three pairs of Ross dividers having a higher bandwidth were used to look differentially at voltages across entire GTO valves or diode stacks. One Tektronix A6906S Fiber Optic Isolation Systems re-equipped with Tektronix 5100 Voltage Probe, good for 2500V max. was good for looking at individual GTO or diode voltages. Using this probe and some Power Electronic Measurements Ltd. current waveform transducer which employ Rogowski coils some detailed test data was collected on the behavior of individual GTOs, diodes and other components. 4-7

Advanced Pole Testing

Figure 4-4 Prototype Pole A1

4-8

Advanced Pole Testing

Figure 4-5 Prototype Pole A2

4-9

Advanced Pole Testing

Hard copies of waveforms, and meter readings of the average voltages appearing between divider outputs representing the device voltages have been recorded to verify that the static and dynamic voltage distribution is such that all devices substantially share the voltage on each valve and verify that no device is burdened with peak overshoot or settled voltage in excess of its recommended operating level. The data obtained indicates that all devices are operating well within their capabilities and well within the range required for reliable operation over many years of operation. Appendix C contains a detailed set of recordings taken during these preliminary tests.

Mid-Point Diodes
Initial measurements on the Mid-Point diodes revealed an unacceptable spread in the dynamic voltage distribution resulting from a mismatch in the reverse recovery charges of the originally installed diodes. Since that time, data on the Qrr of all the diodes in prototype and for production poles has been obtained. Simply by sorting these diodes it will be possible to divide the diodes into closely matching groups that will be used in the production poles. On the prototype pole matching was achieved by changing one diode with the lowest recovery charge. This was sufficient to enable the pole to operated to voltages well above the maximum required operating level.

GTO Valves
One of the concerns when constructing high-power valves from series-connected GTOs is that the individual devices should share the valve voltage equitably under both steady state and transient conditions. Individual GTOs differ especially in regard to their storage time at turn-off. These differences can result in the fastest device in a string experiencing the highest voltage following turn-off of the valve. To avoid this problem, the pole electronics senses the individual characteristics of each GTO and electronically compensates its gating command so that all devices in a string recover simultaneously. The effectiveness of this technique is illustrated in the oscillogram of Figure 4.6, showing the voltage distribution in a valve with nine GTOs in series following turn off of the valve. The total dc-bus voltage is 29kV, and the voltage across individual GTO modules is the difference between adjacent traces.

Heat Run
The poles were both operated in the STATCOM mode with the purely reactive current leading and lagging the voltage by 90 for two 20 minute periods. During these test the dc voltages were set at 14.5kV and the output current magnitude set at 2,500A. After each of these runs the cooling system was shut off and temperature stickers fixed to various components were noted. 4-10

Advanced Pole Testing

Figure 4-6 Voltage Distribution Across Nine GTOs in Series

Protective Mode Test


The protective current limit turn-off tests were made by passing the current through the continuously gated inner valves, while the dc-voltage sources were turned off. This test was performed by increasing the current until the gating was interrupted at 3000 Amperes. When this occurred, gating was removed momentarily for about 2ms at each occurrence and energy from the current source inductor was transferred to the dc-link capacitors, each turn off pumping up the dc-voltage a little higher until gating was inhibited due to the controls over voltage protection scheme. The first few times this test was performed the dc link pumped up to 18.5kV. while the current was repetitively turned off at 3,000A. (55.5MW instantaneous). Further tests were then performed with dc over-voltage inhibit reduced to 12.5kV. These tests were successful.

Production Test Summary


The successful prototype pole tests lead the way to the production tests. A detailed test report on a typical H-bridge is included in Appendix D. This type of test was performed on a total of 24 poles (12 H-Bridges) through the course of the UPFC program. A brief summary of the checks performed during these tests is as follows:

Test hf inverters measure loop current. 4-11

Advanced Pole Testing

With gating disabled check that all gates are reverse biased to 15v. Check pole a1 and a2 status indicators on genesis display screens. Connect shorting link to ac current source then measure and record losses in current source as a function of current. With gating disabled turn on dc voltage sources to low level and check that voltage division is good before increasing to maximum voltage. Record voltages across all gto modules and midpoint diodes using pole mounted digital meters and ross dividers with fluke 8060a.meter. Use ross divider and rogowski coil current sensor to monitor ac output of pole at all times. Set a to 90, enable gating raise dc voltage slowly while checking static and dynamic voltage distribution using pole mounted digital meters and ross dividers with tektronix ds602a digital waveform analyzer and fluke 8060a.meter use rogowski coil with opto isolator to measure current and di/dt in all valves. Connect pole outputs to current source. With continuous gating of upper, lower and inner gto valves, set current to 2,500a peak and observe conduction voltage drops across all modules and mid point diodes. Maintain current at 2,500 a peak, and with water flow set at the minimum rate, measure temperatures of heat sinks and temperature rise on all components for each of the three continuous current paths. Set a to 7.5 and set b so that current leads (and then lags) pole voltages by 90 enable firing, increase dc voltages to 14.5kv, measure and record peak and settled voltage across each gto valve. Use rogowski coil with opto isolator to measure current and di/dt in all valves. Turn on and raise current to 2000a peak and repeat measurements of peak and settled voltages. Record maximum temperatures of all stickered components. Repeat last two tests with peak current of 2,500 a. Run pole for 8 hours with dcv = 14.5kv and peak current = 2,500a with a set at 7.5 and b set at 90. Record maximum temperatures of all stickered components. Run pole for 8 hours with dcv = 14.5kv and peak current = 2,500a with a set at 7.5 and b set at 270. Record maximum temperatures of all stickered components. Measure ac and dc input power at above angle settings with:

4-12

Advanced Pole Testing

1. DCV = 12.2KV 2. DCV = 12.2KV 3. DCV = 12.2KV 4. DCV = 14.5KV

AC OUTPUT = AC OUTPUT = AC OUTPUT = AC OUTPUT =

ZERO (DISCONNECTED) 2000A PEAK 2500A PEAK 2500A PEAK

4-13

5
ADVANCED POLE INSTALLATION
As discussed in Section 2, the first application of the advanced pole was in the worlds first Unified Power Flow Controller (UPFC) installed at American Electric Powers (AEP) Inez substation in eastern Kentucky. Figure 5.1 shows the layout of the UPFC installation. Figure 5.2 shows an aerial view of the Inez substation and the UPFC equipment. The two inverters, the control room, GTO gating power supplies, and auxiliary equipment associated with the cooling system are all accommodated in a 200' by 100' building. The building is generously sized and includes a visitors viewing gallery above the control room. The liquid to air heat exchangers for the cooling system are located outdoors along the back of the building together with the cooling system pumps. Purification equipment for the cooling water is located indoors in the auxiliary equipment corridor at the back of the building. The two inverters are housed in a separate valve hall. Figure 5.3 shows a long view of both shunt and series inverter stacks. Figure 5.4 shows a long view of one inverter pole stack. The twelve poles for each inverter are arranged in four parallel vertical stacks, each three-high, with the common dc-bus and associated capacitors located at the ends of the poles toward the back of the building. The twelve ac output busses from the poles are brought to a uniform height above the topmost poles and then pass through the front wall of the building in parallel arrangement. These busses continue outdoors to the intermediate transformer, the main transformer, and various switchgear.

5-1

Advanced Pole Installation

Figure 5-1 UPFC Installation Layout

Figure 5-2 Aerial View of Inez Site

5-2

Advanced Pole Installation

AC Bus

Mid Point Diode Stack

High Frequency Inverter

DC Bus Clamp

DC Capaci

Figure 5-3 Installed Shunt and Series Inverters

5-3

Advanced Pole Installation

Di/ Dt Reactor Clamp Resistor

Clamp Diode Stack Clamp Capacitor

Gate Drives GTO Modules

Mid Point Diode Stack Pole Electronics Box

Figure 5-4 Detail of Advanced Inverter Pole Stack

5-4

6
TEST RESULTS FROM UTILITY APPLICATION
The final phase of this project was to test the performance of the advanced valve in several modes of operation of a large FACTS installation. As discussed in Section 5, the 3-level valves were installed and tested at AEPs Inez substation site in two phases. During the first phase, the first of the two UPFC inverters was installed and tested as a STATCOM. This is shown as Inverter No. 1 in Figure 6.1. Each inverter has a power rating of 160MVA. This was be the first time the advanced three-level pole operation was tested in an actual utility application. Inverter No. 2 was installed during the second phase of the program and was first tested as a STATCOM. Both inverters were then operated, first as dual STATCOMs, then with Inverter No. 2 as a Static Synchronous Series Compensatior (SSSC), and finally with both inverters operating as a UPFC.

Preliminary Tests
An important advantage of GTO-based inverter equipment is that it can be commissioned off-line to a large extent because it does not depend on the presence of line voltage for commutation (as does a conventional SVC). The STATCOM portion of

Figure 6-1 Connection of UPFC Inverters to Utility System

6-1

Test Results from Utility Application

the UPFC was energized by means of a temporary high-voltage dc power supply connected to the dc bus before connecting to the line. This test allowed the voltage to be raised slowly while normal inverter gating was in progress, and all aspects of the inverter performance were carefully verified. In particular the waveform construction through the intermediate and the main transformer was checked, as well as the sense and functionality of all analog feedback signals. After running at full voltage under this condition it was possible to close onto the transmission line with a high degree of confidence, and the current control and voltage control functions were successfully enabled. After the basic on-line operation of the STATCOM was established, extensive commissioning tests were performed to record the behavior of the equipment under various conditions. During these tests, the STATCOM operated in automatic voltage control mode, and waveforms were recorded over a wide range of operating points. Several large step changes in voltage were commanded and local capacitor banks were switched in and out. Outages of two local transmission lines were initiated and the tests were repeated for each of these conditions. During these latter tests the system impedance was considerably increased, but the STATCOM continued to provide stable and effective voltage control.

STATCOM Performance
The fault capacity on the 138 kV bus at the Inez substation is presently approximately 1300 MVA with all lines in service, and considerably weaker with any line outage. This situation is expected to change when the Big Sandy/Inez line is completed and again in the future when new connections to the EHV system are made. It is thus difficult to exercise the STATCOM to its rated var limits without producing very large voltage swings. To some extent it has been possible to work against the local capacitor bank in the inductive mode, but the voltage is low even with the capacitors connected and a very limited inductive range (about 60 Mvar) is achievable. In the capacitive mode a greater range is achievable. The voltage has been maintained at 1.02 p.u. with the capacitive var output of the STATCOM ranging from 80 to 105 Mvar. For a short time the STATCOM has been taken to about 140 Mvar capacitive, producing 1.06 p.u. voltage on the bus. Nevertheless, the observed performance of the STATCOM has been very good in all respects. To illustrate the underlying dynamic response, a set of waveforms were recorded for a case where the STATCOM was asked to step from 0.3 p.u. inductive to 0.8 p.u. capacitive var output. In this case automatic voltage controls were disabled and the stepped reference was injected into the STATCOM current control system. The result is shown in Figure 6.2. This step produced a swing of about 180 Mvar with about 14% change in bus voltage. It is particularly significant that the STATCOM is seen to operate well under these weak system conditions, since the previous STATCOM application at TVA was on a relatively strong bus.

6-2

Test Results from Utility Application

Figure 6-2 STATCOM Response

6-3

Test Results from Utility Application

Dual STATCOM Tests


Once the second inverter was installed at Inez, the first objective to commission the second inverter as a STATCOM, and then operate both inverters as dual STATCOMs capable of providing up to 320MVA of compensation to the Inez bus. The tests confirmed the capability of the STATCOM controls to result in both inverter sharing current during steady state conditions as well as transient conditions. Figure 6.3 shows the results of one of the tests in VAR control mode, where the bus voltage was free to change (within system limits) while the VAR demand for both inverters was adjusted to measure response. This shows Inverter #1 demand increased to cancel out the VARs provided by Inverter #2. Inverter #1 is started at 0 MVA and then the VAR demand is switched to +78MVA to cancel out the -78MVA provided by Inverter #2. Figure 6.4 shows the results in voltage control mode, where the voltage is stepped from .96 to 1.00PU while the inverters share the VAR demand. The slope for both inverters was programmed for 1.5%. There is some overshoot in the response due to the fact that the system gain was effectively doubled by having both inverters provide the same level of control in single STATCOM mode. This effect can be removed by cutting the gain of the each inverter in half.

Bypass Protection Tests


Before the second inverter could be operated as a series element, it is was necessary to test and confirm the series bypass protection scheme. The bypass is critical for series inverter protection in the event of fault in AEP's power system or in the UPFC inverter equipment. Previous studies showed that the fault capacity of the AEP system to the year 2000 was low enough to permit electronic bypass using the GTO inverter valves without a separate thyristor bypass switch. Without an external bypass, the series inverter must rapidly reconfigure the firing pattern of the inverter valves to go into bypass protection mode before the fault current exceeds the turn-off capability of the GTOs. Figure 6.5 shows the three possible ways to produce a short circuit at the ac terminals of a three-level pole. The darkened switches are the ones turned on for each case. The selection of which of these modes is selected for bypass depends on the state the switches prior to initiation of the fault. Figure 6.6 shows the test results, where during a simulated fault, the Phase A current reaches the trip level of 1.5PU (3000A). The bypass is successfully initiated, and the rise of current in Phase A is stopped and the currents decay down to zero.

6-4

Test Results from Utility Application

Figure 6-3 Dual STATCOM Test in VAR Control Mode

6-5

Test Results from Utility Application

Figure 6-4 Dual STATCOM Test in Voltage Control Mode

6-6

Test Results from Utility Application

Figure 6-5 Valve Bypass Configurations

Figure 6-6 Bypass Test Results

6-7

Test Results from Utility Application

UPFC and SSSC Tests


In the course of commissioning the UPFC, tests were performed to verify its predicted capability. For this purpose, the UPFC was directed to produce large controlled swings of real and reactive power on the Big Sandy line, and sizeable swings of voltage at the Inez station, while measurements were recorded. It must be emphasisized that these swings are not the "normal" duty for the UPFC in this application. AEP system operators defined acceptable boundary limits for the tests and, to soften the impact on the system, slow ramping functions were applied to the power control references for the UPFC. Measured data was available from the UPFC control system and was recorded at one second intervals. Five representative cases have been selected. The first three cases show the UPFC independently controlling real power (P) on the line, reactive power (Q) at the Inez end of the line, and Inez bus voltage respectively. The fourth case is for the UPFC maintaining unity power factor on the line, and the final case is a demonstration of the series inverter operating as an SSSC. In all cases (except the SSSC), the UPFC is operating with the shunt inverter in automatic voltage control mode and the series inverter in automatic power flow control mode. Each set of results is annotated using the sign convention shown in Fig. 1. Note in particular that P and Q for the line are measured at the line-side terminals of the series insertion transformer. This is the actual power at the end of the line, and is defined as positive towards Big Sandy.

Case 1. UPFC Changing Real Power (P)


This case starts with the UPFC idling near zero injected voltage and the real power flow on the line near the "natural" level of 150 MW from Big Sandy. The shunt inverter is regulating the Inez bus to 1 p.u. (using 60 Mvar capacitive output), and about 36 Mvar are being delivered into the line. The objective for this test is to maintain the Inez bus voltage and the line Q unaltered, while making big step changes in line P. The results are shown in Figure 6.7.

The UPFC is first commanded to raise the line power to 240 MW. (It does this by injecting a voltage of about 0.16 p.u. roughly in quadrature with (lagging) the Inez bus voltage. To satisfy the required conditions, the shunt inverter drops its capacitive output to about 20 Mvar, and the series inverter delivers about 40 Mvar capacitive to the line.) The second transition commanded is a 170 MW drop in the line power to 70 MW. (This is accomplished with little change in the magnitude of the injected voltage, but about 180 degrees phase shift, so that the injected voltage is now still roughly in quadrature with the Inez bus voltage, but leading. The shunt inverter produces

6-8

Test Results from Utility Application

1.05 INEZ BUS VOLTAGE (PU) 1 0.95 0 10 20 30 40 50 60 70 80 90 100

200 100 0 -100 -200 -300 0 10 20 30

LINE REAL POWER (P) MW LINE REACTIVE POWER (Q) Mvar

40

50

60

70

80

90

100

100 50 0 -50 -100 0 10 20

SHUNT INVERTER REACTIVE POWER (Mvar)

30

40

50

60

70

80

90 Ti

100 ( )

Figure 6-7 UPFC Changing Real Power

6-9

Test Results from Utility Application

about 85 Mvars capacitive, and the series inverter reverses its output to 10 Mvar inductive.)

The final transition returns the system to the initial operating point (150 MW from Big Sandy). Throughout this test the Inez bus voltage is tightly regulated at 1 p.u. and Q on the line stays constant. It should also be noted that the large changes in real power arriving at Inez must, of course, be balanced by an equal and opposite total change in the power on the other lines leaving the station.

At the time when these tests were performed the natural power flow on the line was too high for the UPFC to demonstrate its unique ability to reverse power flow. On other occasions, however, when the line has been lightly loaded, this has been demonstrated successfully and the UPFC has driven real power back towards Big Sandy.

Case 2. UPFC Changing Reactive Power (Q)


The initial conditions for this test are similar to Case 1. The objective of the test is to regulate the Inez voltage at 1 p.u. and keep the line real power, P, constant while causing large steps in the line reactive power, Q. The results are shown in Figure 6.8.

The UPFC reference for Q is first changed from +30 Mvar to -30 Mvar. (The UPFC forces the change by injecting about 0.05 p.u. voltage roughly in anti-phase with the Inez bus voltage, V1. The line voltage, V2, is consequently reduced in magnitude by about five percent.) For the second step, the Q reference is taken to +100 Mvar (i.e. 100 Mvar to the line). (This time the injected voltage is in phase with the Inez bus voltage, so that V2 is increased by about five percent.) The final step reduces the Q reference to zero. (The line is now fed at unity power factor with V2 reduced by about 2.5 percent relative to V1.) Note: Since the shunt inverter is regulating the Inez bus to 1 p.u. voltage, it automatically produces var swings in its output that are equal and opposite to the swings in Q on the transmission line.

Case 3. UPFC Changing Local Bus Voltage

The objective for this test is to produce a large voltage change at Inez on command, while maintaining an unaltered level of P and Q on the line. For the test the voltage reference is stepped from an initial value of 0.985 p.u., to 1.02 p.u., to 0.95 p.u., and back to 0.985 p.u. The UPFC successfully holds the line P and Q constant (using very small changes in injected voltage), while the shunt inverter goes from its initial

6-10

Test Results from Utility Application

1.05 INEZ BUS VOLTAGE (PU) 1 0.95 0 300 200 100 0 -100 -200 -300 0 150 50 -50 -150 0 10 20 30 40 50 60 70 Ti
Figure 6-8 UPFC Changing Reactive Poweroutput of 40 Mvar capacitive, to 100 Mvar capacitive, to 0 Mvar, and back to 40 Mvar capacitive. The results are shown in Figure 6.9.

10

20

30

40

50

60

70

80

LINE REAL POWER (P) MW LINE REACTIVE POWER (Q) Mvar

Q P

10

20

30

40

50

60

70

80

SHUNT INVERTER REACTIVE POWER (Mvar)

80 ( )

Case 4. UPFC Holding Unity Power Factor


The objective for the test is to maintain unity power factor looking into the transmission line, while producing large swings in real power, P, on the line, and also maintaining the Inez bus at 1 p.u. This case is of particular interest because driving a line at unity power factor should, in principle, make it possible to deliver the largest amount of real power into the line for the lowest current. This should result in the most efficient use of the line from a thermal point of view. Naturally, the reactive power consumed by the line itself must now be supplied at the other end of the line, resulting in higher voltages at that end.) The results are shown in Figure 6.10.

6-11

Test Results from Utility Application

Case 5. Series Inverter in SSSC Mode


For this test, the shunt inverter is disconnected from the dc terminals of the series inverter and is completely out of service. Consequently the Inez bus voltage is not regulated. The series inverter injects voltage into the line essentially in quadrature with the prevailing line current. By means of the quadrature voltage injection, the SSSC is able to raise or lower the line current, but cannot independently alter P and Q. SSSC operation is an important subset of full UPFC operation, since it can be used when the shunt inverter is not available. The results are shown in Figure 6.11. The objective of the test is simply to show the SSSC raising and lowering the power on the Big Sandy line. Voltage injections are selected to give a sequence of approximately 100 MW, 180 MW, 250 MW, and finally 200 MW on the line. Note the corresponding changes in Q. Note: The series inverter in SSSC mode achieves voltage control by changing the dc bus voltage while keeping a fixed firing pattern on the inverter.
1.1 1.05 1 0.95 0.9 0 300 LINE REAL POWER (P) MW 200 LINE REACTIVE POWER (Q) Mvar 100 0 -100 -200 -300 0 10 20 30 40 50 60 70 80 90 10 20 30 INEZ BUS VOLTAGE (PU)

40

50

60

70

80

90

Q P

150 50 -50 -150 0 10 20 30 40 50 60 70 80 90 Time (s) SHUNT INVERTER REACTIVE POWER (Mvar)

Figure 6-9 UPFC Changing Local Bus Voltage

6-12

Test Results from Utility Application

1.05 INEZ BUS VOLTAGE (PU) 1 0.95 0 300 LINE REAL POWER (P) MW 200 LINE REACTIVE POWER (Q) Mvar 100 0 -100 -200 -300 0 10 20 30 40 50 60 70 10 20 30 40 50 60 70

Q P

150 100 50 0 -50 -100 0 10

SHUNT INVERTER REACTIVE POWER (Mvar)

20

30

40

50

60 Ti

70 ( )

Figure 6-10 UPFC Holding Unity Power Factor

6-13

Test Results from Utility Application

1.05 INEZ BUS VOLTAGE (PU) (unregulated) 1 0.95 0 250 LINE REAL POWER (P) MW 150 50 -50 -150 -250 0 10 20 30 40 50 60 70 Time (s) LINE REACTIVE POWER (Q) Mvar 10 20 30 40 50 60 70

Figure 6-11 Series Inverter Operating in SSSC Mode

6-14

7
CONCLUSIONS
The completion of the advanced valve project is another important milestone in the progress of FACTS technology. The successful new high-voltage inverter design, based on the use of three-level poles, has demonstrated clearly that GTO-based voltagesourced inverters are practical and effective, and can be applied at very high power levels in wide variety of FACTS applications. The high-power three-valve has finally made the transition from concept to practical reality with the successful application at the AEP UPFC Inez installation. The measured performance test results presented here verify in all respects the tremendous versatility of the three-level valve as predicted in studies and modeling activities over the preceding years. It is expected that this technology will be deployed in a wide range of equipment to provide operational flexibility, performance improvements, and overall cost reductions in FACTS and HVDC equipment.

7-1

A
Idealized Pole Waveforms

A-1

B
ADVANCED POLE BIL TEST REPORT

B-1

Advanced Pole BIL Test Report

BIL Test on the AEP UPFC Poles The AEP UPFC prototype pole assembly passed both a BIL (Basic Impulse Level) and a 1minute, 60-Hz withstand test. Test date was December 13, 1996. Coolant flowing through the poles had a measured resistivity of 1.2 M-cm. The supply pressure = 12 psig, return pressure = 6 psig, and the estimated flow was greater than 80 gallons per minute. The BIL test applied a 1.2 x 50 s waveform to the unit under test. A series of 3 consecutive impulses at the same voltage were applied. If the unit passed all three impulses at one level, a higher voltage level was then applied. If there was a flashover, the same voltage was reapplied three more times. Failure consisted of at least one flashover in each set of three impulses. The 2 hoses connecting the poles to the CPVC piping of the AEP test facility are metalreinforced. For safety reasons, they are grounded very near to the vertical pipes going to each pole. We used insulating material to prevent flashovers from the pole frame to these pipes. The two areas of concern for flashover were between the frame and these hoses, and between the gate drive power supply cable and the current transformers around the cable. The unit successfully passed 95 kV BIL (the rating of the base insulators). In fact, the pole successfully passed +110 kV (uncorrected). The value corrected for atmospheric pressure and temperature is +115 kV. To reach maximum negative values, we had to remove the base insulators at the center frame of the poles because of flashovers to the metal-reinforced hoses. After the insulators were removed, a series of three consecutive impulses at 110.5 kV or above was completed. (This was the corrected value). The limiting point was at the joint of the gate drive cables in the center of each pole. Correction factor = P (273+20)____ 760mm (273 + T) = 734.3mm (293) 760mm (296) = .9564

where P is barometric pressure in mm, and T is ambient temperature in degrees Celsius. Corrected value = Test value .9564 During the test, several observers watched to determine where a flashover occurred. See Photos of BIL waveforms

B-2

Advanced Pole BIL Test Report

The 1-minute 60-Hz Test was performed on the bottom pole only. The gate drive power supply cable was not completely manufactured for the top pole. In addition, the 60-Hz test transformer could only supply a maximum of 50 mA at 50 kV. The center conductor of the gate drive cable was grounded, and the voltage was applied to the ac bus at the end of the pole.

Voltage (kV)

Current (mA)

10 20 30 40 50

10 16 22 31 40

This was a successful test. The current shown in the table is the leakage current (corona) between the current transformers and the gate drive power supply cable. The coolant flowing through the poles had a measured resistivity of 1.4 M-cm.

C
PROTOTYPE TEST DATA

C-1

LIST OF TEST RECORDINGS AND DATA TAKEN ON AEP PROTOTYPE POLE


DATE 3/3/97 3/3/97 3/3/97 3/3/97 3/3/97 3/3/97 3/3/97 3/3/97 3/3/97 3/3/97 3/3/97 3/3/97 3/3/97 3/3/97 3/3/97 3/3/97 3/3/97 3/3/97 3/3/97 3/3/97 3/3/97 3/3/97 3/3/97 3/3/97 3/1/97 3/1/97 3/1/97 3/1/97 3/1/97 3/1/97 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 1 2 3 4 5 6 REC.# 90 90 7.5 7.5 7.5 7.5 7.5 7.5 7.5 7.5 7.5 7.5 7.5 7.5 7.5 7.5 7.5 7.5 7.5 7.5 7.5 7.5 7.5 7.5 7.5 7.5 7.5 7.5 7.5 7.5 -0.9586 0.9366 0.1016 -0.1346 0.1016 0.1016 0.1016 0.1016 -0.1346 -0.1346 -0.1346 -0.1346 -0.1346 -0.1346 -0.1346 -0.1346 0.1016 0.1016 0.1016 0.1016 0.1016 0.1016 0.1016 0.1016 0.1016 0.1016 0.1016 -0.1346 -0.1346 -0.1346 55 -125 145 -35 145 145 145 145 -35 -35 -35 -35 -35 -35 -35 -35 145 145 145 145 145 145 145 145 145 145 145 -35 -35 -35 -0.0082 -0.1675 -0.5686 0.4587 -0.5686 -0.5686 -0.5686 -0.5686 0.4587 0.4587 0.4587 0.4587 0.4587 0.4587 0.4587 0.4587 -0.5686 -0.5686 -0.5686 -0.5686 -0.5686 -0.5686 -0.5686 -0.5686 -0.5686 -0.5686 -0.5686 0.4587 0.4587 0.4587 DCVV 12.2 12.2 12.2 12.2 12.2 12.2 12.2 12.2 12.2 12.2 12.2 12.2 12.2 12.2 12.2 12.2 12.2 12.2 12.2 12.2 12.2 12.2 12.2 12.2 12.2 12.2 12.2 12.2 12.2 12.2 AC Arms 1420 1420 1420 1420 1420 1420 1420 1420 1420 1420 1420 1420 1420 1420 1420 1420 1420 1420 1420 1420 1420 1420 1420 1420 1420 1420 1420 1420 1420 1420 POLE LOWER LOWER LOWER LOWER LOWER LOWER LOWER LOWER LOWER LOWER LOWER LOWER LOWER LOWER LOWER LOWER LOWER LOWER LOWER LOWER BOTH BOTH BOTH BOTH LOWER LOWER LOWER LOWER LOWER LOWER PART AC-BUS AC-BUS AC-BUS AC-BUS DMP DMP DMP DMP DMP DMP DMP DMP CP1 CP1 CP1 CP1 CP1 CP1 CP1 CP1 EXT+R EXT+R EXT+R EXT+R VALVE P1 VALVE N1 VALVE P1 VALVE P1 VALVE N1 VALVE P1 DESCRIPTION Voltage and Current Absorbing Watts Voltage and Current supplying Watts Voltage and Current Absorbing VARS Voltage and Current Supplying VARS ACVout DMP Stack Voltage at P-MP-N transition ACVout DMP Current at P-MP-N transition ACVout DMP Stack Voltage at N-MP-P transition ACVout DMP Current at N-MP-P transition ACVout DMP Stack Voltage at N-MP-P transition ACVout DMP Current at N-MP-P transition ACVout DMP Stack Voltage at P-MP-N transition ACVout DMP Current at P-MP-N transition ACVout, +VDC,Vclamp at P-MP-N transition ACVout, Current in DiodeCP at P-MP-N transition ACVout, +VDC,Vclamp at N-MP-P transition ACVout, Current in DiodeCP at N-MP-P transition ACVout, +VDC,Vclamp at N-MP-P transition ACVout, Current in DiodeCP at N-MP-P transition ACVout, +VDC,Vclamp at P-MP-N transition ACVout, Current in DiodeCP at P-MP-N transition DC+,VrJCT, VACout at P-MP-N transition Current in ext R & VACout at P-MP-N transition DC+,VrJCT, VACout at N-MP-P transition Current in ext R & VACout at N-MP-P transition Output V & i and Current in Valve P1 Voltage Overshoot Voltage Overshoot Output V & i and Current in Valve P1 Voltage Overshoot Voltage Overshoot

LIST OF TEST RECORDINGS AND DATA TAKEN ON AEP PROTOTYPE POLE


3/1/97 3/1/97 3/1/97 3/1/97 3/1/97 3/1/97 3/1/97 3/1/97 3/1/97 3/1/97 3/1/97 3/1/97 3/1/97 3/1/97 3/1/97 3/1/97 3/1/97 3/1/97 3/1/97 3/1/97 3/1/97 3/1/97 3/1/97 3/1/97 3/1/97 3/1/97 3/1/97 3/1/97 2/26/97 2/26/97 7 6 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 1 2 7.5 7.5 7.5 7.5 7.5 7.5 7.5 7.5 7.5 7.5 7.5 7.5 7.5 7.5 7.5 7.5 7.5 7.5 7.5 7.5 7.5 7.5 7.5 7.5 7.5 7.5 7.5 7.5 7.5 7.5 -0.1346 -0.1346 0.1016 0.1016 0.1016 0.1016 0.1016 0.1016 -0.1346 -0.1346 -0.1346 -0.1346 -0.1346 -0.1346 -0.1346 -0.1346 0.1016 0.1016 0.1016 0.1016 0.1016 0.1016 0.1016 0.1016 -0.1346 -0.1346 -0.1346 -0.1346 0.1016 0.1016 -35 -35 145 145 145 145 145 145 -35 -35 -35 -35 -35 -35 -35 -35 145 145 145 145 145 145 145 145 -35 -35 -35 -35 145 145 0.4587 0.4587 -0.5686 -0.5686 -0.5686 -0.5686 -0.5686 -0.5686 0.4587 0.4587 0.4587 0.4587 0.4587 0.4587 0.4587 0.4587 -0.5686 -0.5686 -0.5686 -0.5686 -0.5686 -0.5686 -0.5686 -0.5686 0.4587 0.4587 0.4587 0.4587 -0.5686 -0.5686 12.2 12.2 12.2 12.2 12.2 12.2 12.2 12.2 12.2 12.2 12.2 12.2 12.2 12.2 12.2 12.2 12.2 12.2 12.2 12.2 12.2 12.2 12.2 12.2 12.2 12.2 12.2 12.2 12.2 12.2 1420 1420 1420 1420 1420 1420 1420 1420 1420 1420 1420 1420 1420 1420 1420 1420 1420 1420 1420 1420 1420 1420 1420 1420 1420 1420 1420 1420 1420 1420 UPPER UPPER UPPER UPPER LOWER LOWER LOWER LOWER LOWER LOWER LOWER LOWER UPPER UPPER UPPER UPPER UPPER UPPER UPPER UPPER UPPER UPPER UPPER UPPER UPPER UPPER UPPER UPPER UPPER UPPER VALVE N1 VALVE P1 VALVE N1 VALVE P1 VALVE N2 VALVE N2 VALVE P2 VALVE P2 VALVE P2 VALVE P2 VALVE N2 VALVE N2 VALVE N2 VALVE N2 VALVE P2 VALVE P2 VALVE P2 VALVE P2 VALVE N2 VALVE N2 DCP DCP DCP DCP DCP DCP DCP DCP P1-8 P1-8 Voltage Overshoot Voltage Overshoot Voltage Overshoot Voltage Overshoot Voltage Overshoot Voltage Overshoot Voltage Overshoot Voltage Overshoot Voltage Overshoot Voltage Overshoot Voltage Overshoot Voltage Overshoot Voltage Overshoot Voltage Overshoot Voltage Overshoot Voltage Overshoot Voltage Overshoot Voltage Overshoot Voltage Overshoot Voltage Overshoot ACVout, Vat ends of DCP at P-MP-N transition ACVout, Current in DiodeCP at P-MP-N transition ACVout, Vat ends of DCP at N-MP-P transition ACVout, Current in DiodeCP at N-MP-P transition ACVout, Vat ends of DCP at N-MP-P transition ACVout, Current in DiodeCP at N-MP-P transition ACVout, Vat ends of DCP at P-MP-N transition ACVout, Current in DiodeCP at P-MP-N transition ACV&ACA from Lower Pole defining points (A) & (B) Detail of complex (2-step) commutation at (B)

LIST OF TEST RECORDINGS AND DATA TAKEN ON AEP PROTOTYPE POLE


2/25/97 2/25/97 2/25/97 2/25/97 2/25/97 2/25/97 1 2 3 4 5 6 7.5 7.5 7.5 7.5 7.5 7.5 0.1016 0.1016 0.1016 0.1016 0.1016 0.1016 145 145 145 145 145 145 -0.5686 -0.5686 -0.5686 -0.5686 -0.5686 -0.5686 12.2 12.2 12.2 12.2 12.2 12.2 1420 1420 1420 1420 1420 1420 MITSUBISHI LOWER LOWER LOWER LOWER LOWER LOWER TOSHIBA UPPER UPPER UPPER UPPER UPPER UPPER UPPER UPPER P1-9 P1-9 P1-9 P1-9 P1-9 P1-9 ACV, ACAmps, GTOV & GTOAmps Defining points (A), (B) & (C) in cycle where GTO current pulses Expanded View of pulses (A) & (B) di/dt and GTO Vdrop at (A) di/dt and GTO Vdrop at (B) di/dt and GTO Vdrop at (C) di/dt falling and GTO Vdrop after (C) ACV, ACAmps, GTOV & GTOAmps Defining points (A), (B) & (C) in cycle where GTO current pulses Expanded View of pulses (A) & (B) di/dt and GTO Vdrop at (A) di/dt and GTO Vdrop at (B) di/dt and GTO Vdrop at (C) di/dt falling and GTO Vdrop after (C) ACV, ACAmps & Amps in GTO during 20 Min. burn-in ACV, ACAmps & Amps in GTO during 20 Min. burn-in ACAmps & GTO Amps at end of Overcurrent Protection test

2/25/97 2/25/97 2/25/97 2/25/97 2/25/97 2/25/97 2/25/97 2/25/97

7 8 9 10 11 12 14 15

7.5 7.5 7.5 7.5 7.5 7.5 7.5 7.5

-0.1346 -0.1346 -0.1346 -0.1346 -0.1346 -0.1346 -0.1346 0.1016

-35 -35 -35 -35 -35 -35 -35 145

0.4587 0.4587 0.4587 0.4587 0.4587 0.4587 0.4587 -0.5686

12.2 12.2 12.2 12.2 12.2 12.2 14.5 14.5

1420 1420 1420 1420 1420 1420 1776 1778

P1-8 P1-8 P1-8 P1-8 P1-8 P1-8 P1-8 P1-8

2/25/97

Continuous firing of inner valves

18.5kV max 3000Apk

BOTH MITSUBISHI LOWER LOWER LOWER LOWER LOWER LOWER LOWER

P1-8

2/24/97 2/24/97 2/24/97 2/24/97 2/24/97 2/24/97 2/24/97

0 1 2 2a 2b 2c 3

7.5 7.5 7.5 7.5 7.5 7.5 7.5

-0.1346 -0.1346 -0.1346 -0.1346 -0.1346 -0.1346 -0.1346

-35 -35 -35 -35 -35 -35 -35

0.4587 0.4587 0.4587 0.4587 0.4587 0.4587 0.4587

12.2 12.2 12.2 12.2 12.2 12.2 12.2

1420 1420 1420 1420 1420 1420 1420

P1-9 P1-9 P1-9 P1-9 P1-9 P1-9 P1-9

2/24/97

7.5

-0.1346

-35

0.4587

12.2

1420

LOWER

P1-9

2/24/97 2/24/97 2/24/97

5 6 7

7.5 7.5 7.5

-0.1346 -0.1346 -0.1346

-35 -35 -35

0.4587 0.4587 0.4587

12.2 12.2 12.2

1420 1420 1420

LOWER LOWER LOWER

P1-9 P1-9 P1-9

2/24/97

7.5

0.1016

145

-0.5686

12.2

1420

LOWER

P1-9

ACV, ACAmps, GTOV & Anti-pll Diode Amps ACV, ACAmps, GTOV & GTOAmps Defining points (A), (B) & (C) in cycle where GTO current pulses Expanded View of pulses (A) & (B) di/dt and GTO Vdrop at (A) di/dt and GTO Vdrop at (B) ACV, ACAmps, GTOV & GTOAmps Defining points (A), (B) & (C) in cycle where GTO current pulses di/dt and GTO Vdrop at (C) ACV, ACAmps, (GTOV-PROBE SHORTED) & GTOAmps Defining points (A), (B) & (C) in cycle where GTO current pulses ACV, ACAmps, (GTOV-with small loop) & GTOAmps Defining points (A), (B) & (C) in cycle where GTO current pulses di/dt and GTO Vdrop at (A) Expanded View of pulses (A) & (B) ACV, ACAmps, (GTOV-with small loop) & GTOAmps Defining points (A), (B) & (C) in cycle where GTO current pulses

LIST OF TEST RECORDINGS AND DATA TAKEN ON AEP PROTOTYPE POLE


2/19/97 2/19/97 2/19/97 2/19/97 2/19/97 2/19/97 2/19/97 2/19/97 2/19/97 2/19/97 2/19/97 2/19/97 2/19/97 2/19/97 2/19/97 2/19/97 2/19/97 2/19/97 2/19/97 2/19/97 2/19/97 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 7.5 7.5 7.5 7.5 7.5 7.5 7.5 7.5 7.5 7.5 7.5 7.5 7.5 7.5 7.5 7.5 7.5 7.5 7.5 7.5 7.5 0.1016 0.1016 -0.1346 -0.1346 -0.1346 -0.1346 -0.1346 -0.1346 0.1016 0.1016 0.1016 0.1016 0.1016 0.1016 0.1016 -0.1346 -0.1346 -0.1346 -0.1346 -0.1346 -0.1346 145 145 -35 -35 -35 -35 -35 -35 145 145 145 145 145 145 145 -35 -35 -35 -35 -35 -35 -0.5686 -0.5686 0.4587 0.4587 0.4587 0.4587 0.4587 0.4587 -0.5686 -0.5686 -0.5686 -0.5686 -0.5686 -0.5686 -0.5686 0.4587 0.4587 0.4587 0.4587 0.4587 0.4587 12.2 12.2 12.2 12.2 12.2 12.2 12.2 12.2 12.2 12.2 12.2 12.2 12.2 12.2 12.2 12.2 12.2 12.2 12.2 12.2 12.2 0 1420 1420 0 0 1420 1420 1420 1420 1420 1420 0 0 1420 1420 0 0 1420 1420 1420 1420 UPPER UPPER UPPER UPPER UPPER UPPER UPPER UPPER UPPER UPPER UPPER UPPER UPPER UPPER UPPER UPPER UPPER UPPER UPPER UPPER UPPER DMP DMP DMP VALVE P2 VALVE P2 VALVE P2 VALVE P2 VALVE P2 VALVE P2 VALVE P2 VALVE P2 Family MP-Gnd Voltages DMP1-7 Family MP-Gnd Voltages DMP1-7 Family MP-Gnd Voltages DMP1-7 Family MP-Gnd Voltages Modules 2 - 8 Family MP-Gnd Voltages Modules 1 - 6 Family MP-Gnd Voltages Modules 1 - 6 Family MP-Gnd Voltages Modules 2 - 8 VAC, IAC & Current in VALVE P2 Family MP-Gnd Voltages Modules 1 - 6 Family MP-Gnd Voltages Modules 2 - 8 VAC, IAC & Current in VALVE P2

VALVE P1 Family MP-Gnd Voltages Modules 1 - 7 VALVE P1 Family MP-Gnd Voltages Modules 3 - 9 VALVE P1 Family MP-Gnd Voltages Modules 3 - 9 VALVE P1 Family MP-Gnd Voltages Modules 1 - 7 VALVE P1 Family MP-Gnd Voltages Modules 1 - 7 VALVE P1 Family MP-Gnd Voltages Modules 3 - 9 VALVE P1 Family MP-Gnd Voltages Modules 1 - 7 VALVE P1 Family MP-Gnd Voltages Modules 3 - 9 DCP STACK FAMILY Voltages to ground & half Clamp Cap amps FAMILY Voltages to ground & half Clamp Cap amps DCP STACK with One Wide Bandwidth PROBE.

2/14/97 2/14/97

90 90

-40 -40

14.5 14.5

1420 1770

LOWER LOWER

VALVE P1 VALVE P1

VALVE V & A FIRST TIME AT MAX.VOLTAGE VALVE V & A FIRST TIME AT MAX. DESIGN LIMIT

VOLTAGES APPEARING ACROSS GTO VALVES AND DIODE STACKS Operator Interface Inputs = 7.5 Corresponds to: Output V 0.997859 PU.V Output Current of Lower Pole Leads V by 90

= = =

145 12,300 V (EACH) 1,420 Arms

DC Voltages = AC Current =

Output Current of Upper Pole Lags V by 90

POLE

VALVE #

VALVE desciption OUTER POSITIVE INNER POSITIVE INNER NEGATIVE OUTER NEGATIVE MID-POINT STACK CLAMP CAPACITOR

rec# 13 3 2 11 3

From Ross Dividers Vpeak Vsettled 3.06 3.3 3.34 3.04 3.05 2.16 2.72 2.78 2.14 2.42

Actual Voltage Vpeak Vsettled 15,300 16,500 16,700 15,200 15,250 10,800 13,600 13,900 10,700 12,100

Percent of Vdc Vpeak Vsettled 124% 134% 136% 124% 124% 88% 111% 113% 87% 98%

Avg, V. Per Device Vpeak Vsettled 1,913 1,833 1,856 1,900 2,179 1,350 1,511 1,544 1,338 1,729

LOW ER P2 LOW ER P1 LOW ER N1 LOW ER N2 LOW ER LOW ER

UPPER UPPER UPPER UPPER UPPER UPPER

P2 P1 N1 N2

OUTER POSITIVE INNER POSITIVE INNER NEGATIVE OUTER NEGATIVE MID-POINT STACK CLAMP CAPACITOR

23 10 9 25

2.92 3.1 3.04 2.92

2.18 2.7 2.72 2.16

14,600 15,500 15,200 14,600

10,900 13,500 13,600 10,800

119% 126% 124% 119%

89% 110% 111% 88%

1,825 1,722 1,689 1,825

1,363 1,500 1,511 1,350

27 29

2.93 3.08 Operator Interface Inputs = 7.5

14,650 15,400

119% 125% Corresponds to: Output V 0.997859 PU.V Output Current of Lower Pole Leads V by -90

= = =

-35 12,300 V (EACH) 1,420 Arms

DC Voltages = AC Current =

Output Current of Upper Pole Lags V by -90

POLE

VALVE #

VALVE desciption OUTER POSITIVE INNER POSITIVE INNER NEGATIVE OUTER NEGATIVE MID-POINT STACK CLAMP CAPACITOR

rec# 15 5 6 17 5 9

From Ross Dividers Vpeak Vsettled 2.96 3.16 3.16 2.96 3.05 2.94 2.12 2.68 2.68 2.12 2.4 2.4

Actual Voltage Vpeak Vsettled 14,800 15,800 15,800 14,800 15,250 14,700 10,600 13,400 13,400 10,600 12,000 12,000

Percent of Vdc Vpeak Vsettled 120% 128% 128% 120% 124% 120% 86% 109% 109% 86% 98% 98%

Avg, V. Per Device Vpeak Vsettled 1,850 1,756 1,756 1,850 2,179 1,325 1,489 1,489 1,325 1,714

LOW ER P2 LOW ER P1 LOW ER N1 LOW ER N2 LOW ER LOW ER

UPPER UPPER UPPER UPPER UPPER UPPER

P2 P1 N1 N2

OUTER POSITIVE INNER POSITIVE INNER NEGATIVE OUTER NEGATIVE MID-POINT STACK CLAMP CAPACITOR

21 8 7 19

2.98 3.24 3.24 2.98

2.14 2.76 2.7 2.16

14,900 16,200 16,200 14,900

10,700 13,800 13,500 10,800

121% 132% 132% 121%

87% 112% 110% 88%

1,863 1,800 1,800 1,863

1,338 1,533 1,500 1,350

33 31

2.92 3.08

14,600 15,400

119% 125%

D
SAMPLE PRODUCTION POLE TEST REPORT
AEP Pole Testing - Poles # 5 & 6
1. Visually inspect pole for loose coolant piping, check component labels and connections etc. Connect glass fiber cables in the proper order to bottom of each pole electronics box (PEB). Disconnect power supply connections from pole electronics board (remove cover, lift leads on top right of board.) Check that DIP switch is set to 1 on top pole, 2 on bottom pole.. Test HF inverters, measure loop current (for magnitude and frequency) with a current gun or Rogowski coil. With gating disabled, check that all gates are reverse biased to 15V (K1 to G1 terminals). Expected range 14.90-15.40 volts. Measure power supply voltages for Pole Electronics Board ( 15 V, +5 V) at loose leads. Shut off HF inverters and re-connect Power Supply leads to PEB Connect Ross Dividers to positive side of lower pole Connect DC meter arrays to positive side of both poles Connect current sensor (Rogowski) to lower pole (A2) output

2.

3.

4.

5. 6. 7. 8. 9.

10. Connect Ross Dividers #6 To Pole A1 Output And #7 To Pole A2 Output 11. Turn on control and check pole A1 and A2 status indicators on Genesis display screens (with partial recovery detection only) 12. Use meter to check pin connections of "OSI" current sensor plugs: pin A-F= 15V; pin B-F = -15V; pin C-F = 10 for old style CT, 10 k for new style CT; pin -E 5.5 . 13. With gating disabled, turn on DC voltage sources to low level (3 kV) and check that voltage division (using digital meters) on GTOs and mid-diodes is good before increasing to maximum voltage of 12.2 kV. Record voltages across all GTO modules and midpoint diodes using pole mounted digital meters and Ross dividers with Fluke 8060A Meter. Need to move Ross dividers (V8 group) 4 times to record all mid-diodes. After moving DVM leads from POS to NEG side, raise DC volts to about 3 kV and check meters for uniformity to ensure meter leads are properly connected. Expect modules to be about 950 volts on

D-1

P2/N2 valves, and 460 volts on P1/N1 valves. Expect mid-diodes to read 120 mV using Fluke meter at the BNC panel. Check gate current for each module by attaching a Rogowski coil around each gate lead and observing waveform on a scope during the first turnon of gate signal. Check that gate current exists at the first turnon and that the current values are correct (70 A peak, 10 A average back-porch current. This test requires shutting down and restarting the gating for each module. Use a photodetector connected to a scope to check light throughput of fibers on any bad gate drive. Expect 50-120mV peak output when viewed on a scope.

Test 13 - POSITIVE SIDE = 3 kV


Range 240-250 volts A1P2 valve (range only) A2P2 valve (range only) A2DMP (30-35 mV) 244-249 242-254 32 A1P1 valve (range only) A2P1 valve (range only) Range 115-120 volts 117-119 119-121 -

NEGATIVE SIDE = 3 kV
Range 240-250 volts A1N2 valve (range only) A2N2 valve (range only) A2DMN (30-35 mV) 244-248 232-242 A1N1 valve (range only) A2N1 valve (range only) Range 115-120 volts 120-121 117-121 -

Test 13 - Positive Side DC = 12.2 kV


Module A1P21 A1P22 A1P23 A1P24 A1P25 A1P26 A1P27 A1P28 930-980V 975 969 969 968 961 962 956 958 Module A2P21 A2P22 A2P23 A2P24 A2P25 A2P26 A2P27 A2P28 930-980V 984 969 961 971 968 970 962 942 Module A1P11 A1P12 A1P13 A1P14 A1P15 A1P16 A1P17 A1P18 A1P19 450-470V 465 467 463 464 460 461 460 461 460 Module A2P11 A2P12 A2P13 A2P14 A2P15 A2P16 A2P17 A2P18 A2P19 450-470V 470 465 465 464 456 465 460 462 464

Ross Dividers at BNC Panel (5000:1 ratio)


Mid-Diode A2DMP1 A2DMP2 A2DMP3 A2DMP4 A2DMP5 A2DMP6 A2DMP7 (top) 120-125 mV 121 121 119 121 121 120 121 Mid-Diode A1DMP1 A1DMP2 A1DMP3 A1DMP4 A1DMP5 A1DMP6 A1DMP7 (top) 120-125 mV 118 119 118 119 119 118 119

NEGATIVE SIDE - DC = 12.2 kV


Module A1N21 A1N22 A1N23 A1N24 A1N25 A1N26 A1N27 A1N28 930-980V 963 970 970 971 975 977 975 983 Module A2N21 A2N22 A2N23 A2N24 A2N25 A2N26 A2N27 A2N28 930-980V 930 956 964 963 965 953 951 935 Module A1N11 A1N12 A1N13 A1N14 A1N15 A1N16 A1N17 A1N18 A1N19 450-470V 462 463 462 461 462 463 464 465 464 Module A2N11 A2N12 A2N13 A2N14 A2N15 A2N16 A2N17 A2N18 A2N19 450-470V 462 462 458 464 454 463 465 464 469

Ross Dividers at BNC Panel (5000:1 ratio) Mid-Diode A2DMN1 A2DMN2 A2DMN3 A2DMN4 A2DMN5 A2DMN6 A2DMN7 (top) 120-125 mV 118 120 120 121 121 121 121 Mid-Diode A1DMN1 A1DMN2 A1DMN3 A1DMN4 A1DMN5 A1DMN6 A1DMN7 (top) 120-125 mV 121 121 120 120 121 120 121

14/ ***Set To 90, enable gating; raise DC Voltage slowly while checking static and dynamic voltage distribution using pole mounted digital meters and Ross Dividers with Tektronix DS602A Digital Waveform Analyzer and Fluke 8060A meter. (This test requires shutting off the power and reconnecting digital meters and Ross dividers to check voltages across ALL Modules And MidPoint Diodes). Move digital meter leads 1 times, Ross dividers 3 times.

Test 14 - NEGATIVE SIDE - Digital Meters DC = 12.2 kV


Module 10801150V 1117 1110 1137 1132 1143 1118 1124 1160 Module 1080-1150V Module 350-390V Module 350-390V

A1N21 A1N22 A1N23 A1N24 A1N25 A1N26 A1N27 A1N28

A2N21 A2N22 A2N23 A2N24 A2N25 A2N26 A2N27 A2N28

1085 1094 1104 1128 1120 1091 1087 1103

A1N11 A1N12 A1N13 A1N14 A1N15 A1N16 A1N17 A1N18 A1N19

371 380 374 370 375 372 380 373 382

A2N11 A2N12 A2N13 A2N14 A2N15 A2N16 A2N17 A2N18 A2N19

375 381 370 371 374 373 379 380 384

Ross Dividers at BNC Panel (5000:1 ratio)


Mid-Diode A2DMN1 A2DMN2 A2DMN3 A2DMN4 A2DMN5 A2DMN6 A2DMN7 (top) 94-98 mV 95.04 95.14 94.76 95.88 96.52 95.19 95.67 Mid-Diode A1DMN1 A1DMN2 A1DMN3 A1DMN4 A1DMN5 A1DMN6 A1DMN7 (top) 94-98 mV 94.66 94.7 94.49 95.12 96.3 95.5 96.1

POSITIVE SIDE - Digital Meters DC = 12.2 kV


Module A1P21 A1P22 A1P23 A1P24 A1P25 A1P26 A1P27 A1P28 1080-1150V 1120 1105 1100 1099 1094 1113 1108 1092 Module A2P21 A2P22 A2P23 A2P24 A2P25 A2P26 A2P27 A2P28 1080-1150V 1115 1104 1106 1095 1098 1115 1113 1093 Module A1P11 A1P12 A1P13 A1P14 A1P15 A1P16 A1P17 A1P18 A1P19 350-390V 350 365 367 365 371 368 361 368 367 Module A2P11 A2P12 A2P13 A2P14 A2P15 A2P16 A2P17 A2P18 A2P19 350-390V 367 367 368 357 359 370 365 365 352

Ross Dividers at BNC Panel (5000:1 ratio)


Mid-Diode A2DMP1 A2DMP2 A2DMP3 A2DMP4 A2DMP5 A2DMP6 A2DMP7 (top) 94-98 mV 95.4 95.99 95.8 95.7 97.2 96.2 95.02 Mid-Diode A1DMP1 A1DMP2 A1DMP3 A1DMP4 A1DMP5 A1DMP6 A1DMP7 (top) 94-98 mV 95.12 97.59 94.00 95.98 96.27 94.79 95.32

15/

Connect pole outputs to current source (install 2 cables)

16/

Set current to 2,500A peak and observe conduction voltage drops across all modules and mid point diodes with an oscilloscope:

(1) (2) (3)

Uppers On Mids On Lowers On

(check P2, P1 only, no diode measurements) (use scope to look at diodes; P1 & N1 are on) (check N1, N2 only, no diode measurements)

Use long leads and insulated probes, connect to Scope to measure waveforms. Measured 3.2-3.6 volts for GTOs; < 2 volts for D1 diodes; 1.9-2.3 volts for Mid-diodes. GTO and D1 are measured on the same waveform - one is positive and the other is the negative going part of the waveform.

17/

Maintain Current At 2,500 A peak, and with water flow set at the minimum rate, measure temperatures of heat sinks and temperature rise (with handheld meter) on all components for each of the three continuous current paths. (1) Uppers On (2) (3) Mids On Lowers On

18/ *** Set To 7.5 To 145 To 0.1621 (Mitsu)/ 0.1071 (Tosh) To -0.4697 (Mitsu)/ -0.4807 (Toshiba). Set DC power supplies to 12.2 KV; Current to 1768 Arms Record peak and settled voltage across all GTO valves and mid-point diode stacks. Use 2 Ross dividers across a valve with 5000:1 ratio. Measure voltage at panel in control room.

Ross Dividers at BNC Panel (5000:1 ratio)


Valve A1N1 A2N1 A2N2 A1N2 A2P2 A1P2 A2P1 A1P1 Vpeak 3.18 (= 15.9 kV) 3.34 3.14 3.00 3.20 3.02 3.28 3.24 V 2.4 2.38 2.42 2.40 Vsteady 2.70 2.72 2.10 2.12 2.12 2.12 2.70 2.70

19/ *** Set To 7.5 To -35 to -0.1621 (Mitsu)/ -0.1071 (Tosh) to 0.4697 (Mitsu)/ -0.4807 (Toshiba). Set DC Supplies To 12.2 KV; Current to 1768 Arms Record peak and settled voltages across all GTO valves, midpoint and clamp diode stacks. Use 2 Ross dividers across a valve with 5000:1 ratio. Measure voltage at panel in control room. Ross Dividers at BNC Panel (5000:1 ratio)
Valve A1N1 A2N1 A2N2 A1N2 A2P2 A1P2 A2P1 A1P1 Vpeak 3.20 3.28 3.04 3.14 3.06 3.16 3.30 3.24 V 2.40 2.40 2.40 2.36 Vsteady 2.70 2.72 2.10 2.12 2.10 2.14 2.70 2.70

20/ *** Record maximum temperatures of all stickered components

All GTO and D1 diode temperature labels are < 71 C. One GTO has a lower label that shows = 54 C. o o o A2DMP4 mid-diode = 82 C. A2DCP (clamp diode) aluminum plates = 93 C, and 0.68 uF = 48 C. 21/ *** Perform 8-Hour Heat Run and Record A1 Delay Values:

Set to 7.5

to -35 to 0.4697 (Mitsu)/ 0.4807 (Toshiba).

to -0.1621 (Mitsu)/ -0.1071 (Tosh) Set DC Supplies To 14.5 kV;

Current to 1768 Arms. Run for 8 hours.

Reduce DC to 12.2 KV, and record actual delays for upper pole (A1). Print screen, AND save to disk as C:\poletest\dat\POLxxDEL.DAT, where xx is the pole number. See typical current and voltage waveform See delay values in screen printout..

22/

Print out scope waveforms of pole voltage and current for record, check STATUS, Record max temperatures of all stickered components. All GTO and D1 diode temperature labels show no change. A2DCP (clamp diode) aluminum o o o heat sinks = 77 C, and 0.68 uF = 64 C. Clamp capacitor case = 38.5 C

23/ *** Perform second 8-Hour Heat Run and Record A2 Delay Values:

Set to 7.5

to 145 to -0.4697 (Mitsu)/ -0.4807 (Toshiba).

to 0.1621 (Mitsu)/ 0.1071 (Tosh) Set DC Supplies To 14.5 kV;

Current to 1768 Arms. Run for 8 hours.

Reduce DC to 12.2 KV, and record actual delays for Lower Pole (A2). Print screen, AND save to disk as C:\poletest\dat\POLxxDEL.DAT, where xx is the pole number. See typical current and voltage waveforms. See delay values in screen printout.

24/

Print out scope waveforms of pole voltage and current for record, check STATUS, Record max temperatures of all stickered components. All GTO and D1 diode temperature labels show no change. A2DCP (clamp diode) aluminum o o o heat sinks > 104 C, and A1 0.68 uF = 54.1 C, A2 0.68 uF = 38.5 C.

25/

Test all clamp capacitor monitors by paralleling 1.5F capacitor. Make sure that cross buses are connected between 5 uF capacitors for lower inductance. Requires 4 measurements altogether. Capacitor monitor should show FAILURE at or below 12 kV without current in the pole. All 4 capacitor error signals came up at 9 to 12 kV.

26/ *** Measure AC And DC input power (record PVT kW; DC supply A and B currents on Fluke meters on second floor) using angle settings: (1) DCV = 12.2KV ; AC output = 2000A PEAK = 7.5; = 145

= 0.1621 (Mitsu)/ 0.1071 (Tosh)

= -0.4697 (Mitsu)/ -0.4807 (Toshiba).

Measured Peschel Tranformer (PVT) = 124 kW. DC power supplies current = +3.035 amps, -3.075 amps. (2) DCV = 12.2KV ; AC output = 2000A PEAK = 7.5; = -35

= -0.1621 (Mitsu)/ -0.1071 (Tosh)

= 0.4697 (Mitsu)/ 0.4807 (Toshiba).

Measured Peschel Tranformer (PVT) = 132 kW. DC power supplies current = +2.80 amps, -2.73 amps. (3) = 7.5 DCV = 12.2KV = -35 ; AC output = ZERO = 0.0 = 0.0

Measured Peschel Tranformer (PVT) = 0 kW. DC power supplies current = +2.78 amps, -2.755 amps.

27/

Emergency Turn-Off At 3000A Peak Current. Connect P5100 probe to A2 PE box BNC #2; run to optical transmitter and back to 744 scope. Use 5:1 gain on receiver, set scope to 50 mV/div. Compare this signal to the ac current output (pole A2) from Rogowski coil. A2 pin #2 should look identical to current; Reconnect to A1 P.E. box. A1 o pin #2 will be 180 out of phase, but equal magnitude, to the pole output current. In the control rack, adjust pot R28 to reduce voltage on test point 49 to 2.4 volts, down from 3.1 volts. DC Voltages are off. Gradually increase the AC current to 3000A peak, where current will be repeatedly interrupted as the DC Voltages are pumped up and gating is inhibited. Be certain to RESET the voltage to 3.1 at test point 49 after the test is complete. Do this for each of the following firing modes. No DC voltage. Display current on 744 scope.

(1) (2) (3)

With Uppers On With Mids On With Lowers On

Use Graphtec recorder at -10%, STANDARD paper length. See traces. DC voltages increase from 0 to approximately 14 kV when the current is interrupted. *** Full recovery detection should be enabled during all switching mode tests after the DC voltage has been raised above 6 KV

and may require a different setting for each pair of poles. 4/30/97

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