AN INTRODUCTION TO INTERRUPTS

INTERRUPTS There are two main types of interrupt in the 8086 microprocessor, internal and external hardware interrupts. Hardware interrupts occur when a peripheral device asserts an interrupt input pin of the microprocessor. Whereas internal interrupts are initiated by the state of the C ! "e.#. divide by $ero error% or by an instruction. rovided the interrupt is permitted, it will be ac&nowled#ed by the processor at the end of the current memory cycle. The processor then services the interrupt by branchin# to a special service routine written to handle that particular interrupt. !pon servicin# the device, the processor is then instructed to continue with what is was doin# previously by use of the 'return from interrupt' instruction. The status of the pro#ramme bein# executed must first be saved. The processors re#isters will be saved on the stac&, or, at very least, the pro#ramme counter will be saved. reservin# those re#isters which are not saved will be the responsibility of the interrupt service routine. (nce the pro#ramme counter has been saved, the processor will branch to the address of the service routine. Edge or Level sensitive Interrupts )d#e level interrupts are reco#nised on the fallin# or risin# ed#e of the input si#nal. They are #enerally used for hi#h priority interrupts and are latched internally inside the processor. *f this latchin# was not done, the processor could easily miss the fallin# ed#e "due to its short duration% and thus not respond to the interrupt re+uest. ,evel sensitive interrupts overcome the problem of latchin#, in that the re+uestin# device holds the interrupt line at a specified lo#ic state "normally lo#ic $ero% till the processor ac&nowled#es the interrupt. This type of interrupt can be shared by other devices in a wired -(.- confi#uration, which is commonly used to support daisy chainin# and other techni+ues. Maskable Interrupts The processor can inhibit certain types of interrupts by use of a special interrupt mas& bit. This mas& bit is part of the fla#s/condition code re#ister, or a special interrupt re#ister. *n the 8086 microprocessor if this bit is clear, and an interrupt re+uest occurs on the *nterrupt .e+uest input, it is i#nored. Non Maskable Interrupts There are some interrupts which cannot be mas&ed out or i#nored by the processor. These are associated with hi#h priority tas&s which cannot be i#nored "li&e memory

parity or bus faults%. *n #eneral, most processors support the 0on12as&able *nterrupt "02*%. This interrupt has absolute priority, and when it occurs, the processor will finish the current memory cycle, then branch to a special routine written to handle the interrupt re+uest. Advantages o! Interrupts *nterrupts are used to ensure ade+uate service response times by the processin#. 3ometimes, with software pollin# routines, service times by the processor cannot be #uaranteed, and data may be lost. The use of interrupts #uarantees that the processor will service the re+uest within a specified time period, reducin# the li&elihood of lost data. Interrupt Laten"# The time interval from when the interrupt is first asserted to the time the C ! reco#nises it. This will depend much upon whether interrupts are disabled, prioriti$ed and what the processor is currently executin#. 4t times, a processor mi#ht i#nore re+uests whilst executin# some indivisible instruction stream "read1write1modify cycle%. The fi#ure that matters most is the lon#est possible interrupt latency time. Interrupt Response Ti$e The time interval between the C ! reco#nisin# the interrupt to the time when the first instruction of the interrupt service routine is executed. This is determined by the processor architecture and cloc& speed.

T%e Operation o! an Interrupt se&uen"e on t%e '(') Mi"ropro"essor*

5. )xternal interface sends an interrupt si#nal, to the *nterrupt .e+uest "*0T.% pin, or an internal interrupt occurs. 6. The C ! finishes the present instruction "for a hardware interrupt% and sends *nterrupt 4c&nowled#e "*0T4% to hardware interface. 7. The interrupt type 0 is sent to the Central rocessor !nit "C !% via the 8ata bus from the hardware interface. 9. The contents of the fla# re#isters are pushed onto the stac&. :. ;oth the interrupt "*<% and "T<% fla#s are cleared. This disables the *0T. pin and the trap or sin#le1step feature.

6. The contents of the code se#ment re#ister "C3% are pushed onto the 3tac&. =. The contents of the instruction pointer "* % are pushed onto the 3tac&. 8. The interrupt vector contents are fetched, from "9 x 0% and then placed into the * and from "9 x 0 >6% into the C3 so that the next instruction executes at the interrupt service procedure addressed by the interrupt vector. ?. While returnin# from the interrupt1service routine by the *nterrupt .eturn "*.)T% instruction, the * , C3 and <la# re#isters are popped from the 3tac& and return to their state prior to the interrupt.

Multiple Interrupts
*f more than one device is connected to the interrupt line, the processor needs to &now to which device service routine it should branch to. The identification of the device re+uestin# service can be done in either hardware or software, or a combination of both. The three main methods are@ 5. 3oftware ollin#, 6. Hardware ollin#, "8aisy Chain%, 7. Hardware *dentification "Aectored *nterrupts%.

So!t+are Polling Deter$ination o! t%e Re&uesting Devi"e

4 software routine is used to identify the device re+uestin# service. 4 simple pollin# techni+ue is used, each device is chec&ed to see if it was the one needin# service.

Havin# identified the device, the processor then branches to the appropriate interrupt1 handlin#1routine address for the #iven device. The order in which the devices appear in the pollin# se+uence determines their priority.

Su$$ar# o! So!t+are Polled I,O

ollin# is the most common and simplest method of */( control. *t re+uires no special hardware and all */( transfers are controlled by the C ! pro#ramme. ollin# is a synchronous mechanism, by which devices are serviced in se+uential order. The pollin# techni+ue, however, has limitations. 5% it is wasteful of the processors time, as it needlessly chec&s the status of all devices all the time, 6% it is inherently slow, as it chec&s the status of all */( devices before it comes bac& to chec& any #iven one a#ain, 7% when fast devices are connected to a system, pollin# may simply not be fast enou#h to satisfy the minimum service re+uirements, 9% priority of the device is determined by the order in the pollin# loop, but it is possible to chan#e it via software.

So!t+are,-ard+are Driven Identi!i"ation .Dais# C%ain/

This is si#nificantly faster than a pure software approach. 4 daisy chain is used to identify the device re+uestin# service.

Daisy Chain Polling Arangement

8aisy chainin# is used for level sensitive interrupts, which act li&e a wired -(.- #ate. 4ny re+uestin# device can ta&e the interrupt line low, and &eep it asserted low until it is serviced. ;ecause more than one device can assert the shared interrupt line simultaneously, some method must be employed to ensure device priority. This is done usin# the interrupt ac&nowled#e si#nal #enerated by the processor in response to an interrupt re+uest. )ach device is connected to the same interrupt re+uest line, but the interrupt ac&nowled#e line is passed throu#h each device, from the hi#hest priority device first, to the lowest priority device last.

4fter preservin# the re+uired re#isters, the microprocessor #enerates an interrupt ac&nowled#e si#nal. This is #ated throu#h each device. *f device 5 #enerated the interrupt, it will place its identification si#nal on the data bus, which is read by the processor, and used to #enerate the address of the interrupt1service routine. *f device 5 did not re+uest the servicin#, it will pass the interrupt ac&nowled#e si#nal on to the next device in the chain. 8evice 6 follows the same procedure, and so on.

-ard+are Identi!i"ation .0e"tored Interrupts/

This is the fastest system. The onus is placed on the re+uestin# device to re+uest the interrupt, and identify itself. The identity could be a branchin# address for the desired interrupt1handlin# routine. *f the device Bust supplies an identification number, this can be used in conBunction with a loo&up table to determine the address of the re+uired service routine. .esponse time is best when the device re+uestin# service also supplies a branchin# address.

Priority Interrupt Management Controller riority *nterrupt Controller Chips " *C-s% are hardware chips desi#ned to ma&e the tas& of a device presentin# its own address to the C ! simple. The *C also assesses the priority of the devices connected to it. 2odern *C-s can also be pro#rammed to prevent the #eneration of interrupts which are lower than a desired level. The decoded location is connected to the output of a priority encoder. The input of priority encoder is connected to each device. When a device re+uests service, priority encoder presents a special code combination "uni+ue for each device% to decoded memory location. The port thus holds the value or address associated with hi#hest device re+uestin# service. the the the the

The priority encoder arran#es all devices in a list, devices #iven a lower priority are serviced when no other hi#her priority devices need servicin#. This simplifies the software re+uired to determine the device, resultin# in an increase in speed. T%e disadvantages are* 5% 6% 7% 9% the extra chip re+uired, resultant increases in cost, more board space and power consumption, fixed priority in hardware.