Lenovo E420 analysis, Wistron OEM, HM65 chipset. Protective isolation conduction conditions.

BQ24745 satisfied as long as the main power supply 22 feet, 2 feet AC_IN thresh old 17.6V, large internal 2.4V. 13 feet ACOK internal MOS transistor will be high impedance, 3-pin output 3.3V reference voltage provided pullups. Common point voltage is generated DCBATOUT. 3.3V and 5V system standby chip BD95280. BD95280 30 feet to the main power supply will be from 28 feet out after a 3.3V linear voltage PWR_5V3D3V_VREG2 And 5V linear voltage PWR_5V3D3V_VREG1, through PG4119, G9306 in order to conve rt 3D3V_PWR_2 and 5V_PWR_2 This board 5V_PWR_2 suspended only for the chip to 3 feet and 22 feet to provid e the BOOT voltage of 4.7V. 3D3V_PWR_2 convert 3D3V_AUX_S5 by PR4122 3D3V_AUX_S5 convert RTC_AUX_S5 through Q6001 replace the RTC battery. Provide the PCH RTC circuit provides power and 32.768KHZ clock. 3D3V_AUX_S5 another way to convert 3D3V_AUX_KBC, primarily to provide power for the EC and the reference voltage. Powered BAT_IN # LID_CLOSE # AC_IN_KBC EC_RST 4 have a high level signal, this machine in the boot BIOS chip. EC are met within the given S5_ENABLE converted through a resistor R3603 3V_5V_ EN As BD95280 2 feet and 21 feet as the opening of 3.3V and 5V signal. Thus BD95280 will produce 3V_PWR and 5V_PWR voltage is converted to 3D3V_S5 fol lowed by jumpers and 5V_S5 This 2-powered role and the PCH V5REF_Sus (PCH Southbridge internal power supply, this voltage is not normal, r esulting in full-board USB can not be used) VCCSUS3_3 (VccSus3_3 normal PLTRST # This signal only works) When the 3.3V and 5V normal, BD95280 issue 3V_5V_POK sent pQ1901 The cut-off on the pQ1901 produce PM_RSMRST # sent to the PCH E22 point (this s ignal with EC issued, 3V_5V_POK not generated on the front pQ1901 conduction to this signal low) PCH received PM_RSMRST # issued after SUS_CLK (32.768kZH) to the EC 77 feet to turn the clock EC EC on the clock, power, reset all OK premise issue AC_PRESENT (AC adapter into normal) to PCH Shorting the EC 93 feet KBC_PWRBTN_EC # and GND release, rising edge triggered, EC issued PM_PWRBTN # (rising edge active) to PCH PCH received the EC PM_PWRBTN # start signal, the first issue to the EC SLP_S4 # 21 feet the other way SLP_S4 # sent to PU4601 3 feet as memory, open signal to produce 1D5V_S3 Issuing SLP_S3 #, this signal is converted into the 5V_S0 3D3V_S5 1D5V_S0 5V_S5 3D3V_S0 converted into 1D5V_S3 SLP_S3 # Q3606 makes the cut-off all the way to the role and produce PS_S3CNTRL , PS_S3CNTRL role and Q3704 Makes Q3704 cutoff produce 0D75V_EN. 0D75V_EN normal high after the SLP_S4 # simultaneously sent to PU4604 as a turn -on signal, such that the resulting 0D75V_S0 (memory termination voltage) SLP_S3 # PU4701 role and another way of a pin as open signal, 1D5V_S3 and 1D8V_ S0 supply are normal issued RUNPWROK. RUNPWROK sent to PCH, inform RUN series power supply are normal. RUNPWROK another road and P *** P_S3 # phase as a turn-on signal is sent to the U3609, resulting PWR_1D05V_EN PWR_1D05V_EN and turn signals with RUNPWROK role and PU4501 as 3 feet, producin g 1D05V_VTT When the power supply is normal 1D05V_VTT issued after 1.05VTT_PWRGD 1.05VTT_PWRGD role and PU4801 of 15 feet as a turn-on signal, generating VCCSA_

PWR (0.85v) VCCSA_PWR normally issued after D85V_PWRGD to PCH, D85V_PWRGD another way to PU 4201 9 feet, as the CPU turn signal. PU4201 CPU on received signal, the output H_CPU_SVIDDAT (data) H_CPU_SVIDCLK (clock) H_CPU_SVIDDAT and H_CPU_SVIDCLK main communication with the CPU VID similar ide ntification. After decoding will return pu4201 PU4201 get decoded message is generated after the CPU power VCC_CORE and VCC_GF XCORE (CPU internal set of significant supply) VR_SVID_ALERT # (thermal alarm active low) (This signal is directly connected t o CPU, effective after, PU4201 will reduce CPU clock speed) CPU power supply to normal after PU4201 7 feet issued IMVP_PWRGD, another IMVP_ PWRGD normal PCH issue CLK_EXP_P and CLK_EXP_N CPU master clock, and motherboard desired clock frequency (this board internal clock chip integration and PCH) EC issued from 84 feet S0_PWR_GOOD, this signal is delayed by 200 ms in SLP_S3 # will be issued after normal. S0_PWR_GOOD and D85V_PWRGD are normally generated after PWROK. IMVP_PWRGD ANDed with S0_PWR_GOOD produce SYS_PWROK to PCH through U3603 PCH PCH received internally ANDed with PWROK and issued PM_DRAM_PWRGD PM_DRAM_PWRGD and 0D75V_EN phase to the CPU via U3701 produce VDDPWRGOOD After receiving VDDPWRGOOD CPU, PCH also issued to the CPU H_CPUPWRGD PCH issue PLT_RST reset CPU, EC, reader. PCH modules within the North Bridge. PCH internal Northbridge module is reset, PCH issued in a valid DGPU_PWR_EN # DGPU_PWR_EN # make Q9305 off, resulting DGPU_PWR_EN left the Q9301 Q9301 MOS is the right half of the G tube cutoff low Q9302 Q9302 conduction electrode potent ial makes the 3D3V_S0 into 3D3V_VGA_S0 as independence was VDDQ supply Makes the D9101 and D9201 DGPU_PWR_EN role in the off-state generator 8209A_EN/ DEM_VGA 8209A_EN/DEM_VGA as PU9201 opening signal such that the resulting VGA_CORE_PWR (independence was the main power supply) VGA_CORE_PWR normal PU9201 issue PWR_VGA_CORE_PGOOD through R9214 into DGPU_PWR OK (powered with R9213 and C9212 RC delay provided) DGPU_PWROK convert 1D5V_VGA_PWOK_R through R8601 DGPU_PWR_EN DGPU_PWROK as U9302 turn-signal generating 1V_VGA_S0 1V_VGA_S0 normally issued after 9025_PGOOD_1V, 8209A_EN/DEM_VGA 9025_PGOOD_1V DGPU_PWR_EN 3 group roles and Q9304 high signal In the conduction state so Q9304, Q9303, G low electrode potential, so that the RUN_ENABLE Q9303 into conduction RUNON_R_1, RUNON_R_1 voltage is 20V, so U9301 is turned into the 1D5V_S3 1D5V_VGA_S0 9025_PGOOD_1V and DGPU_PWR_EN as U9303 turn-signal generating 1D8V_LDO_VGA, whe n 1D8V_LDO_VGA normal U9303 issued 1D8V_S0_VGA_PG. Thus significant independence and memory have all the required electricity generation. 1D5V_VGA_PWOK 1D8V_S0_VGA_PG PLT_RST # 3 set of high-level signal phase generat ed through U8301 VGA_RST # Finally there VGA_RST # Reset significant independence.