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# The Communications Edge ™

Tech-note
Author: Stephan R. Kurtz

## Mixers as Phase Detectors

Most systems which require phase informa- alternate conduction, causing the ends of the where
tion use mixers somewhere in the measure- RF transformer’s secondary winding (B and ωL ≡ frequency of the LO signal
ment or comparison of the phase informa- C) to be alternately at ground potential, ΦL ≡ phase angle of the LO signal
tion. Theoretically, any mixer with a dc cou- switching at a rate equal to the frequency of j ≡ √-1
pled port could be used as a phase detector. the input signal to the LO port. The instan- gn ≡ constants.
Practically, however, mixers often display taneous voltage at the IF port is determined
Applying an RF signal, the small signal volt-
some very non-ideal characteristics (e.g., dc by: 1) the level and polarity of the instanta-
offset) when used as phase detectors. The age across the diode is VRF (ωRt + ΦR),
neous voltage at the RF transformer’ s sec-
actual mixer chosen for a particular applica- ondary winding; and 2) which terminal of which results in a diode current waveform of
tion will often depend on the degree to the secondary is at ground potential at that iD = G(ωLt + ΦL) VRF (ωRt + ΦR) (2)
which these non-ideal characteristics can instant. The output at the IF port contains
be tolerated. If VRF is expressed as
the sum and difference of the frequencies of ∞
the signals input to the LO and RF ports. VRF (ωRt + ΦR) = Σ νm exp (j(m(ωRt + ΦR)))
This article discusses the general theory m = -∞
behind the use of mixers as phase detectors; If the RF and LO signals have identical fre- (3)
the origin of some of the various non-ideal quencies, then their difference is zero Hz, or
then combining equations (1), (2), and
characteristics and how they can be mini- dc, which is the desired output for a phase
(3) yields
mized; some of the factors affecting phase detector. Their sum, which is twice the input ∞
detector response; and finally, some general frequency, can be selectively filtered out if it iD = Σ gn νm exp (j(n(ωLt + ΦL)
is not already beyond the frequency response n, m = -∞
guidelines to be considered when picking a + m(ωRt + ΦR))) (4)
mixer for a phase detector application. of the IF port.
In a four-diode ring mixer as shown in
HOW PHASE DETECTORS MATHEMATICAL DESCRIPTION Figure 1, the total current seen at the
WORK In order to demonstrate mixer operation IF port is given by
The basic concept upon which phase detec- mathematically, we need to first look at the IIF = 1/2 (iD2 - iD1 + iD4 - iD3) (5)
tion rests is that the application of two iden- mixing process as it occurs in each diode.
The conductance waveform for the diode where iDj is the current flowing through
tical frequency, constant amplitude signals to
can be expressed in terms of the local oscilla- diode j.
a mixer results in a dc output which is pro-
portional to the phase difference between tor frequency and its phase angle as shown Combining equations (4) and (5) gives
the two signals. While it is true that even a below:2 ∞
∞ IIF = -Σ 2gn νm exp (j(n(ωLt + ΦL)
single diode can be used as a mixer, most n, m
G(ωLt + ΦL) = Σ gn exp (j(n(ωLt+ ΦL))) (1)
phase detectors involve the use of double n = -∞ + m(ωRt + ΦR))) (6)
balanced mixers (for reasons to be discussed
later). With this in mind, the theory present-
ed here assumes that a double balanced
mixer is being used. Figure 1 is a schematic RF

## of a typical double balanced, four-diode

LO iD4
ring mixer. A iD1

D4 D1
The voltage at the secondary of the LO B C
transformer causes currents to flow through D3 D2 IF
diode pair D1, D2 or D3, D4, depending iD3
D iD2
on polarity. The DC voltage at B or C is RL

## held at virtual ground potential by the volt-

age divider action of the conducting diode
pair. The diode pairs (D1, D2 and D3 D4) Figure 1. A typical double balanced four-diode ring mixer.

WJ Communications, Inc. • 401 River Oaks Parkway • San Jose, CA 95134-1918 • Phone: 1-800-WJ1-4401 • Fax: 408-577-6620 • e-mail: sales@wj.com • Web site: www.wj.com
The Communications Edge ™
Tech-note
Author: Stephan R. Kurtz

where n, m = all odd integers. It is in this pseudo-linear response region response region, phase detector sensitivity
that the sensitivity of the phase detector to varies linearly with maximum output voltage.
All terms in equation (6) other than those
changes in ∆Φ (i.e., dVIF/d∆Φ) is maxi-
for n × m = -1 represent unwanted inter- The question now remaining is: What
mum. However, as seen in Figure 2, the
modulation products and must be filtered exactly is the range of linear response, i.e.,
actual value of this maximum sensitivity is
out if not already sufficiently attenuated by what is ∆Φ? Of course, VIF and V2 are
strongly affected by changes in the maxi-
the frequency response of the IF port. never exactly equal except at ∆Φ = π/2, and
mum voltages seen at ∆Φ equal to 0 or π.
so the response is only approximately linear.
In a phase detection application ωL is equal
Assume that the phase detector output is Thus, the above question should more cor-
to ωR which results in a current at the IF port
described by rectly be: What is the range around
(looking only at the n × m = - 1 terms) of
∆Φ = π/2 that the percentage deviation of
VIF = V cos (∆Φ + π) (10)
I = -2g ν ± exp (j(n(±ω t ± ω )). (7)
IF ±1 R1 L R VIF from linearity will be less than or equal
where V is the amplitude of the maximum to d, where
Assuming a load resistance R, if we rewrite
voltage seen at ∆Φ = 0 or π. Now superim- V -V
the exponential in equation (7) in trigono- pose a straight line on top of VIF which pass- (
d = 2 IF 100.
V2 ) (13)
metric form, keeping only the real part, the es through the point (π/2, 0) i.e., Substituting equations (10) and (12) into
result is
V2 = A (∆Φ - π/2). (11) (13) and evaluating at
V = -2Rg ν ± cos (±Φ ± Φ ) (8)
IF ±1 R1 L R
In order for V2 to be approximately equal to ∆Φ = π/2 + δΦ*
or VIF over the linear response region, it must results in
VIF = -2Rg±1 νR±1 cos (∆Φ + π) (9) follow that the slope of VIF and V2 are equal
at ∆Φ = π/2. Thus, equation (11) can be
d= ( δΦ -δΦsin δΦ ) 100. (14)
which indicates that the voltage at the IF port rewritten as
will be dc and will vary as the cosine of the If we now expand sin (( in a power series
phase difference between the LO and RF sig- V2 = V (∆Φ - π/2) (12) and keep only the first two terms in the
nals. Null readings for VIF are thus obtained series, we get
which indicates that within the linear
δΦ2
whenever the phase difference ∆Φ between
the LO and RF signals is equal to nπ/2 with
d=
3! ( )
100. (15a)
or
n = ±1, ±3, ..., while maximum and mini-
6d
mum readings are obtained for ∆Φ = nπ
where n = 0, ±1, ±2, ...
2 δΦ =

100
(15b)

## where δΦ is in radians. Figure 3 plots equa-

PEAK OUTPUT, SENSITIVITY,
tion (15a) versus both δΦ and ∆Φ. The
AND LINEARITY 1
VIF - DIMENSIONLESS UNITS

## range of linear response is thus seen to

Figure 2 shows VIF varying as the cosine of depend on how much deviation from lin-
the phase difference ∆Φ between the LO and δφ
earity can be tolerated. For example, if a
RF signals, with maximum negative voltages 0 π π 3π π 10% deviation from linearity can be tolerat-
occuring at ∆Φ = 0 and maximum positive 4 2 4 ed, then the linear response region will
voltages occuring at ∆Φ = π. While that is the δφ
extend approximately from ∆Φ = 45° to
most common form of phase detector output, ∆φ - RADIANS
135°; i.e., δΦ = ±45°.
it is also possible to obtain maximum positive -1

## voltages at ∆Φ = 0 and maximum negative NONIDEAL CHARACTERISTICS

voltages at ∆Φ = π by means of relatively
The theory presented in the previous sec-
minor internal wiring changes to the mixer.
-2 tion assumed an “ideal” mixer, i.e., the cir-
The response of VIF to changes in ∆Φ is fair- cuit was perfectly balanced. However, this is
ly linear over the region in phase space corre- often not possible or practicable, with the
Figure 2. Typical phase detector response curve varies
sponding to as cos (∆Φ + π). Detector response is fairly linear over
∆Φ = π/2 + δΦ. Detector sensitivity increases as maxi- *Evaluation at ∆Φ = π/2 - δΦ would simply
∆Φ = π/2 + δΦ. mum VIF increases. result in a value of -d.

WJ Communications, Inc. • 401 River Oaks Parkway • San Jose, CA 95134-1918 • Phone: 1-800-WJ1-4401 • Fax: 408-577-6620 • e-mail: sales@wj.com • Web site: www.wj.com
The Communications Edge ™
Tech-note
Author: Stephan R. Kurtz

result that when practical mixers are used as case for which only the LO signal is applied that now the LO transformer is not perfectly
phase detectors they often display some to the mixer. If the LO transformer is per- symmetrical with respect to the center tap.
characteristics which differ from those of fectly symmetrical on either side of the cen- Satisfying equation (16) only guarantees that
idealized mixers. ter tap, then at any instant in time, the volt- the voltage at B is the same as that at C.
age VLO at point A is exactly equal in mag- However, it does not guarantee that the volt-
The characteristics of most interest are dc
nitude (although opposite in polarity) to age at B and C is equal to that at the center
offset and/or mixer-induced phase shift of
that applied at point D (see Figure 1). The tap of the LO transformer. Suppose that the
the signals due to circuit imbalance. The
voltage drop from B to C, and, consequent- transformer is asymmetrically wound so that
design engineer is interested in how these
ly, the voltage that will be at the RF and IF 1.1 VLO is applied to point A and -0.9 VLO
characteristics may change as various ele-
ports, is determined by the degree of diode is applied to point B (i.e., the center tap is at
ments affecting mixer performance are
balance in the circuit. With only an LO sig- a voltage of +0.9 VLO with respect to
changed (e.g., frequency, LO and RF drive
nal applied, the circuit in Figure 1 is basical- ground). The total voltage drop across diode
levels, load resistance, and temperature).
ly an ac bridge. Thus, in order to have zero
pairs D1, D2 and D3, D4 will be 2VLO. If
voltage drop from B to C, the following
DC OFFSET the diodes are perfectly balanced, the voltage
condition must hold:
Theoretically, when ∆Φ is equal to π/2, the at points B and C will be VLO with respect
dc voltage measured at the I port of the ZD1 ZD3 = ZD2 ZD4 (16) to ground. The I-port connects points B and
phase detector should be zero. DC offset is where ZDj is the complex impedance of C to the center tap of the LO transformer
the deviation from 0 Vdc that is seen when diode j. Equation (16) requires that each through a load resistor. There is thus a dc
∆Φ = π/2. If only one signal (LO or RF) is diode have the same v,i curve and that the voltage of 0.1 VLO that will be seen across
applied to the mixer, the dc offset is then stray capacitance and inductance on each this load resistor due to the transformer
simply the dc component of that portion of side of the bridge also be matched. The asymmetry alone.
the applied signal which is measured at the impossibility of ever perfectly satisfying
I port, implying that dc offset is inversely equation (16) is reflected by the fact that no MINIMIZING DC OFFSET
related to isolation. The impact of a non- mixer has infinite isolation. If the dc offset is known, its effect can be
zero dc offset voltage is shown in Figure 4. negated, or at least minimized, by simply
Both the actual phase angle at which a null The effect of transformer asymmetry can be
shown if it is assumed that somehow equa- applying an appropriate dc bias to the I port.
reading is obtained and the minimum and
tion (16) has been perfectly satisfied but Of course, the ideal way to minimize the
maximum voltages at the I port are affected.
effect of dc offset voltage is to select a mixer
The origin of dc offset voltages is a combi- having minimum dc offset in the first place.
nation of diode imbalance and transformer But, most mixer data sheets do not provide
asymmetry and can come from either or +VM this information. They do, however, provide
both input signals. Let us consider now the DC OFFSET = 0 isolation information which can be used to
VIF - VOLTS dc

## get a rough approximation of the dc offset.

0
π π This follows from the fact that dc offset is
2
∆φ − RADIANS simply the dc component of that portion of
RANGE OF LINEAR RESPONSE
δφ - DEGREES -VM
DEVIATION OF PHASE DETECTOR

## the applied LO (or RF) signal which is seen

OUTPUT FROM LINEARITY - %

## -60 -30 0 +30 +60

25 at the I port. For example, if a signal is
20 applied to the L port at a power level of LO
+VM dBm, the power in dBm dissipated in a 50-
15 +VM
DC OFFSET =
VIF - VOLTS dc

## 3 ohm load at the I port is

10
0 IF = LO - IS (17)
π π
5 2
where IS is the L-to-I isolation expressed in
0 -VM
30 60 90 120 150 db. Expressing the power at the I port in
PHASE DIFFERENCE ∆φ - DEGREES
watts we get
Figure 4. Non-zero dc offset voltage affects both the
Figure 3. Phase detector output is a pseudo-linear
function of phase difference.
value of ∆Φ at which a null reading is obtained and the
voltage measured for any given ∆Φ.
PIF = 10 ( ) =10(
IF
10
-3
LO - IS
10 )
-3
(18)

WJ Communications, Inc. • 401 River Oaks Parkway • San Jose, CA 95134-1918 • Phone: 1-800-WJ1-4401 • Fax: 408-577-6620 • e-mail: sales@wj.com • Web site: www.wj.com
The Communications Edge ™
Tech-note
Author: Stephan R. Kurtz

If we assume a 50Ω load resistance, we can explained because a mixer used as a phase
calculate that the magnitude of the voltage 20 detector is acting as a current source. Thus,
measured at the I port must be increasing the load impedance results in a

DC Offset - mV
20

## VIF = √ 50 PIF = (50)1/2 10

( LO - IS -30
20
-3 ) (19) larger voltage drop across the load. Also,
10 increasing the load impedance upsets the iso-
The average, or dc, value of the I port volt- 5 lation of the mixer. Mixer isolation is speci-
age (in volts) is given by 2/π VIF; thus, fied for (and measured with) the I port ter-
0
minated into 50 ohms. Any other load resis-
VDC = 2/π (50)1/2 10
( LO - IS -30
20 )
-3
(20a)
10 11 12 13 14
Frequency - GHz
15
tance results in part of the output being
SN18014
LO Drive Level = +7 dBm reflected back into the mixer, thereby upset-
or, more simply, SN23003
Load Resistor = 50 Ohms
SN22001 ting its balance.
VDC = (4.5) 10α (20b) EQN (20) Using
Typical Isolation
Figure 8 shows that variations and tempera-
where Guaranteed Isolation ture also affect dc offset voltage.
α = LO - IS - 30 Temperature affects dc offset by virtue of its
20 Figure 5. Magnitude of dc offset voltage as a function
of frequency for three different WJ-M14A mixers. Also
Although equation (20) makes no reference shown are results from equation 20 when typical and
to the polarity of the dc offset, it can be used guaranteed isolation values for the M14A are used.
16

DC OFFSET - mV
to get a rough idea of the magnitude of the 14 M1E
offset voltage. It is also useful in estimating device. This is also shown in Figure 5. The 12
10
the effects of changes in LO drive level jagged nature of the data in Figure 5 is due 8
6 M6G
and/or isolation (see Table I). Figure 5 com- to the fact that the L-to-I isolation is not 4
2
pares the results of equation (20) with data really a smooth function of frequency. 0
0 2 4 6 8 10 12 14
taken on three separate diode mixers. It is LO DRIVE LEVEL - dBm
Figure 6 shows the effect of varying the LO
seen that the magnitude of the offset voltage
drive level upon dc offset voltage for typical
at any given frequency can differ from unit- Figure 6. Magnitude of dc offset as a function of LO
diode mixers. drive level of the WJ-M1E and M6G mixers. (Data on
to-unit of the same mixer. This is because
the M1E mixer were taken at a frequency of 210 MHz,
the isolation is not identical between the In addition to isolation and LO drive level, with a load resistance of 1000Ω. Data on the M6G
dc offset is also affected by load resistance mixer were taken at a frequency of 1.5 GHz, with a load
units. Using typical isolation values for this resistance of 50Ω.)
model mixer, equation (20) gives results con- and temperature. Figure 7 shows that
sistent with the spread of data from the three increasing the load resistance of the I port of
mixers. Using guaranteed isolation values, a mixer results in an increase in dc offset.
equation (20) gives the maximum dc offset This effect is most pronounced for initial 3.0

voltage that would be expected for such a increases above 50 ohms and can be
DC OFFSET at LOAD R
DC OFFSET at 50 Ω

## 0 +3 +7 +10 +13 +17 +20

15 25.3 35.8 63.7 90.0 127.1 226.0 319.2
20 14.2 20.1 35.8 50.6 71.5 127.1 179.5 1.0
ISOLATION - dB

## 25 8.0 11.3 20.1 28.5 40.2 71.5 100.9

30 4.5 6.4 11.3 16.0 22.6 40.2 56.8
35 2.5 3.6 6.4 9.0 12.7 22.6 31.9
0
40 1.4 2.0 3.6 5.1 7.1 12.7 17.9 0 200 400 600 800 1000
LOAD RESISTANCE - Ω
45 0.80 1.1 2.0 2.9 4.0 7.1 10.1
50 0.45 0.64 1.1 1.6 2.3 4.0 5.7 Figure 7. Increasing load resistance affects dc offset.
(Data shown were taken using a mixer at a frequency
Table I. DC offset voltage in millivolts for various combinations of LO drive level and isolation. of 210 MHz and an LO drive level of +14.6 dBm.)

WJ Communications, Inc. • 401 River Oaks Parkway • San Jose, CA 95134-1918 • Phone: 1-800-WJ1-4401 • Fax: 408-577-6620 • e-mail: sales@wj.com • Web site: www.wj.com
The Communications Edge ™
Tech-note
Author: Stephan R. Kurtz

## the RF signal. Figure 9 shows the effect of a

mixer-induced phase shift on the phase PHASE SHIFT = 0 = θ
20 +VM
detector output. Both the actual phase angle

VIF - VOLTS dc
M1E
at which a null reading is obtained and the
0
15 voltage seen at any give ∆Φ are affected by π π
2
DC OFFSET - mV

mixer induced phase shifts. The minimum -VM
and maximum voltages seen at the I port are
10
not affected, however.
PHASE SHIFT =
+VM

VIF - VOLTS dc
5 MINIMIZING MIXER-INDUCED
M62 @ 4.2 GHz
PHASE SHIFT
0 π π
Just as for dc offset, most mixer data sheets 2
-60 -40 -20 0 20 40 60 80 100
do not provide any information with respect -VM
TEMPERATURE - ¡C
to mixer-induced phase shift Θ. Unfortunately,
-5
M62 @ 3.7 GHz unlike dc offset, Θ is not easily related to
Figure 9. Mixer-induced phase shift Θ affects the
any of the standard mixer parameters which apparent relative phase at which a null reading is
Figure 8. Changing temperature affects dc offset. (Data obtained. Minimum and maximum voltages are not
on the WJ-M1E mixer were taken at a frequency of 210
are reported. The design engineer thus has
affected, however.
MHz, and LO drive level of +14.6 dBm, and a load no guidance whatsoever as to which mixer to
resistance of 1000Ω. Data shown for 3 different units.
These data were taken using an LO drive level of use in order to minimize Θ. The best he can
which the effects of both dc offset and mixer
+6 dBm and a load resistance of 50Ω.) do is specify a mixer with as symmetric a cir-
induced phase shift are evident. The data as
cuit layout as possible and then measure Θ
originally taken would indicate a null output
effect upon the conductance characteristics once he has the mixer in hand. Minimizing
the effects of Θ are relatively simple once the voltage at ∆Φ equal to 164°, a maximum
of the diodes. As each diode reacts different-
ly to the temperature change, the balance of value of Θ is known. All that is required is positive voltage of +73 mV at 258° and a
the mixer is upset and, as a result, isolation that the electrical lengths of the lines leading maximum negative voltage of -64 mV at 78°.
changes. to the L and R ports be adjusted appropri- These results obviously do not agree with
ately to compensate for the different electri- the theoretical performance described earlier
MIXER-INDUCED PHASE SHIFT cal lengths from the L-to-I ports and the R- in this article. The dc offset can be obtained
Even after the effects of dc offset have been to-I ports.
by taking one half of the difference between
minimized, it is still possible that a null Figure 10 shows data taken on a mixer in the magnitudes of the maximum output
reading will be obtained at some relative
phase other than π/2. This is because the
mixer itself may change the relative phase of
the two input signals; i.e., signals input at a 80

## relative phase difference ∆Φ may produce a 60

dc output voltage at the I port correspond- 40
DC OUTPUT - mV

## ing to a relative phase ∆Φ + Θ. This incre- H

20
mental phase shift Θ results from the fact
0
that the electrical length from the L-to-I 30 60 90 120 150 180 210 240 270 300 330 360
-20 ∆φ - DEGREES
port is not identical to that from the R-to-I DC OFFSET
port. Some mixers are purposely designed -40
with nonsymmetrical circuits in order to -60
couple and match the diodes and to provide -80
the correct impedance matching to the R
and L ports. These circuit asymmetries result
Figure 10. Data on dc output vs taken on a diode mixer demonstrates the effects of both dc offset and mixer-
in a different phase shift being imposed on induced phase shift. The dashed line shows the effect of the dc offset. (Data were taken using a frequency of 1.5
the LO signal than that which is imposed on GHz, an LO drive level of +6 dBm, an RF level of -9 dBm, and an IF load of 50.

WJ Communications, Inc. • 401 River Oaks Parkway • San Jose, CA 95134-1918 • Phone: 1-800-WJ1-4401 • Fax: 408-577-6620 • e-mail: sales@wj.com • Web site: www.wj.com
The Communications Edge ™
Tech-note
Author: Stephan R. Kurtz

voltages; i.e., dc offset = 1/2 (|+73| - |-64|) = version loss. Thus, as conversion loss operate in a 50-ohm system and the I port
+4.5 mV. If the horizontal axis is shifted decreases, maximum output voltage increas- expects to work into a 50-ohm load imped-
upward by 4.5 mV the data would now es. And, as shown previously, this results in ance. However, many dc and low frequency
indicate a null reading at ∆Φ equal to 168°, increased sensitivity of the phase detector to impedance levels are much higher than 50
a maximum positive voltage of +68.5 mV at changes in ∆Φ near π/2. ohms. In Figures 13 and 14 we show the
258° and a maximum negative voltage of effects of varying the load resistance on
-68.5 mV at 78°. The locations of the null DRIVE LEVELS phase detector output. The results can be
and maximum output readings are all shifted Drive levels of the signals applied to the L
from their theoretical locations by the mixer- and R ports must be within the specified
induced phase shift of 78°. This indicates an limits for the mixer being used. The LO sig-
electrical path length difference of 3.52 cm nal must be of a level sufficient to turn on 130

MAXIMUM DC OUTPUT - mV
(i.e., the diodes while the RF signal should be M6G
120
δ1= Θ × c = 78° ( 3 × 1010 cm/sec
360 f 360° 1.85 × 109 cycles/sec ) below the 1dB compression point. Again,
this much is basic. Of more interest is how 110
M6KC @ 2.5 MHz

= 3.52 cm). Increasing the length of the line varying the LO and/or RF signal levels with- 100
leading to the R port by 3.52 cm and apply- in the above specified limits will affect the 90
M6KC @ 5.0 MHz
ing two signals 90° out of phase resulted in a output of the phase detector.
80
null reading, just as theory would predict.
Normally, the LO signal level is sufficiently
70
high to completely turn on the mixer. This
FACTORS AFFECTING PHASE
results in variations in LO signal level having -2 0 2 4 6 8 10
DETECTOR RESPONSE LO DRIVE LEVEL - dBm
a relatively minor effect on output voltage.
When a mixer is used in a phase detector Figure 11 bears this out with data taken two
application, all of the standard rules and pre- types of diode mixers. It also must be kept in Figure 11. Maximum dc output voltage increases as LO
drive level increases. (Data on the WJ-M6G were taken
cautions for mixer use are still in effect. mind that variations in LO drive level can at 1.5 GHz using an RF level of -3 dBm, and a load
Thus, even after the nonideal characteristics resistance of 50Ω. Data on the WJ-M6KC were taken at
affect the dc offset of the phase detector. frequencies of 2.5 and 5.0 MHz using an RF level of 0
and their effects have been minimized, the This follows directly from equation (20) and dBm, and a load resistance of 50Ω.
design engineer still must concern himself was shown in Figure 6.
with how variations in frequency, drive lev-
If it is assumed that the LO signal has com-
els, load and temperature will influence the
pletely turned on the mixer, then the output 2.5
mixer’s response as a phase detector.
signal level will be the RF signal level minus
2.0 RF = + 25 dBm
the conversion loss. This is valid until com-
FREQUENCY
pression begins to take place. Figure 12 shows 1.5 RF = + 20 dBm
The frequency must be within the band- how the output of diode mixer is affected by
1.0 RF = + 17 dBm
widths of the L and R ports. More subtle
DC OUTPUT - VOLTS

## variations in RF drive level. The data in

effects of frequency include its influence Figure 12 corresponding to the RF = +25 dBm 0.5
RF = + 10 dBm
upon dc offset, upon maximum output volt- curve represent output taken with an RF level 0
age and upon the detector’s sensitivity to 45 90 135 180
above the 1 dB compression point. This is a ∆φ - DEGREES
changes in phase angle. -0.5
possible and often desirable mode of phase
Frequency affects dc offset by virtue of its detector operation. Increasing the RF level -1.0

effect upon isolation as shown in Figure 5. It above the 1 dB compression point does pro- -1.5
changes maximum output voltage and sensi- duce an increase in maximum output voltage.
-2.0
tivity by virtue of its effect upon conversion And, it is again noted that anything which
loss. Assuming that the LO signal is of a level affects the maximum output voltage also -2.5

sufficient to completely turn on the diodes affects the sensitivity of the phase detector.
and assuming infinite L-to-I isolation, the
output signal level VIF will be essentially IF LOAD Figure 12. Increasing the RF level increases the maxi-
mum output voltage. (Data were taken at 30 MHz using
equal to the RF signal level minus the con- Most double balanced mixers are designed to an LO level of +27 dBm, and a load resistance of 50Ω.)

WJ Communications, Inc. • 401 River Oaks Parkway • San Jose, CA 95134-1918 • Phone: 1-800-WJ1-4401 • Fax: 408-577-6620 • e-mail: sales@wj.com • Web site: www.wj.com
The Communications Edge ™
Tech-note
Author: Stephan R. Kurtz

Varying the temperature of the environment true at low frequencies. Another benefit
in which the phase detector is being used offered by double balanced mixers over sin-
2.5
primarily affects the conductance character- gle balanced mixers is that fewer undesired
2.0
istics of the diodes. These effects are reflected frequencies are appearing at the I port.3
R = + 1000 Ω
by variations in the mixer’s isolation and
1.5 conversion loss characteristics. Figure 8 LOW LEVEL VS HIGH LEVEL
R = + 100 Ω shows the effect of temperature variation The choice as to whether a low or high level
1.0
R = 50 Ω
upon dc offset voltage. Figure 15 shows the mixer needs to be used is often dependent
DC OUTPUT - VOLTS

0.5 effect of temperature variation upon phase upon the specific application being considered.
detector output voltage.
0
A couple of points are worth mentioning.
45 90 135 180
∆φ - DEGREES SELECTING THE RIGHT MIXER First, high level mixers have inherently more
-0.5
This section presents some general guidelines complex circuits than do low level mixers
-1.0
which can be followed when selecting a mixer (see Figure 16).1 Low level mixers are of a
for use as a phase detector. For any particular Class I type, typically having only a single
-1.5
application, more than one mixer may satisfy diode in each leg. High level mixers are of
-2.0 the given guidelines; or one or more of the either Class II or Class III and have multiple
guidelines may need to be violated. elements in each leg. Class II, Type I mixers
have two diodes in each leg; Class II, Type 2
SINGLE VS DOUBLE BALANCE mixers have a series precision resistor and a
Figure 13. Increases in load resistance result in
diode in each leg; and Class III mixers have
increased maximum output voltage. (Data were taken at In principle, any mixer with a dc coupled
a frequency of 30 MHz using an LO drive level of +27 a capacitor in parallel with a series resistor
dBm, and RF level of +17 dBm.) port (even a single diode) can be used as a
and a diode in each leg. The result of this
phase detector. In practice, phase detectors
increased complexity in high level mixers is
are most commonly double balanced mixers.
The reason behind this is that double bal- that they are more difficult to balance. This
200
anced mixers often have better isolation can result in lower isolation and higher dc
R = 412 Ω
characteristics (and better dc offset) than do offset and mixer-induced phase shift.
DC OUTPUT - mV

100 R = 100 Ω
R = 50 Ω single balanced mixers. This is particularly A second point to keep in mind is that at any
0
given frequency, it is common that there will
-100 be available a smaller selection of high level
mixers than low level mixers. This is particu-
-200 250 +25¡C
0 90 180 larly true at higher frequencies (i.e., ≥ 1 GHz).
+60¡C
∆φ - DEGREES 200 -10¡C An option to be kept in mind then, is to
150 attenuate the incoming signals and use a low-
Figure 14. Increases in load resistance result in 100 level mixer to compare their phases.
DC OUTPUT - mV

## increased maximum output voltage. (Data were taken

on a WJ-M6G mixer at a frequency of 1.85 GHz using 50
an LO level of +6 dBm, and an RF level of -9 dBm. 0
Increasing load from 412Ω to 825Ω did not appreciably 20 60 100 140 180
change the results. -50 ∆φ - Degrees
-100
CLASS 1 MIXER CLASS 2 MIXER
-150 (TYPE 2)
summarized by noting that as load resistance
-200
increases, so does peak output voltage. As in
-250
the case of dc offset, this effect is explained
by the fact that a mixer used as a phase CLASS 2 MIXER CLASS 3 MIXER
(TYPE 1)
detector acts as a current source. And, again, Figure 15. Effects of temperatre variation on phase
increasing the peak output voltage increases detector output. (Data using an LO level of 0 dBm, an
RF level of 0 dBm, a load resistance of 1000Ω, and a Figure 16. The various classes of mixers have different
the sensitivity of the phase detector. frequency of 14,258 MHz.) elements.

WJ Communications, Inc. • 401 River Oaks Parkway • San Jose, CA 95134-1918 • Phone: 1-800-WJ1-4401 • Fax: 408-577-6620 • e-mail: sales@wj.com • Web site: www.wj.com
The Communications Edge ™
Tech-note
Author: Stephan R. Kurtz

LOW FREQUENCY VS HIGH the same conductance characteristics. having maximum isolation in the fre-
FREQUENCY However, at low frequencies, it is possible to quency range over which phase detection
As with signal level, the frequency of the select discrete diodes so that their balance is is to take place. This will minimize dc
incoming signal is dependent upon the spe- superior to that of a quad. offset. If any information is available at
cific application being considered. In princi- this point, it is also desirable to select
ple, there is no reason why a microwave GENERAL GUIDELINES those mixers having minimum mixer-
mixer should behave any differently than a Shown below are some general rules-of- induced phase shift.
low frequency mixer when used as a phase thumb to be followed when selecting a mixer 4) From those mixers having maximum iso-
detector. In practice, however, there are a for a specific phase detector application: lation and minimum mixer-induced
few facts worth considering.
1) Determine whether a high or low level phase shift, select those having minimum
First, as frequency increases, the number of mixer is needed. High level means the conversion loss. This will maximize the
mixers available to select from decreases. total combined input power is above sensitivity of phase response.
Second, as frequency increases, isolation +10 dBm.
In addition to the above guidelines, other
decreases and as a result, dc offset increases.
2) Select those mixers of the appropriate criteria that affect mixer selection include
This follows from the fact that as frequency
level whose bandwidth is such that the size, package type, connector type, and price.
increases, wiring capacitance, transformer
frequency range over which phase detec-
winding capacitance, and physical location
tion is to take place lies well within the REFERENCES
of components all act to upset the balance of
bandwidth. This follows from the fact 1. Cheadle, D.L. “Selecting Mixers for Best
the mixer. An option to be kept in mind
that it is desirable to maximize isolation Intermod Performance,” Microwaves,
that would minimize these problems would
(in order to minimize dc offset) and min- Vol. 12, Nos. 11 and 12 (November,
be to downconvert the incoming signals
before comparing their phase. imize conversion loss (in order to maxi- December, 1973), pp. 48-54, 58-62.
mize the sensitivity of phase response).
Both of these characteristics are degraded 2. Cochrane, J.B. and F.A. Marki. “Thin-
near the ends of the bandwidth. Film Mixers Team Up to Block Out Mixer
Whether it is better for a mixer to use dis- Noise,” Microwaves, Vol. 16, No. 3
Deviations from this rule may be possible
crete diodes or a monolithic quad depends (March 1977), pp. 34-40.
when specific data on isolation and con-
on the specific application. A quad will offer
version loss vs frequency is available for 3. Pappenfus, EW., W.B. Bruene, and E.O.
better temperature stability than will discrete
the frequency range in question. Schoenike. Single Sideband Principles
diodes. A quad also offers excellent circuit
balance because the diodes in the quad all 3) From the group of mixers of appropriate and Circuits, New York: McGraw-Hill,
come from the same silicon chip and have level and bandwidth, select those mixers 1964, p. 130.