Eval Programmation Complete

Evaluation programmation Partie 1 : questionnement crit (9 pages) Partie 2 : questionnement TP (10 pages) Partie 3 : document ressource (4 pages) Partie
4 : extrait documentation constructeur PIC16F877
Evaluation programmation Partie 1 Questionnement crit
Sige 406 Evaluation programmation Questionnement de la partie crite I Analyse de la version en langage assembleur I.1 Sous programme INIT
Question1 A partir du schma structurel du PIC16F877, indiquer dans le tableau du document rponse 1, les configurations des diffrents ports dentres/sorties. Indiquer galement quel est le signal affect chacune des broches. Question2 Par dfaut et dune manire gnrale, comment sont configures les broches dentres/sorties du PIC16F877 ? Configuration du PORTD : Question3 Ecrire les instructions assembleurs permettant daccder la banque0. Justifier votre rponse. Complter alors la partie intitule slection de la banque 0 par dfaut du document rponse 2. Question4 Quel est le nom du registre de configuration du PORTD ? Quelle doit tre la valeur stocke dans ce registre pour configurer correctement le PORTD. Justifier votre rponse. Question5 Ecrire les instructions assembleurs permettant de configurer le PORTD correctement. Complter alors la partie intitule Configuration du PORTD du document rponse 2. Question6 En considrant les signaux affects aux broches du PORTD, indiquer quels devront tre leurs tats logiques lorsque le systme est mis sous tension. Justifier votre rponse. Ecrire les instructions assembleurs permettant dinitialiser correctement ces broches. Complter la partie intitule Configuration du PORTD du document rponse2. Configuration du PORTA et du PORTD : La particularit de ces entres est quelles peuvent tre configures soit en analogique soit en numrique. Question7 Dans le cas de notre systme technique, doit on utiliser ces broches en numriques ou en analogiques. Justifier votre rponse. Question8 Daprs la documentation constructeur, quel est le registre permettant de configurer lutilisation des entres en analogique ou en numrique. Dans quelle banque se trouve ce registre ?
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Sige 406 Evaluation programmation Questionnement de la partie crite

Question9 En supposant que le bit ADFM=1, indiquer quelle devra tre la valeur de ce registre. Justifier votre rponse. Question10 Ecrire les instructions assembleurs permettant de configurer correctement le PORTA et le PORTE. Complter la partie intitule configuration du PORTA et du PORTE du document rponse 2.
I.2 Programme principal

On souhaite crire en langage assembleur, le programme correspondant lalgorigramme du programme principal (voir document ressource). On utilisera les dclarations du fichier Decla.h pour une lisibilit du programme. Test FC_AV=0 : Dans le fichier de dclarations on a la ligne suivante :
#DEFINE FC_AV PORTE,1
Test VAR_GV=1 : VAR_GV est le bit0 de la variable 8 bits VAR_GRANDE_VIT :

#DEFINE VAR_GV VAR_GRANDE_VIT,0
Test BP_MVT_SENS actifs On dcomposera ce test de cette manire.
W=$FF BP_MVT_SENS actifs ? OUI Z=0 ? OUI NON NON PORTC-W
Z est un bit du registre STATUS. Pour tester ce bit on pourra utiliser la syntaxe suivante : STATUS,Z Action sur VAR_DEP : VAR_DEP est une variable sur 8 bits.
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Test IMA_ACC : Dans le fichier de dclarations on a la ligne suivante :
#DEFINE IMA_ACC PORTE,0
Test BP_M=0, BP_CONDUCT1=0 et BP_CONDUCT2=0 : Dans le fichier de dclarations on a les lignes suivantes :
#DEFINE #DEFINE #DEFINE BP_M BP_CONDUCT1 BP_CONDUCT2 PORTB,1 PORTB,2 PORTB,3
Question11 Ecrire le programme principal en langage assembleur correspondant lalgorigramme du programme principal. Justifier toutes vos instructions par des commentaires. Complter le document rponse 3.
II Analyse de la version en langage C II.1 Etude du sous programme detect_sens

Question12 Dfinir la sortie DIR (voir description de F1.3.3 Dtecter le sens de rotation des moteurs ). Question13 Rappeler le rsultats des oprations suivantes : -a0, -a1, -a+0, -a+1. Sachant que a correspond une variable sur 1 bit. Question14 En dduire quelle est lopration raliser avec DIR pour mettre 1 la variable DIR_GLI sans modifier les autres variables. Question15 Quelle est lopration raliser avec DIR pour mettre 0 la variable DIR_GLI sans modifier les autres variables.
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On rappelle les instructions suivantes du langage C :
Les oprateurs logiques bit bit :

Ces oprateurs agissent sur des mots binaires. Ils effectuent entre deux mots une opration logique sur les bits de mme rang.
Oprateur & | ^ ~ >> << Fonction ET OU OU exclusif NON Dcalage droite des bits Dcalage gauche des bits Notation Z=X&Y Z=X|Y Z=X^Y Z=~Y Z=X>>4 (Z prend la valeur de X aprs le dcalage droite de 4 bits) Z=X<<4 (Z prend la valeur de X aprs le dcalage gauche de 4 bits)
Les oprateurs de tests conditionnels :

Ces oprateurs sadressent uniquement aux oprations de test conditionnel. Le rsultat de ces tests est binaire : vrai(= 1 ) ou faux(= 0 ). Les oprateurs logiques :
Oprateur && || ! Fonction ET logique OU logique NON logique
Question16 En saidant de ce qui a t ralis jusqu prsent, crire le sous programme detect_sens en langage C. Justifier les mises 1 ou 0 des variables DIR_GLI, DIR_REHA, DIR_SITE et DIR_DOS.
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Sige 406 Evaluation programmation Questionnement de la partie crite II.2 Etude du sous programme inc_pos_gli
Le sous programme inc_pos_gli permet dincrmenter une seule fois la variable POS_GLI. Nous pouvons agir uniquement sur les variables POS_GLI_H et POS_GLI_L. Question17 Dfinir la variable POS_GLI (voir description de F1.3 Calculer la position courante ). Question18 Dfinir les variables POS_GLI_H et POS_GLI_L. En supposant que POS_GLI=$8153, indiquer les valeurs prises par POS_GLI_H et POS_GLI_L. Question19 Dessiner un tableau montrant la variable POS_GLI sincrmentant de $7FFD $8002 ainsi que les variables POS_GLI_H et POS_GLI_L correspondantes. Question20 Proposer un algorigramme permettant de raliser le sous programme inc_pos_gli . Il faut saider des questions prcdentes. Question21 Ecrire le programme en langage C correspondant lalgorigramme inc_pos_gli .
II.3 Etude du sous programme dec_pos_gli

Le sous programme dec_pos_gli permet de dcrmenter une seule fois la variable POS_GLI. Nous ne pouvons agir uniquement sur les variables POS_GLI_H et POS_GLI_L. Question22 Proposer un algorigramme permettant de raliser le sous programme dec_pos_gli . Question23 Ecrire le programme en langage C correspondant lalgorigramme dec_pos_gli .
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Sige 406 Evaluation programmation Questionnement de la partie crite DOCUMENT REPONSE 1

Nom de la broche RA0 RA1 RA2 RA3 RA4 RA5 RB0 RB1 RB2 RB3 RB4 RB5 RB6 RB7 RC0 RC1 RC2 RC3 RC4 RC5 RC6 RC7 RD0 RD1 RD2 RD3 RD4 RD5 RD6 RD7 RE0 RE1 RE2 Configuration (E, S ou NU (Non Utilis)) Nom du signal
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;*********************************************************************** ;* sous programme initialisation (init) partiel * ;*********************************************************************** ;* Ce sous programme permet d' initialiser toutes les variables, et les registres * ;* du PIC16F877 * ;*********************************************************************** init ;*********************************************************************** ;* A complter : slection banque 0 (par dfaut) * ;***********************************************************************
;*********************************************************************** ;* Initialisation des variables * ;*********************************************************************** BCF DEP_RAP1 BCF DEP_RAP2 BCF DEP CLRF DIR CLRF VAR_TEMPO CLRF VAR_GRANDE_VIT CLRF POS_GLI_PREC_L ;*********************************************************************** ;* partie complter : configuration du PORTD * ;***********************************************************************
;*********************************************************************** ;* partie complter : configuration du PORTA et PORTE * ;***********************************************************************
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;*********************************************************************** ;* PROGRAMME PRINCIPAL * ;*********************************************************************** LIST p=16F877 #include <p16F877.inc> ORG GOTO 0x0000 DEBUT ; adresse de dpart aprs Reset
DEBUT ORG 0x060 ;*********************************************************************** ;* Partie complter : on dbute par lappel du sous programme init * ;* Il faut crire tout le programme principal en langage assembleur * ;***********************************************************************
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Evaluation programmation Partie 2 Questionnement TP
Sige 406 Evaluation programmation Questionnement de la partie TP I Cration du projet

Critres dvaluations :
PMC1 : mettre jour un projet existant ou crer un projet PMC1.1 : ouvrir ou crer un projet PMC1.2 : choisir loutil de construction PMC1.3 : configurer les paramtres de constructions PMC1.4 : choisir le microcontrleur PMC1.7 : ajouter le fichier source et les fichiers include au projet PMC2 : compiler le projet PMC2.1 : lancer la compilation PMC2.2 : dtecter les erreurs PMC2.3 : corriger les erreurs
On dispose de trois fichiers : -406.c, -Decla.h, -pic1687x. Ces fichiers sont stocks dans votre rpertoire de travail. On dsire crer un projet nomm 406 dans un autre rpertoire nomm 406_TPx (x=1 si vous passez en premier, x=2 si vous passez en second). Ce rpertoire sera crer. Question1 Copier les trois fichiers fournis dans le nouveau rpertoire. Crer le projet permettant dutiliser les fichiers fournis. Compiler votre projet. Une fois le projet compil correctement appeler le professeur pour valider votre travail en lui expliquant les diffrentes tapes.
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Sige 406 Evaluation programmation Questionnement de la partie TP II Programmation et test de la mmorisation sur le sige 406
PMC4 : programmer le microcontrleur PMC4.1 : enregistrer le fichier de programmation PMC4.2 : mettre en uvre le programmateur PMC4.3 : placer correctement le microcontrleur PMC4.4 : slectionner le composant programmer laide dun logiciel PMC4.5 : charger le fichier de programmation PMC4.6 : programmer le composant PMC5 : rdiger le compte rendu PMC5.3 : proposer une mthode de tests du programme PMC5.4 : traduire les rsultats observs PMC5.5 : conclure sur la validit du programme test
Le programme 406.c permet de : -calculer la position courante du sige, -mmoriser une position dun conducteur, -rappeler les positions mmorises Ce programme ne gre pas la grande vitesse. On souhaite : -programmer le PIC16F877, -tester le programme par une observation sur le systme sige 406 . Question2 A partir du dossier technique, rappeler quelle est la procdure de mmorisation. Que se passe-t-il la fin de la mmorisation ? Question3 A partir du dossier technique, rappeler quelle est la procdure de rappel dune position mmorise. Que se passe-t-il la fin du rappel. Question4 : critre PMC5.3 : proposer une mthode de test Proposer une mthode de test par lobservation sur le systme sige 406 pour vrifier que le programme permet bien : -de mmoriser la position de conduite n1, -de rappeler la position de conduite mmorise n1, Une fois la mthode trouve et rdige, vous pouvez passer la question suivante.
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Sige 406 Evaluation programmation Questionnement de la partie TP

La question suivante se fait sur le poste de programmation et sur le sige 406. Si la place est occupe ne perdez pas de temps et passez la 3 partie Test du sous programme memo grce au logiciel MPLAB. Question5 : critre PMC4 : programmer le microcontrleur Programmer le PIC16F877 avec le fichier adquat. Question6 : critre PMC5.4 : traduire les rsultats des tests observs et PMC5.5 : conclure sur la validit du programme test Placer correctement le PIC16F877 sur la carte PIC . Insrer la carte PIC dans le rack. Procder aux tests et valider le fonctionnement du programme. Vous devez faire valider le fonctionnement par le professeur. Rdiger lobservation de vos tests.
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Sige 406 Evaluation programmation Questionnement de la partie TP III Test du sous programme memo grce au logiciel MPLAB
PMC3 : simuler le programme en mode pas pas PMC3.1 : crer des stimuli PMC3.2 : crer une fentre de visualisation PMC3.3 : observer le contenu des mmoires du microcontrleur PMC3.4 : faire dfiler le programme pour diffrents cas de fonctionnement PMC3.4.1 : montrer le droulement du programme quand rien ne se passe PMC3.4.2 : montrer le droulement du programme lorsque lon agit sur certaines entres et/ou certaines variables PMC3.4.3 : montrer laction du programme sur les sorties et/ou les variables et/ou le contenu des mmoires. PMC3.4.4 : conclure sur le fonctionnement du programme PMC5 : rdiger le compte rendu PMC5.3 : proposer une mthode de tests du programme PMC5.4 : traduire les rsultats observs PMC5.5 : conclure sur la validit du programme test
Dans cette partie on souhaite valider par la simulation la mmorisation de la position de conduite 1.
III.1 Initialisation des entres

Question7 Complter le document rponse 1 en indiquant : -les correspondances des broches dentres du PIC16F877 avec les noms des signaux, -les niveaux logiques de toutes les entres du PIC16F877 lorsque le sige est au repos. Il faut saider de la description de la fonction F12 Acqurir les consignes Question8 : critre PMC3.1 : crer les stimuli Crer trois stimuli diffrents sauvegarder dans le rpertoire du projet intituls : -PORTC.Psti, -PORTB.Psti, -PORTE.Psti Question9 En procdant de la manire suivante, configurer les entres du PIC16F877 correspondant un fonctionnement du sige au repos : Lancer la simulation du programme (touche F9). Ouvrir le stimulus PORTB.Psti Configurer les niveaux logiques des entres du port B (sige au repos). Fermer le stimulus PORTB.Psti Recommencer pour les ports C et E. Question10 : critre PMC3.2 : crer une fentre de visualisation Vrifier que les entres du PIC16F877 sont configures correctement. G BERTHOME Page 4/10

Question11 : critre PMC3.4.1 : montrer le droulement du programme quand rien ne se passe En simulant le programme en pas pas vrifier que son excution correspond bien lvolution de lalgorigramme du programme principal lorsque le sige est au repos. Faire valider par le professeur.
III.2 Test du sous programme memo III.2.1 Dfinition du cahier des charges du sous programme memo
Il faut saider de la description des fonctions F13 Calculer la position courante et F14 Mmoriser la position Cette partie vise exploiter le dossier technique afin de mieux comprendre le rle du sous programme memo . Si vous tes bloqu vous pouvez passer la suite et revenir ensuite cette partie. Ne perdez pas de temps sur cette partie Question12 A votre avis, dans quel type de mmoire est stocke la position courante du sige ? Question13 Indiquer le nombre de variables qui composent la position courante du sige (voir F13 Calculer la position courante ) Nommer ces variables. Dterminer alors le nombre doctets ncessaires pour avoir une information sur la position courante du sige. Question14 A partir de lextrait de la documentation constructeur du PIC16F877, dterminer la capacit de la mmoire utilis pour stocker la position courante du sige. Est-elle suffisante ?(on suppose quil faut stocker 2 positions de conduite plus la position courante). Justifier votre rponse. On donne un extrait du fichier Decla.h :
static static static static static static static static unsigned char unsigned char unsigned char unsigned char unsigned char unsigned char unsigned char unsigned char POS_GLI_MEM1_L=0x00; POS_GLI_MEM1_H=0x01; POS_REHA_MEM1_L=0x02; POS_REHA_MEM1_H=0x03; POS_SITE_MEM1_L=0x04; POS_SITE_MEM1_H=0x05; POS_DOS_MEM1_L=0x06; POS_DOS_MEM1_H=0x07;
Question15 Nommer les adresses o seront stockes les variables reprsentant la position courante. Indiquer les valeurs de ces adresses. Question16 Reprsenter partiellement la mmoire o seront stockes les variables reprsentant la position courante en indiquant : -les noms des variables, -les nom des adresses, -les valeurs des adresses.
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Sige 406 Evaluation programmation Questionnement de la partie TP III.2.2 Test du sous programme memo
Procdure de test : critre PMC5.3 : proposer une mthode de test du programme Question17 Proposer une procdure de test pour vrifier que lon stocke correctement les variables en mmoire. On veut notamment voir dans cette procdure les tapes suivantes : -modification des variables reprsentant la position courante (on sait que la position initiale pour tous les mouvements est $7FFF). On se fixe 4 valeurs fixer qui sont les suivantes : -POS_GLI=$8150, -POS_REHA=$7F32, -POS_SITE=$80AB, -POS_DOS=$7E6A -mthode pour excuter le sous programme memo , -mthode pour mmoriser le position, -observation des variables reprsentant la position courante stockes en mmoire aux bonnes adresses. Tests : critres dvaluation :
PMC3 : simuler le programme en mode pas pas PMC3.2 : crer une fentre de visualisation PMC3.3 : observer le contenu des mmoires du microcontrleur PMC3.4 : faire dfiler le programme pour diffrents cas de fonctionnement PMC3.4.1 : montrer le droulement du programme quand rien ne se passe PMC3.4.2 : montrer le droulement du programme lorsque lon agit sur certaines entres et/ou certaines variables PMC3.4.3 : montrer laction du programme sur les sorties et/ou les variables et/ou le contenu des mmoires.
Question18 Effectuer les tests en vrifiant que le programme fonctionne selon vos attentes. Attention : le sous programme prod_sign_sonore utilise des temporisations vous resterez bloqu dedans. Pour en sortir il faudra faire un reset et excuter de nouveau le programme principal lorsque le sige est au repos. Faire valider par le professeur
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Transcription des rsultats : critre PMC5.5 : conclure sur la validit du programme test Question19 On souhaite savoir ce que vous avez observez tape par tape. Transcrire alors les rsultats observs. Question20 Reprsenter le contenu de la mmoire (partiel : uniquement ce qui nous intresse) en indiquant : -o se trouvent les adresses en notant leurs noms sur cette reprsentation -o se trouvent les donnes stockes en notant leurs noms sur cette reprsentation.
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Sige 406 Evaluation programmation Questionnement de la partie TP IV Validation que la position est mmorise
Dans cette partie on souhaite valider que lon crit rellement dans la mmoire du PIC16F877 par une lecture de son contenu. On sait que ladresse de dbut de la mmoire du PIC16F877 est $4200. Que la deuxime adresses est $4202. Etc Critres dvaluation :
PMC4 : programmer le composant programmable PMC4.7 : lire le contenu du composant PMC5 : rdiger le compte rendu PMC5.3 : proposer une mthode de test du programme PMC5.4 : traduire les rsultats observs PMC5.5 : conclure sur la validit du programme test
Question21 Proposer une mthode pour vrifier que lon stocke rellement les positions en mmoire. La question suivante se fait sur le poste de programmation et sur le sige 406. Si ces postes sont occups, ne perdez pas de temps et passez la 5 partie Modification du programme pour mmoriser la position du conducteur2 . Question22 Vrifier que la position du sige est bien mmorise en mmoire en appliquant votre mthode. Faire valider par le professeur en expliquant la mthode et en commentant le contenu de la mmoire du PIC16F877. Vous noterez notamment : -les actions ralises sur le sige, -les valeurs contenues dans la mmoire, -la conclusion.
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Sige 406 Evaluation programmation Questionnement de la partie TP V Modification du programme pour mmoriser la position du conducteur2
On souhaite modifier lalgorigramme et le programme afin que lon puisse mmoriser les deux positions de conduites. Question23 Proposer un nouvel algorigramme. Question24 Modifier le sous programme memo . Question25 Tester votre nouveau programme. Faire valider par le professeur. Question26 Tester votre programme sur le sige 406. Faire valider par le professeur.
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Sige 406 Evaluation programmation Questionnement de la partie TP DOCUMENT REPONSE 1

Nom de la broche RB1 RB2 RB3 RB4 RB5 RB6 RB7 RC0 RC1 RC2 RC3 RC4 RC5 RC6 RC7 RE0 RE1 RE2 Nom du signal Etat logique lorsque le sige est au repos
CAPT_GLI CAPT_REHA CAPT_SITE CAPT_DOS
0 0 0 0
IMA_ACC FC_AV FC_AR
1 1 0
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Evaluation programmation Partie 3 Document ressource
Evaluation programmation Document ressource
1. ALGORIGRAMMES
1.1 Programme principal du sige 406
DEBUT init
Systme aliment ? OUI NON NON FC_AV=0 ? OUI gv GR_VIT, COM_GLI_AV, COM_GLI_AR, VAR_GV
NON
VAR_GV=1 ? OUI gv
GR_VIT, COM_GLI_AV, COM_GLI_AR, VAR_GV
BP_MVT_SENS actifs ? OUI VAR_DEP=$01 detect_sens
NON NON
VAR_DEP=$01 ? OUI DIR mem_pos_cour VAR_DEP=$00
DIR
OUI
VAR_GV0 ? NON
OUI
IMA_ACC1 ? NON BP_M=0 ? OUI memo POS_MVT_MEM1, POS_MVT_MEM2, COM_BUZ
NON
NON
BP_CONDUCT1=0 ? OUI rappel1 COM_MVT_SENS, COM_BUZ
POS_MVT, POS_MVT_MEM1
NON
BP_CONDUCT2=0 ? OUI rappel2 COM_MVT_SENS, COM_BUZ FIN
POS_MVT, POS_MVT_MEM2,
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1.2 Sous-programme detect_sens
NON DEBUT
BP_GLI_AV=0 ? OUI DIR_GLI=1
NON
BP_GLI_AR=0 ? OUI DIR_GLI=0
NON
BP_REHA_MONT =0? OUI DIR_REHA=1
NON
BP_REHA_DESC =0? OUI DIR_REHA=0
NON
BP_SITE_MONT =0? OUI DIR_SITE=1
NON
BP_SITE_DESC =0? OUI DIR_SITE=0
NON
BP_DOS_AV=0 ? OUI DIR_DOS=1
NON
BP_DOS_AR=0 ? OUI DIR_DOS=0
DEBUT
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1.3 Programme dinterruption calculer_position_courante
DEBUT Sauvegarder les nouveaux tats des capteurs dans CHANG_CAPT NON NON bit 4 de CHANG_CAPT bit 4 de MEM_CAPT ? OUI DIR_GLI=0 ? OUI dec_pos_gli NON 1
bit 7 de CHANG_CAPT bit 7 de MEM_CAPT ? OUI DIR_DOS=0 ? OUI dec_pos_dos NON
inc_pos_dos
inc_pos_gli Mmoriser les nouveaux tats des capteurs MEM_CAPT=CHANG_CAPT
NON
bit 5 de CHANG_CAPT bit 5 de MEM_CAPT ? OUI DIR_REHA=0 ? OUI dec_pos_reha NON
FIN
inc_pos_reha
NON
bit 6 de CHANG_CAPT bit 6 de MEM_CAPT ? OUI DIR_SITE=0 ? OUI dec_pos_site NON
inc_pos_site
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1.4 Sous-programme memo partiel permettant de mmoriser uniquement une position de conduite
DEBUT
NON
BP_M=0 ? OUI BP_M=0 ET BP_CONDUCT1=0 ? OUI mem1 FIN_MEMO=1 prod_sign_sonore
NON
BP_M=0 OU BP_CONDUCT1=0 ? NON
OUI
FIN
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Evaluation programmation Partie 4 Documentation constructeur PIC16F877
PIC16F87X
28/40-Pin 8-Bit CMOS FLASH Microcontrollers
Devices Included in this Data Sheet:
PIC16F873 PIC16F874 PIC16F876 PIC16F877
Pin Diagram
PDIP
MCLR/VPP RA0/AN0 RA1/AN1 RA2/AN2/VREFRA3/AN3/VREF+ RA4/T0CKI RA5/AN4/SS RE0/RD/AN5 RE1/WR/AN6 RE2/CS/AN7 VDD VSS OSC1/CLKIN OSC2/CLKOUT RC0/T1OSO/T1CKI RC1/T1OSI/CCP2 RC2/CCP1 RC3/SCK/SCL RD0/PSP0 RD1/PSP1 1 2 3 4 5 6 40 39 38 37 36 35 RB7/PGD RB6/PGC RB5 RB4 RB3/PGM RB2 RB1 RB0/INT VDD VSS RD7/PSP7 RD6/PSP6 RD5/PSP5 RD4/PSP4 RC7/RX/DT RC6/TX/CK RC5/SDO RC4/SDI/SDA RD3/PSP3 RD2/PSP2
Microcontroller Core Features:

High performance RISC CPU Only 35 single word instructions to learn All single cycle instructions except for program branches which are two cycle Operating speed: DC - 20 MHz clock input DC - 200 ns instruction cycle Up to 8K x 14 words of FLASH Program Memory, Up to 368 x 8 bytes of Data Memory (RAM) Up to 256 x 8 bytes of EEPROM Data Memory Pinout compatible to the PIC16C73B/74B/76/77 Interrupt capability (up to 14 sources) Eight level deep hardware stack Direct, indirect and relative addressing modes Power-on Reset (POR) Power-up Timer (PWRT) and Oscillator Start-up Timer (OST) Watchdog Timer (WDT) with its own on-chip RC oscillator for reliable operation Programmable code protection Power saving SLEEP mode Selectable oscillator options Low power, high speed CMOS FLASH/EEPROM technology Fully static design In-Circuit Serial Programming (ICSP) via two pins Single 5V In-Circuit Serial Programming capability In-Circuit Debugging via two pins Processor read/write access to program memory Wide operating voltage range: 2.0V to 5.5V High Sink/Source Current: 25 mA Commercial, Industrial and Extended temperature ranges Low-power consumption: - < 0.6 mA typical @ 3V, 4 MHz - 20 A typical @ 3V, 32 kHz - < 1 A typical standby current
PIC16F877/874
7 8 9 10 11 12 13 14 15 16 17 18 19 20
34 33 32 31 30 29 28 27 26 25 24 23 22 21
Peripheral Features:
Timer0: 8-bit timer/counter with 8-bit prescaler Timer1: 16-bit timer/counter with prescaler, can be incremented during SLEEP via external crystal/clock Timer2: 8-bit timer/counter with 8-bit period register, prescaler and postscaler Two Capture, Compare, PWM modules - Capture is 16-bit, max. resolution is 12.5 ns - Compare is 16-bit, max. resolution is 200 ns - PWM max. resolution is 10-bit 10-bit multi-channel Analog-to-Digital converter Synchronous Serial Port (SSP) with SPI (Master mode) and I2C (Master/Slave) Universal Synchronous Asynchronous Receiver Transmitter (USART/SCI) with 9-bit address detection Parallel Slave Port (PSP) 8-bits wide, with external RD, WR and CS controls (40/44-pin only) Brown-out detection circuitry for Brown-out Reset (BOR)
2001 Microchip Technology Inc.
DS30292C-page 1
PIC16F87X
FIGURE 1-2:
Device PIC16F874 PIC16F877
PIC16F874 AND PIC16F877 BLOCK DIAGRAM

Program FLASH 4K 8K Data Memory 192 Bytes 368 Bytes
13 FLASH Program Memory 8 Level Stack (13-bit) Program Counter
Data EEPROM 128 Bytes 256 Bytes

Data Bus 8 PORTA RA0/AN0 RA1/AN1 RA2/AN2/VREFRA3/AN3/VREF+ RA4/T0CKI RA5/AN4/SS PORTB RB0/INT RB1 RB2 RB3/PGM RB4 RB5 RB6/PGC RB7/PGD PORTC
RAM File Registers RAM Addr(1)
Program Bus
14 Instruction reg Direct Addr 7
Addr MUX 8 Indirect Addr
FSR reg STATUS reg 8 3
Power-up Timer Instruction Decode & Control Timing Generation OSC1/CLKIN OSC2/CLKOUT Oscillator Start-up Timer Power-on Reset Watchdog Timer Brown-out Reset In-Circuit Debugger Low-Voltage Programming 8
MUX
ALU
RC0/T1OSO/T1CKI RC1/T1OSI/CCP2 RC2/CCP1 RC3/SCK/SCL RC4/SDI/SDA RC5/SDO RC6/TX/CK RC7/RX/DT PORTD RD0/PSP0 RD1/PSP1 RD2/PSP2 RD3/PSP3 RD4/PSP4 RD5/PSP5 RD6/PSP6 RD7/PSP7 PORTE
W reg
Parallel Slave Port
MCLR
VDD, VSS
RE0/AN5/RD RE1/AN6/WR RE2/AN7/CS
Timer0
Timer1
Timer2
10-bit A/D
Data EEPROM
CCP1,2
Synchronous Serial Port
USART
Note 1: Higher order bits are from the STATUS register.
DS30292C-page 6
PIC16F87X
2.2 Data Memory Organization
The data memory is partitioned into multiple banks which contain the General Purpose Registers and the Special Function Registers. Bits RP1 (STATUS<6>) and RP0 (STATUS<5>) are the bank select bits. Each bank extends up to 7Fh (128 bytes). The lower locations of each bank are reserved for the Special Function Registers. Above the Special Function Registers are General Purpose Registers, implemented as static RAM. All implemented banks contain Special Function Registers. Some frequently used Special Function Registers from one bank may be mirrored in another bank for code reduction and quicker access. Note: EEPROM Data Memory description can be found in Section 4.0 of this data sheet.
RP1:RP0 00 01 10 11
Bank 0 1 2 3
2.2.1
GENERAL PURPOSE REGISTER FILE
The register file can be accessed either directly, or indirectly through the File Select Register (FSR).
DS30292C-page 12
PIC16F87X
FIGURE 2-3: PIC16F877/876 REGISTER FILE MAP
File Address Indirect addr.(*) TMR0 PCL STATUS FSR PORTA PORTB PORTC PORTD(1) PORTE(1) PCLATH INTCON PIR1 PIR2 TMR1L TMR1H T1CON TMR2 T2CON SSPBUF SSPCON CCPR1L CCPR1H CCP1CON RCSTA TXREG RCREG CCPR2L CCPR2H CCP2CON ADRESH ADCON0 00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0Ah 0Bh 0Ch 0Dh 0Eh 0Fh 10h 11h 12h 13h 14h 15h 16h 17h 18h 19h 1Ah 1Bh 1Ch 1Dh 1Eh 1Fh 20h Indirect addr.(*) OPTION_REG PCL STATUS FSR TRISA TRISB TRISC TRISD(1) TRISE(1) PCLATH INTCON PIE1 PIE2 PCON File Address 80h 81h 82h 83h 84h 85h 86h 87h 88h 89h 8Ah 8Bh 8Ch 8Dh 8Eh 8Fh 90h 91h 92h 93h 94h 95h 96h 97h 98h 99h 9Ah 9Bh 9Ch 9Dh 9Eh 9Fh A0h General Purpose Register 80 Bytes accesses 70h-7Fh 7Fh Bank 0 Bank 1 General Purpose Register 80 Bytes accesses 70h-7Fh Bank 2 Indirect addr.(*) TMR0 PCL STATUS FSR PORTB File Address 100h 101h 102h 103h 104h 105h 106h 107h 108h 109h 10Ah 10Bh 10Ch 10Dh 10Eh 10Fh 110h 111h 112h 113h 114h 115h 116h 117h 118h 119h 11Ah 11Bh 11Ch 11Dh 11Eh 11Fh 120h Indirect addr.(*) OPTION_REG PCL STATUS FSR TRISB File Address 180h 181h 182h 183h 184h 185h 186h 187h 188h 189h 18Ah 18Bh 18Ch 18Dh 18Eh 18Fh 190h 191h 192h 193h 194h 195h 196h 197h 198h 199h 19Ah 19Bh 19Ch 19Dh 19Eh 19Fh 1A0h
PCLATH INTCON EEDATA EEADR EEDATH EEADRH
PCLATH INTCON EECON1 EECON2 Reserved(2) Reserved(2)
SSPCON2 PR2 SSPADD SSPSTAT
TXSTA SPBRG
General Purpose Register 16 Bytes
ADRESL ADCON1
EFh F0h FFh
16Fh 170h 17Fh
General Purpose Register 80 Bytes accesses 70h - 7Fh Bank 3
1EFh 1F0h 1FFh
Unimplemented data memory locations, read as 0. * Not a physical register. Note 1: These registers are not implemented on the PIC16F876. 2: These registers are reserved, maintain these registers clear.
DS30292C-page 13
PIC16F87X
2.2.2 SPECIAL FUNCTION REGISTERS
The Special Function Registers are registers used by the CPU and peripheral modules for controlling the desired operation of the device. These registers are implemented as static RAM. A list of these registers is given in Table 2-1. The Special Function Registers can be classified into two sets: core (CPU) and peripheral. Those registers associated with the core functions are described in detail in this section. Those related to the operation of the peripheral features are described in detail in the peripheral features section.
TABLE 2-1:
Address Bank 0 00h(3) 01h 02h(3) 03h(3) 04h(3) 05h 06h 07h 08h(4) 09h(4) 0Ah(1,3) 0Bh(3) 0Ch 0Dh 0Eh 0Fh 10h 11h 12h 13h 14h 15h 16h 17h 18h 19h 1Ah 1Bh 1Ch 1Dh 1Eh 1Fh Legend: Note 1: 2: 3: 4: 5: INDF TMR0 PCL STATUS FSR PORTA PORTB PORTC PORTD PORTE PCLATH INTCON PIR1 PIR2 TMR1L TMR1H T1CON TMR2 T2CON SSPBUF SSPCON CCPR1L CCPR1H Name
SPECIAL FUNCTION REGISTER SUMMARY

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on: POR, BOR Details on page:
Addressing this location uses contents of FSR to address data memory (not a physical register) Timer0 Module Register Program Counter (PC) Least Significant Byte IRP RP1 RP0 TO PD Z DC C Indirect Data Memory Address Pointer PORTA Data Latch when written: PORTA pins when read PORTB Data Latch when written: PORTB pins when read PORTC Data Latch when written: PORTC pins when read PORTD Data Latch when written: PORTD pins when read GIE PSPIF(3) PEIE ADIF (5) T0IE RCIF INTE TXIF EEIF RBIE SSPIF BCLIF RE2 T0IF CCP1IF RE1 INTF TMR2IF RE0 RBIF TMR1IF CCP2IF Write Buffer for the upper 5 bits of the Program Counter
0000 0000 xxxx xxxx 0000 0000 0001 1xxx xxxx xxxx --0x 0000 xxxx xxxx xxxx xxxx xxxx xxxx ---- -xxx ---0 0000 0000 000x 0000 0000 -r-0 0--0 xxxx xxxx xxxx xxxx
27 47 26 18 27 29 31 33 35 36 26 20 22 24 52 52 51 55 55 70, 73 67 57 57 58 96 99 101 57 57 58 116 111
Holding register for the Least Significant Byte of the 16-bit TMR1 Register Holding register for the Most Significant Byte of the 16-bit TMR1 Register WCOL T1CKPS1 T1CKPS0 TOUTPS1 CKP T1OSCEN TOUTPS0 SSPM3 T1SYNC TMR2ON SSPM2 TMR1CS TMR1ON Timer2 Module Register TOUTPS3 TOUTPS2 SSPOV SSPEN Synchronous Serial Port Receive Buffer/Transmit Register SSPM1 SSPM0 Capture/Compare/PWM Register1 (LSB) Capture/Compare/PWM Register1 (MSB) SPEN RX9 CCP1X SREN CCP1Y CREN CCP1M3 ADDEN CCP1M2 FERR CCP1M1 OERR CCP1M0 RX9D
--00 0000 0000 0000
T2CKPS1 T2CKPS0 -000 0000

xxxx xxxx 0000 0000 xxxx xxxx xxxx xxxx --00 0000 0000 000x 0000 0000 0000 0000 xxxx xxxx xxxx xxxx
CCP1CON RCSTA TXREG RCREG CCPR2L CCPR2H CCP2CON ADRESH ADCON0
USART Transmit Data Register USART Receive Data Register Capture/Compare/PWM Register2 (LSB) Capture/Compare/PWM Register2 (MSB) ADCS1 ADCS0 CCP2X CHS2 CCP2Y CHS1 CCP2M3 CHS0 CCP2M2 GO/DONE CCP2M1 CCP2M0 ADON A/D Result Register High Byte
--00 0000 xxxx xxxx 0000 00-0
x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as '0', r = reserved. Shaded locations are unimplemented, read as 0. The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<12:8> whose contents are transferred to the upper byte of the program counter. Bits PSPIE and PSPIF are reserved on PIC16F873/876 devices; always maintain these bits clear. These registers can be addressed from any bank. PORTD, PORTE, TRISD, and TRISE are not physically implemented on PIC16F873/876 devices; read as 0. PIR2<6> and PIE2<6> are reserved on these devices; always maintain these bits clear.
DS30292C-page 15
PIC16F87X
TABLE 2-1:
Address Bank 1 80h(3) 81h 82h(3) 83h(3) 84h(3) 85h 86h 87h 88h(4) 89h(4) 8Ah(1,3) 8Bh(3) 8Ch 8Dh 8Eh 8Fh 90h 91h 92h 93h 94h 95h 96h 97h 98h 99h 9Ah 9Bh 9Ch 9Dh 9Eh 9Fh Legend: Note 1: 2: 3: 4: 5: INDF OPTION_REG PCL STATUS FSR TRISA TRISB TRISC TRISD TRISE PCLATH INTCON PIE1 PIE2 PCON SSPCON2 PR2 SSPADD SSPSTAT TXSTA SPBRG ADRESL ADCON1 Addressing this location uses contents of FSR to address data memory (not a physical register) RBPU IRP INTEDG RP1 T0CS RP0 T0SE TO PSA PD PS2 Z PS1 DC PS0 C Program Counter (PC) Least Significant Byte Indirect Data Memory Address Pointer PORTA Data Direction Register PORTB Data Direction Register PORTC Data Direction Register PORTD Data Direction Register IBF GIE PSPIE(2) OBF PEIE ADIE (5) IBOV T0IE RCIE PSPMODE INTE TXIE EEIE RBIE SSPIE BCLIE PORTE Data Direction Bits T0IF CCP1IE INTF TMR2IE POR RBIF TMR1IE CCP2IE BOR Write Buffer for the upper 5 bits of the Program Counter
0000 0000 1111 1111 0000 0000 0001 1xxx xxxx xxxx --11 1111 1111 1111 1111 1111 1111 1111 0000 -111 ---0 0000 0000 000x 0000 0000 -r-0 0--0 ---- --qq
SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)

Name
27 19 26 18 27 29 31 33 35 37 26 20 21 23 25 68 55 73, 74 66 95 97 116 112
Unimplemented Unimplemented GCEN ACKSTAT ACKDT ACKEN RCEN PEN RSEN SEN Timer2 Period Register Synchronous Serial Port (I2C mode) Address Register SMP CKE D/A P S R/W UA BF Unimplemented Unimplemented Unimplemented CSRC TX9 TXEN SYNC BRGH TRMT TX9D Baud Rate Generator Register Unimplemented Unimplemented Unimplemented Unimplemented A/D Result Register Low Byte ADFM PCFG3 PCFG2 PCFG1 PCFG0

0000 0000 1111 1111 0000 0000 0000 0000

0000 -010 0000 0000

xxxx xxxx 0--- 0000
DS30292C-page 16
PIC16F87X
TABLE 2-1:
Address Bank 2 100h(3) 101h 102h(3) 103h(3) 104h(3) 105h 106h 107h 108h 109h 10Ah(1,3) 10Bh(3) 10Ch 10Dh 10Eh 10Fh Bank 3 180h(3) 181h 182h(3) 183h(3) 184h(3) 185h 186h 187h 188h 189h 18Ah(1,3) 18Bh(3) 18Ch 18Dh 18Eh 18Fh Legend: Note 1: 2: 3: 4: 5: INDF OPTION_REG PCL STATUS FSR TRISB PCLATH INTCON EECON1 EECON2 Addressing this location uses contents of FSR to address data memory (not a physical register) RBPU IRP INTEDG RP1 T0CS RP0 T0SE TO PSA PD PS2 Z PS1 DC PS0 C Program Counter (PC) Least Significant Byte Indirect Data Memory Address Pointer Unimplemented PORTB Data Direction Register Unimplemented Unimplemented Unimplemented GIE EEPGD PEIE T0IE Write Buffer for the upper 5 bits of the Program Counter INTE RBIE WRERR T0IF WREN INTF WR RBIF RD
0000 0000 1111 1111 0000 0000 0001 1xxx xxxx xxxx
SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)

Name
INDF TMR0 PCL STATUS FSR PORTB PCLATH INTCON EEDATA EEADR EEDATH EEADRH
Addressing this location uses contents of FSR to address data memory (not a physical register) Timer0 Module Register Program Counters (PC) Least Significant Byte IRP RP1 RP0 TO PD Z DC C Indirect Data Memory Address Pointer Unimplemented PORTB Data Latch when written: PORTB pins when read Unimplemented Unimplemented Unimplemented GIE PEIE T0IE Write Buffer for the upper 5 bits of the Program Counter INTE RBIE T0IF INTF RBIF
0000 0000 xxxx xxxx 0000 0000 0001 1xxx xxxx xxxx
27 47 26 18 27 31 26 20 41 41 41 41 27 19 26 18 27 31 26 20 41, 42 41
xxxx xxxx

---0 0000 0000 000x xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx
EEPROM Data Register Low Byte EEPROM Address Register Low Byte EEPROM Data Register High Byte EEPROM Address Register High Byte
1111 1111

---0 0000 0000 000x x--- x000 ---- ---0000 0000 0000 0000
EEPROM Control Register2 (not a physical register) Reserved maintain clear Reserved maintain clear
DS30292C-page 17
PIC16F87X
2.2.2.1 STATUS Register
The STATUS register contains the arithmetic status of the ALU, the RESET status and the bank select bits for data memory. The STATUS register can be the destination for any instruction, as with any other register. If the STATUS register is the destination for an instruction that affects the Z, DC or C bits, then the write to these three bits is disabled. These bits are set or cleared according to the device logic. Furthermore, the TO and PD bits are not writable, therefore, the result of an instruction with the STATUS register as destination may be different than intended. For example, CLRF STATUS will clear the upper three bits and set the Z bit. This leaves the STATUS register as 000u u1uu (where u = unchanged). It is recommended, therefore, that only BCF, BSF, SWAPF and MOVWF instructions are used to alter the STATUS register, because these instructions do not affect the Z, C or DC bits from the STATUS register. For other instructions not affecting any status bits, see the Instruction Set Summary." Note: The C and DC bits operate as a borrow and digit borrow bit, respectively, in subtraction. See the SUBLW and SUBWF instructions for examples.
REGISTER 2-1:
STATUS REGISTER (ADDRESS 03h, 83h, 103h, 183h)

R/W-0 IRP bit 7 R/W-0 RP1 R/W-0 RP0 R-1 TO R-1 PD R/W-x Z R/W-x DC R/W-x C bit 0
bit 7
IRP: Register Bank Select bit (used for indirect addressing) 1 = Bank 2, 3 (100h - 1FFh) 0 = Bank 0, 1 (00h - FFh) RP1:RP0: Register Bank Select bits (used for direct addressing) 11 = Bank 3 (180h - 1FFh) 10 = Bank 2 (100h - 17Fh) 01 = Bank 1 (80h - FFh) 00 = Bank 0 (00h - 7Fh) Each bank is 128 bytes TO: Time-out bit 1 = After power-up, CLRWDT instruction, or SLEEP instruction 0 = A WDT time-out occurred PD: Power-down bit 1 = After power-up or by the CLRWDT instruction 0 = By execution of the SLEEP instruction Z: Zero bit 1 = The result of an arithmetic or logic operation is zero 0 = The result of an arithmetic or logic operation is not zero DC: Digit carry/borrow bit (ADDWF, ADDLW,SUBLW,SUBWF instructions) (for borrow, the polarity is reversed) 1 = A carry-out from the 4th low order bit of the result occurred 0 = No carry-out from the 4th low order bit of the result C: Carry/borrow bit (ADDWF, ADDLW,SUBLW,SUBWF instructions) 1 = A carry-out from the Most Significant bit of the result occurred 0 = No carry-out from the Most Significant bit of the result occurred Note: For borrow, the polarity is reversed. A subtraction is executed by adding the twos complement of the second operand. For rotate (RRF, RLF) instructions, this bit is loaded with either the high, or low order bit of the source register.
bit 6-5
bit 4
bit 3
bit 2
bit 1
bit 0
Legend: R = Readable bit - n = Value at POR W = Writable bit 1 = Bit is set U = Unimplemented bit, read as 0 0 = Bit is cleared x = Bit is unknown
DS30292C-page 18
PIC16F87X
3.3 PORTC and the TRISC Register
FIGURE 3-6:
PORTC is an 8-bit wide, bi-directional port. The corresponding data direction register is TRISC. Setting a TRISC bit (= 1) will make the corresponding PORTC pin an input (i.e., put the corresponding output driver in a Hi-Impedance mode). Clearing a TRISC bit (= 0) will make the corresponding PORTC pin an output (i.e., put the contents of the output latch on the selected pin). PORTC is multiplexed with several peripheral functions (Table 3-5). PORTC pins have Schmitt Trigger input buffers. When the I2C module is enabled, the PORTC<4:3> pins can be configured with normal I2C levels, or with SMBus levels by using the CKE bit (SSPSTAT<6>). When enabling peripheral functions, care should be taken in defining TRIS bits for each PORTC pin. Some peripherals override the TRIS bit to make a pin an output, while other peripherals override the TRIS bit to make a pin an input. Since the TRIS bit override is in effect while the peripheral is enabled, read-modifywrite instructions (BSF, BCF, XORWF) with TRISC as destination, should be avoided. The user should refer to the corresponding peripheral section for the correct TRIS bit settings.
PORTC BLOCK DIAGRAM (PERIPHERAL OUTPUT OVERRIDE) RC<4:3>
Port/Peripheral Select(2) Peripheral Data Out Data Bus WR Port D CK Q Q 1 0
VDD P I/O pin(1)
Data Latch WR TRIS D CK Q Q N Vss Schmitt Trigger Q D EN 0 Schmitt Trigger with SMBus levels
TRIS Latch RD TRIS Peripheral OE(3) RD Port SSPl Input 1 CKE SSPSTAT<6> Note 1: I/O pins have diode protection to VDD and VSS. 2: Port/Peripheral select signal selects between port data and peripheral output. 3: Peripheral OE (output enable) is only activated if peripheral select is active.
FIGURE 3-5:
PORTC BLOCK DIAGRAM (PERIPHERAL OUTPUT OVERRIDE) RC<2:0>, RC<7:5>
Port/Peripheral Select(2) Peripheral Data Out Data Bus WR Port

D CK Q Q
VDD P I/O pin(1)
Data Latch WR TRIS

D CK Q Q
N VSS Schmitt Trigger Q D EN
TRIS Latch RD TRIS Peripheral OE(3) RD Port Peripheral Input Note 1: I/O pins have diode protection to VDD and VSS. 2: Port/Peripheral select signal selects between port data and peripheral output. 3: Peripheral OE (output enable) is only activated if peripheral select is active.
DS30292C-page 33
PIC16F87X
TABLE 3-5:
Name RC0/T1OSO/T1CKI RC1/T1OSI/CCP2 RC2/CCP1 RC3/SCK/SCL RC4/SDI/SDA RC5/SDO RC6/TX/CK RC7/RX/DT
PORTC FUNCTIONS
Bit# bit0 bit1 bit2 bit3 bit4 bit5 bit6 bit7 Buffer Type ST ST ST ST ST ST ST ST Function Input/output port pin or Timer1 oscillator output/Timer1 clock input. Input/output port pin or Timer1 oscillator input or Capture2 input/ Compare2 output/PWM2 output. Input/output port pin or Capture1 input/Compare1 output/ PWM1 output. RC3 can also be the synchronous serial clock for both SPI and I2C modes. RC4 can also be the SPI Data In (SPI mode) or data I/O (I2C mode). Input/output port pin or Synchronous Serial Port data output. Input/output port pin or USART Asynchronous Transmit or Synchronous Clock. Input/output port pin or USART Asynchronous Receive or Synchronous Data.
Legend: ST = Schmitt Trigger input
TABLE 3-6:
Address 07h 87h
SUMMARY OF REGISTERS ASSOCIATED WITH PORTC

Bit 7 RC7 Bit 6 RC6 Bit 5 RC5 Bit 4 RC4 Bit 3 RC3 Bit 2 RC2 Bit 1 RC1 Bit 0 RC0 Value on: POR, BOR
xxxx xxxx 1111 1111
Name PORTC TRISC
Value on all other RESETS

uuuu uuuu 1111 1111
PORTC Data Direction Register
Legend: x = unknown, u = unchanged
DS30292C-page 34
PIC16F87X
REGISTER 11-2: ADCON1 REGISTER (ADDRESS 9Fh)
U-0 ADFM bit 7 bit 7 ADFM: A/D Result Format Select bit 1 = Right justified. 6 Most Significant bits of ADRESH are read as 0. 0 = Left justified. 6 Least Significant bits of ADRESL are read as 0. Unimplemented: Read as '0' PCFG3:PCFG0: A/D Port Configuration Control bits:
PCFG3: AN7(1) AN6(1) AN5(1) RE2 RE1 RE0 PCFG0
0000 0001 0010 0011 0100 0101 011x 1000 1001 1010 1011 1100 1101 1110 1111
U-0
R/W-0
U-0
R/W-0 PCFG3
R/W-0 PCFG2
R/W-0 PCFG1
R/W-0 PCFG0 bit 0
bit 6-4 bit 3-0
AN4 RA5 A A A A D D D A A A A A D D D
AN3 RA3 A VREF+ A VREF+ A VREF+ D VREF+ A VREF+ VREF+ VREF+ VREF+ D VREF+
AN2 RA2 A A A A D D D VREFA A VREFVREFVREFD VREF-
AN1 RA1 A A A A A A D A A A A A A D D
AN0 RA0 A A A A A A D A A A A A A A A
VREF+ VDD RA3 VDD RA3 VDD RA3 VDD RA3 VDD RA3 RA3 RA3 RA3 VDD RA3
VREFVSS VSS VSS VSS VSS VSS VSS RA2 VSS VSS RA2 RA2 RA2 VSS RA2
CHAN/ Refs(2) 8/0 7/1 5/0 4/1 3/0 2/1 0/0 6/2 6/0 5/1 4/2 3/2 2/2 1/0 1/2
A A D D D D D A D D D D D D D
A A D D D D D A D D D D D D D
A A D D D D D A A A A D D D D
A = Analog input
D = Digital I/O
Note 1: These channels are not available on PIC16F873/876 devices. 2: This column indicates the number of analog channels available as A/D inputs and the number of analog channels used as voltage reference inputs. Legend: R = Readable bit - n = Value at POR W = Writable bit 1 = Bit is set U = Unimplemented bit, read as 0 0 = Bit is cleared x = Bit is unknown
The ADRESH:ADRESL registers contain the 10-bit result of the A/D conversion. When the A/D conversion is complete, the result is loaded into this A/D result register pair, the GO/DONE bit (ADCON0<2>) is cleared and the A/D interrupt flag bit ADIF is set. The block diagram of the A/D module is shown in Figure 11-1. After the A/D module has been configured as desired, the selected channel must be acquired before the conversion is started. The analog input channels must have their corresponding TRIS bits selected as inputs.
To determine sample time, see Section 11.1. After this acquisition time has elapsed, the A/D conversion can be started.
DS30292C-page 112
PIC16F87X
13.0 INSTRUCTION SET SUMMARY
Each PIC16F87X instruction is a 14-bit word, divided into an OPCODE which specifies the instruction type and one or more operands which further specify the operation of the instruction. The PIC16F87X instruction set summary in Table 13-2 lists byte-oriented, bit-oriented, and literal and control operations. Table 13-1 shows the opcode field descriptions. For byte-oriented instructions, f represents a file register designator and d represents a destination designator. The file register designator specifies which file register is to be used by the instruction. The destination designator specifies where the result of the operation is to be placed. If d is zero, the result is placed in the W register. If d is one, the result is placed in the file register specified in the instruction. For bit-oriented instructions, b represents a bit field designator which selects the number of the bit affected by the operation, while f represents the address of the file in which the bit is located. For literal and control operations, k represents an eight or eleven bit constant or literal value. All instructions are executed within one single instruction cycle, unless a conditional test is true or the program counter is changed as a result of an instruction. In this case, the execution takes two instruction cycles with the second cycle executed as a NOP. One instruction cycle consists of four oscillator periods. Thus, for an oscillator frequency of 4 MHz, the normal instruction execution time is 1 s. If a conditional test is true, or the program counter is changed as a result of an instruction, the instruction execution time is 2 s. Table 13-2 lists the instructions recognized by the MPASMTM assembler. Figure 13-1 shows the general formats that the instructions can have. Note: To maintain upward compatibility with future PIC16F87X products, do not use the OPTION and TRIS instructions.
All examples use the following format to represent a hexadecimal number: 0xhh where h signifies a hexadecimal digit.
FIGURE 13-1: TABLE 13-1:

Field
f W b k x
OPCODE FIELD DESCRIPTIONS

Description
GENERAL FORMAT FOR INSTRUCTIONS

0
Byte-oriented file register operations 13 8 7 6 OPCODE d f (FILE #) d = 0 for destination W d = 1 for destination f f = 7-bit file register address Bit-oriented file register operations 13 10 9 7 6 OPCODE b (BIT #) b = 3-bit bit address f = 7-bit file register address Literal and control operations General 13 OPCODE k = 8-bit immediate value CALL and GOTO instructions only 13 11 OPCODE 10 k (literal) 8 7 k (literal)
Register file address (0x00 to 0x7F) Working register (accumulator) Bit address within an 8-bit file register Literal field, constant data or label Don't care location (= 0 or 1). The assembler will generate code with x = 0. It is the recommended form of use for compatibility with all Microchip software tools. Destination select; d = 0: store result in W, d = 1: store result in file register f. Default is d = 1. Program Counter Time-out bit Power-down bit
0 f (FILE #)
PC TO PD
The instruction set is highly orthogonal and is grouped into three basic categories: Byte-oriented operations Bit-oriented operations Literal and control operations
k = 11-bit immediate value
A description of each instruction is available in the PICmicro Mid-Range Reference Manual, (DS33023).
DS30292C-page 135
PIC16F87X
TABLE 13-2:
Mnemonic, Operands
PIC16F87X INSTRUCTION SET

14-Bit Opcode Description Cycles MSb BYTE-ORIENTED FILE REGISTER OPERATIONS LSb Status Affected Notes
ADDWF ANDWF CLRF CLRW COMF DECF DECFSZ INCF INCFSZ IORWF MOVF MOVWF NOP RLF RRF SUBWF SWAPF XORWF
f, d f, d f f, d f, d f, d f, d f, d f, d f, d f f, d f, d f, d f, d f, d
Add W and f AND W with f Clear f Clear W Complement f Decrement f Decrement f, Skip if 0 Increment f Increment f, Skip if 0 Inclusive OR W with f Move f Move W to f No Operation Rotate Left f through Carry Rotate Right f through Carry Subtract W from f Swap nibbles in f Exclusive OR W with f
1 1 1 1 1 1 1(2) 1 1(2) 1 1 1 1 1 1 1 1 1
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0111 0101 0001 0001 1001 0011 1011 1010 1111 0100 1000 0000 0000 1101 1100 0010 1110 0110
dfff dfff lfff 0xxx dfff dfff dfff dfff dfff dfff dfff lfff 0xx0 dfff dfff dfff dfff dfff
ffff ffff ffff xxxx ffff ffff ffff ffff ffff ffff ffff ffff 0000 ffff ffff ffff ffff ffff
C,DC,Z Z Z Z Z Z Z Z Z
1,2 1,2 2 1,2 1,2 1,2,3 1,2 1,2,3 1,2 1,2
C C C,DC,Z Z
1,2 1,2 1,2 1,2 1,2
BIT-ORIENTED FILE REGISTER OPERATIONS BCF BSF BTFSC BTFSS ADDLW ANDLW CALL CLRWDT GOTO IORLW MOVLW RETFIE RETLW RETURN SLEEP SUBLW XORLW f, b f, b f, b f, b k k k k k k k k k Bit Clear f Bit Set f Bit Test f, Skip if Clear Bit Test f, Skip if Set Add literal and W AND literal with W Call subroutine Clear Watchdog Timer Go to address Inclusive OR literal with W Move literal to W Return from interrupt Return with literal in W Return from Subroutine Go into standby mode Subtract W from literal Exclusive OR literal with W 1 1 1 (2) 1 (2) 1 1 2 1 2 1 1 2 2 2 1 1 1
01 01 01 01 11 11 10 00 10 11 11 00 11 00 00 11 11 00bb 01bb 10bb 11bb 111x 1001 0kkk 0000 1kkk 1000 00xx 0000 01xx 0000 0000 110x 1010 bfff bfff bfff bfff kkkk kkkk kkkk 0110 kkkk kkkk kkkk 0000 kkkk 0000 0110 kkkk kkkk ffff ffff ffff ffff kkkk kkkk kkkk 0100 kkkk kkkk kkkk 1001 kkkk 1000 0011 kkkk kkkk
1,2 1,2 3 3 C,DC,Z Z TO,PD Z
LITERAL AND CONTROL OPERATIONS
TO,PD C,DC,Z Z
Note 1: When an I/O register is modified as a function of itself ( e.g., MOVF PORTB, 1), the value used will be that value present on the pins themselves. For example, if the data latch is 1 for a pin configured as input and is driven low by an external device, the data will be written back with a 0. 2: If this instruction is executed on the TMR0 register (and, where applicable, d = 1), the prescaler will be cleared if assigned to the Timer0 module. 3: If Program Counter (PC) is modified, or a conditional test is true, the instruction requires two cycles. The second cycle is executed as a NOP.
Note:
Additional information on the mid-range instruction set is available in the PICmicro Mid-Range MCU Family Reference Manual (DS33023).
DS30292C-page 136
PIC16F87X
13.1
ADDLW Syntax: Operands: Operation: Status Affected: Description:
Instruction Descriptions
Add Literal and W [label] ADDLW 0 k 255 (W) + k (W) C, DC, Z The contents of the W register are added to the eight bit literal k and the result is placed in the W register. Operation: Status Affected: Description: k BCF Syntax: Operands: Bit Clear f [label] BCF 0 f 127 0b7 0 (f<b>) None Bit 'b' in register 'f' is cleared. f,b
ADDWF Syntax: Operands: Operation: Status Affected: Description:
Add W and f [label] ADDWF 0 f 127 d [0,1] (W) + (f) (destination) C, DC, Z Add the contents of the W register with register f. If d is 0, the result is stored in the W register. If d is 1, the result is stored back in register f. f,d
BSF Syntax: Operands: Operation: Status Affected: Description:
Bit Set f [label] BSF 0 f 127 0b7 1 (f<b>) None Bit 'b' in register 'f' is set. f,b
ANDLW Syntax: Operands: Operation: Status Affected: Description:
AND Literal with W [label] ANDLW 0 k 255 (W) .AND. (k) (W) Z The contents of W register are ANDed with the eight bit literal 'k'. The result is placed in the W register. k
BTFSS Syntax: Operands: Operation: Status Affected: Description:
Bit Test f, Skip if Set [label] BTFSS f,b 0 f 127 0b<7 skip if (f<b>) = 1 None If bit 'b' in register 'f' is '0', the next instruction is executed. If bit 'b' is '1', then the next instruction is discarded and a NOP is executed instead, making this a 2TCY instruction.
ANDWF Syntax: Operands: Operation: Status Affected: Description:
AND W with f [label] ANDWF 0 f 127 d [0,1] (W) .AND. (f) (destination) Z AND the W register with register 'f'. If 'd' is 0, the result is stored in the W register. If 'd' is 1, the result is stored back in register 'f'. f,d
BTFSC Syntax: Operands: Operation: Status Affected: Description:
Bit Test, Skip if Clear [label] BTFSC f,b 0 f 127 0b7 skip if (f<b>) = 0 None If bit 'b' in register 'f' is '1', the next instruction is executed. If bit 'b', in register 'f', is '0', the next instruction is discarded, and a NOP is executed instead, making this a 2TCY instruction.
DS30292C-page 137
PIC16F87X
CALL Syntax: Operands: Operation: Call Subroutine [ label ] CALL k 0 k 2047 (PC)+ 1 TOS, k PC<10:0>, (PCLATH<4:3>) PC<12:11> None Call Subroutine. First, return address (PC+1) is pushed onto the stack. The eleven-bit immediate address is loaded into PC bits <10:0>. The upper bits of the PC are loaded from PCLATH. CALL is a two-cycle instruction. Status Affected: Description: CLRWDT Syntax: Operands: Operation: Clear Watchdog Timer [ label ] CLRWDT None 00h WDT 0 WDT prescaler, 1 TO 1 PD TO, PD CLRWDT instruction resets the Watchdog Timer. It also resets the prescaler of the WDT. Status bits TO and PD are set.
Status Affected: Description:
CLRF Syntax: Operands: Operation: Status Affected: Description:
Clear f [label] CLRF 0 f 127 00h (f) 1Z Z The contents of register f are cleared and the Z bit is set. f
COMF Syntax: Operands: Operation: Status Affected: Description:
Complement f [ label ] COMF 0 f 127 d [0,1] (f) (destination) Z The contents of register f are complemented. If d is 0, the result is stored in W. If d is 1, the result is stored back in register f. f,d
CLRW Syntax: Operands: Operation: Status Affected: Description:
Clear W [ label ] CLRW None 00h (W) 1Z Z W register is cleared. Zero bit (Z) is set.
DECF Syntax: Operands: Operation: Status Affected: Description:
Decrement f [label] DECF f,d 0 f 127 d [0,1] (f) - 1 (destination) Z Decrement register f. If d is 0, the result is stored in the W register. If d is 1, the result is stored back in register f.
DS30292C-page 138
PIC16F87X
DECFSZ Syntax: Operands: Operation: Status Affected: Description: Decrement f, Skip if 0 [ label ] DECFSZ f,d 0 f 127 d [0,1] (f) - 1 (destination); skip if result = 0 None The contents of register f are decremented. If d is 0, the result is placed in the W register. If d is 1, the result is placed back in register f. If the result is 1, the next instruction is executed. If the result is 0, then a NOP is executed instead making it a 2TCY instruction. INCFSZ Syntax: Operands: Operation: Status Affected: Description: Increment f, Skip if 0 [ label ] INCFSZ f,d 0 f 127 d [0,1] (f) + 1 (destination), skip if result = 0 None The contents of register f are incremented. If d is 0, the result is placed in the W register. If d is 1, the result is placed back in register f. If the result is 1, the next instruction is executed. If the result is 0, a NOP is executed instead, making it a 2TCY instruction.
GOTO Syntax: Operands: Operation: Status Affected: Description:
Unconditional Branch [ label ] GOTO k 0 k 2047 k PC<10:0> PCLATH<4:3> PC<12:11> None GOTO is an unconditional branch. The eleven-bit immediate value is loaded into PC bits <10:0>. The upper bits of PC are loaded from PCLATH<4:3>. GOTO is a twocycle instruction.
IORLW Syntax: Operands: Operation: Status Affected: Description:
Inclusive OR Literal with W [ label ] IORLW k 0 k 255 (W) .OR. k (W) Z The contents of the W register are ORed with the eight bit literal 'k'. The result is placed in the W register.
INCF Syntax: Operands: Operation: Status Affected: Description:
Increment f [ label ] INCF f,d 0 f 127 d [0,1] (f) + 1 (destination) Z The contents of register f are incremented. If d is 0, the result is placed in the W register. If d is 1, the result is placed back in register f.
IORWF Syntax: Operands: Operation: Status Affected: Description:
Inclusive OR W with f [ label ] IORWF f,d 0 f 127 d [0,1] (W) .OR. (f) (destination) Z Inclusive OR the W register with register 'f'. If 'd' is 0 the result is placed in the W register. If 'd' is 1 the result is placed back in register 'f'.
DS30292C-page 139
PIC16F87X
MOVF Syntax: Operands: Operation: Status Affected: Description: Move f [ label ] MOVF f,d 0 f 127 d [0,1] (f) (destination) Z The contents of register f are moved to a destination dependant upon the status of d. If d = 0, destination is W register. If d = 1, the destination is file register f itself. d = 1 is useful to test a file register, since status flag Z is affected. NOP Syntax: Operands: Operation: Status Affected: Description: No Operation [ label ] None No operation None No operation. NOP
MOVLW Syntax: Operands: Operation: Status Affected: Description:
Move Literal to W [ label ] k (W) None The eight bit literal k is loaded into W register. The dont cares will assemble as 0s. MOVLW k 0 k 255
RETFIE Syntax: Operands: Operation: Status Affected:
Return from Interrupt [ label ] None TOS PC, 1 GIE None RETFIE
MOVWF Syntax: Operands: Operation: Status Affected: Description:
Move W to f [ label ] (W) (f) None Move data from W register to register 'f'. MOVWF f 0 f 127
RETLW Syntax: Operands: Operation: Status Affected: Description:
Return with Literal in W [ label ] RETLW k 0 k 255 k (W); TOS PC None The W register is loaded with the eight bit literal 'k'. The program counter is loaded from the top of the stack (the return address). This is a two-cycle instruction.
DS30292C-page 140
PIC16F87X
RLF Syntax: Operands: Operation: Status Affected: Description: Rotate Left f through Carry [ label ] RLF 0 f 127 d [0,1] See description below C The contents of register f are rotated one bit to the left through the Carry Flag. If d is 0, the result is placed in the W register. If d is 1, the result is stored back in register f.
C Register f
SLEEP Syntax: Operands: Operation: [ label ] SLEEP None 00h WDT, 0 WDT prescaler, 1 TO, 0 PD TO, PD The power-down status bit, PD is cleared. Time-out status bit, TO is set. Watchdog Timer and its prescaler are cleared. The processor is put into SLEEP mode with the oscillator stopped.
f,d
Status Affected: Description:
RETURN Syntax: Operands: Operation: Status Affected: Description:
Return from Subroutine [ label ] None TOS PC None Return from subroutine. The stack is POPed and the top of the stack (TOS) is loaded into the program counter. This is a two-cycle instruction. RETURN
SUBLW Syntax: Operands: Operation: Description:
Subtract W from Literal [ label ] SUBLW k 0 k 255 k - (W) (W) The W register is subtracted (2s complement method) from the eight-bit literal 'k'. The result is placed in the W register.
Status Affected: C, DC, Z
RRF Syntax: Operands: Operation: Status Affected: Description:
Rotate Right f through Carry [ label ] RRF f,d 0 f 127 d [0,1] See description below C The contents of register f are rotated one bit to the right through the Carry Flag. If d is 0, the result is placed in the W register. If d is 1, the result is placed back in register f.
C Register f
SUBWF Syntax: Operands: Operation: Status Affected: Description:
Subtract W from f [ label ] SUBWF f,d 0 f 127 d [0,1] (f) - (W) (destination) C, DC, Z Subtract (2s complement method) W register from register 'f'. If 'd' is 0, the result is stored in the W register. If 'd' is 1, the result is stored back in register 'f'.
DS30292C-page 141
PIC16F87X
SWAPF Syntax: Operands: Operation: Status Affected: Description: Swap Nibbles in f [ label ] SWAPF f,d 0 f 127 d [0,1] (f<3:0>) (destination<7:4>), (f<7:4>) (destination<3:0>) None The upper and lower nibbles of register f are exchanged. If d is 0, the result is placed in the W register. If d is 1, the result is placed in register f. XORWF Syntax: Operands: Operation: Status Affected: Description: Exclusive OR W with f [label] XORWF f,d 0 f 127 d [0,1] (W) .XOR. (f) (destination) Z Exclusive OR the contents of the W register with register 'f'. If 'd' is 0, the result is stored in the W register. If 'd' is 1, the result is stored back in register 'f'.
XORLW Syntax: Operands: Operation: Status Affected: Description:
Exclusive OR Literal with W [label] XORLW k 0 k 255 (W) .XOR. k (W) Z The contents of the W register are XORed with the eight-bit literal 'k'. The result is placed in the W register.
DS30292C-page 142

Eval Programmation Complete

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Evaluation programmation Partie 1 : questionnement crit (9 pages) Partie 2 : questionnement TP (10 pages) Partie 3 : document ressource (4 pages) Partie

4 : extrait documentation constructeur PIC16F877

Evaluation programmation Partie 1 Questionnement crit

Sige 406 Evaluation programmation Questionnement de la partie crite

I.2 Programme principal

Test VAR_GV=1 : VAR_GV est le bit0 de la variable 8 bits VAR_GRANDE_VIT :

Test BP_MVT_SENS actifs On dcomposera ce test de cette manire.

W=$FF BP_MVT_SENS actifs ? OUI Z=0 ? OUI NON NON PORTC-W

Sige 406 Evaluation programmation Questionnement de la partie crite

II Analyse de la version en langage C II.1 Etude du sous programme detect_sens

Sige 406 Evaluation programmation Questionnement de la partie crite

Les oprateurs logiques bit bit :

Les oprateurs de tests conditionnels :

II.3 Etude du sous programme dec_pos_gli

Sige 406 Evaluation programmation Questionnement de la partie crite DOCUMENT REPONSE 1

Sige 406 Evaluation programmation Questionnement de la partie crite DOCUMENT REPONSE 2

;*********************************************************************** ;* partie complter : configuration du PORTA et PORTE * ;***********************************************************************

RETURN G BERTHOME Page 7/9

Sige 406 Evaluation programmation Questionnement de la partie crite DOCUMENT REPONSE 3

Sige 406 Evaluation programmation Questionnement de la partie crite

Evaluation programmation Partie 2 Questionnement TP

Sige 406 Evaluation programmation Questionnement de la partie TP I Cration du projet

Sige 406 Evaluation programmation Questionnement de la partie TP

III.1 Initialisation des entres

Sige 406 Evaluation programmation Questionnement de la partie TP

Sige 406 Evaluation programmation Questionnement de la partie TP

Sige 406 Evaluation programmation Questionnement de la partie TP DOCUMENT REPONSE 1

CAPT_GLI CAPT_REHA CAPT_SITE CAPT_DOS

IMA_ACC FC_AV FC_AR

Evaluation programmation Partie 3 Document ressource

Evaluation programmation Document ressource

GR_VIT, COM_GLI_AV, COM_GLI_AR, VAR_GV

BP_MVT_SENS actifs ? OUI VAR_DEP=$01 detect_sens

VAR_DEP=$01 ? OUI DIR mem_pos_cour VAR_DEP=$00

IMA_ACC1 ? NON BP_M=0 ? OUI memo POS_MVT_MEM1, POS_MVT_MEM2, COM_BUZ

BP_CONDUCT1=0 ? OUI rappel1 COM_MVT_SENS, COM_BUZ

BP_CONDUCT2=0 ? OUI rappel2 COM_MVT_SENS, COM_BUZ FIN

Evaluation programmation Document ressource

BP_GLI_AV=0 ? OUI DIR_GLI=1

BP_GLI_AR=0 ? OUI DIR_GLI=0

BP_REHA_MONT =0? OUI DIR_REHA=1

BP_REHA_DESC =0? OUI DIR_REHA=0

BP_SITE_MONT =0? OUI DIR_SITE=1

BP_SITE_DESC =0? OUI DIR_SITE=0

BP_DOS_AV=0 ? OUI DIR_DOS=1

BP_DOS_AR=0 ? OUI DIR_DOS=0

Evaluation programmation Document ressource

bit 7 de CHANG_CAPT bit 7 de MEM_CAPT ? OUI DIR_DOS=0 ? OUI dec_pos_dos NON

inc_pos_gli Mmoriser les nouveaux tats des capteurs MEM_CAPT=CHANG_CAPT

bit 5 de CHANG_CAPT bit 5 de MEM_CAPT ? OUI DIR_REHA=0 ? OUI dec_pos_reha NON

bit 6 de CHANG_CAPT bit 6 de MEM_CAPT ? OUI DIR_SITE=0 ? OUI dec_pos_site NON

Evaluation programmation Document ressource

BP_M=0 ? OUI BP_M=0 ET BP_CONDUCT1=0 ? OUI mem1 FIN_MEMO=1 prod_sign_sonore

BP_M=0 OU BP_CONDUCT1=0 ? NON

Evaluation programmation Partie 4 Documentation constructeur PIC16F877

Microcontroller Core Features:

2001 Microchip Technology Inc.

PIC16F874 AND PIC16F877 BLOCK DIAGRAM

Data EEPROM 128 Bytes 256 Bytes

RAM File Registers RAM Addr(1)

14 Instruction reg Direct Addr 7

Addr MUX 8 Indirect Addr

FSR reg STATUS reg 8 3

Parallel Slave Port