36

COPYBIT ELIMINATOR REVISITED

Design by H. Schaake The circuit
The circuit of the original version has been complemented with an IC (by using a MACH210 in the IC1 position), a couple of resistors, some jumpers, and a capacitor see F i g . 1. The MACH210 is equivalent to two MACH110s (used in the earlier version), These chips are identical as far as housing is concerned. The operation of the updated eliminator is identical to that of the earlier version: the reader is therefore referred to the earlier article for background information, block schematic and timing diagram. ur February 1994 issue carried an article describing an inexpensive and straightforward circuit for eliminating the copybit from a digital S/PDIF* audio signal to enable users to copy (digitally) their own musical work many times without degradation by the SCMS**. The present article describes an updated version of that circuit, which can be used with the latest DAT, DCC and MD players.

Contents
W A R N I N G. The information in this article is intended solely for the recording, processing and copying of private musical work. The Editor and Publishers disclaim all responsibility for its use that infringes any copyright vested in commercial compacts discs and (digital) tape cassettes.

A comparison
The integrated circuits used in digital recorders fulfil more and more functions. Even the until recently discrete S / PDIF buffer/amplifier which converts the S/PDIF signal to TTL level is integrated in modern equipment. This is a good thing, of course, since fewer ICs bring the cost, and thus the price to the consumer, down. The original eliminator needed a TTL signal at its input, but the updated version contains a separate S/PDIF buffer amplifier. However, the design allows S / PDIF signals already at TTL level to be processed without any difficulty. The IC s used in modern recorders are faster and run at a higher master-clock frequency than those produced only a few years ago. Nowadays, a 256fs master clock is quite normal, and even 384 f s and 512 f s models are in production. Since the eliminator needs a 128fs clock, a binary scaler is provided in the updated version. If a 128fs clock is available in the recorder and this can be used, it should be preferred: experience shows that this enables some recorders to lock on more readily. The present version provides a choice of using either a LOCK or an UNLOCK signal and the facility of inverting the clock if required. These options may be useful for modifying types of DAT , DCC or MD recorder that have not been considered by the designer. The copybit indication outputs, COPYIN and COPYOU , can not only drive LED s directly, but may be used, if a copybit is present, as a block (=192 frames) trigger. This allows the S/PDIF signal to be inspected on an oscilloscope at or near the timing-slot position of the copybit frame.

chamfered to indicate how the chip should be located in the relevant IC socket. Header K1 is signal-compatible with the earlier version. A length of flatcable (keep this as short as possible) terminated into a 10-pin connector links the circuit with the appropriate points in the recorder. Switch S 1 enables the eliminator to be switched on and off as required. Thus, if the eliminator is intended to be in circuit at all times, the switch may be omitted.

Building into a recorder

Selecting between CLK and CLK , UNLK and LOCK, and 128fs and 256fs is by means of jumpers. The table on the next page gives connection data for a number of modern recorders; these data may also prove useful with recorders not specified. The selection between CLK and CLK is not given; this must be determined empirically, since

Construction
The printed-circuit board in F i g . 3 has been kept small to facilitate its incorporation into a recorder. Population of the board is straightforward. The MACH210 is housed in a PLCC case. One of the four corners has been

* Sony/Philips Digital Interface Format the consumer version of the AES/EBU standard. This standard was devised by the American Audio Engineering Society and the European Broadcasting Union to define the signal format, electrical characteristics and connectors to be used for digital interfaces between professional audio products. ** Serial Copy Management System.
ELEKTOR ELECTRONICS SEPTEMBER 1995

COPYBIT ELIMINATOR REVISITED

37

Contents
12

1 IC2f

13

IC2e
11

IC2c
10 5

5V

6 R1

K1
1 CLK 2 UNLK 3 RX OUT 4 RX IN 5 REC/P 6 VCC 7 GND 8 COPY IN 9 COPY OUT 10 GND 9

IC2d 1
8 CLK CLK

8k2

C4 100n 22 32 44 10

it depends on other connections. This involves nothing more than reversing the jumper and seeing whether the recorder locks or does not lock to the digital audio data of the eliminator. If the connections of a particular recorder are not given, order a service manual in which these can normally be found. A typical interconnection diagram of the signal source, the updated copybit eliminator and a digital recorder is given in F i g . 2.
24 S1 11

REC COPYIN1 COPYIN2 COPYIN3

UNLK

LOCK R3 R8 R7 1k8 1k8 1k8 2 42 25

IC1
SPDIFOUT

Pin signals
P i n 1 (C L K). This is either 128fs or 256fs, depending on the position of jumper 128/256. A jumper at CLK gives an inverted clock signal; at CLK, it gives a direct clock signal. P i n 2 (U N L K). This gives the PLL lock indication. The signal must be low when the PLL is locked (jumper at UNLK). If the opposite is the case, set the jumper in position LOCK. P i n 3 ( R X O U T ) . The relevant track on the board is broken before or after the coaxial/optical S/PDIF input buffer, depending on the accessibility of these points in the recorder. The part of the track from the input bus or the output of the buffer is linked to RXIN and the other part to RXOUT. P i n 4 (R X I N). See text for pin 3. P i n 5 (R E C/ P ). The record indication signal is connected to this pin (high level when the equipment is recording). P i n 6 . ( V C C ) . Supply voltage (+5 V) tapped from the recorder. P i n 7 (G N D). Link to ground of recorder. P i n s 8 , 9 , 1 0 are for connecting remotely sited LEDs. The signals may also be used as block trigger for inspecting the S/PDIF signal on an oscilloscope (only possible when the copybit is present in the input signal).

ON/OFF

SPDIF2
R4 D1 L1 D2 R5 R6 1mH 1k8 1k8 1k8 3 4 5 COPYOUT1 COPYOUT2 COPYOUT3 FCK1 20 21 C3 33 R9 10k 1 12 23 34 128FS UNLK SPDIFIN FCK2 /128FS 13 41 R2 8k2 950084 - 11 35 256 128 //128FS 6

5V IC2 = 74HCU04 5V
10 16V C2 100n 14

IC2a
C1 47n 1

IC2b
2 3

IC2
7

R10 27k

Fig. 1. Circuit diagram of the updated copybit eliminator.

COPYBIT KILLER II
256 RX IN 128

1 2

CLK UNLK

DIGITAL RECORDER

3 RX OUT 5 REC/P VCC GND +5V DIG.

CLK CLK 6 UNLK LOCK 7 10

S/PDIF OR DIGITAL SIGNAL

Parts list
950084-12

8 COPY IN

9 COPY OUT

R e s i s t o r s: R1, R2 = 8.2 k R3R8 = 1.8 k R5 = 27 k R9 = 10 k C a p a c i t o r s:

Fig. 2. Interconnection diagram of the signal source, the updated copybit eliminator and the recorder.

LOCK CLK C2 UNLK CLK

S1

C4

D1 D2 256 128 R6 R5 R4 R3 R8 R7 950084-1

L1

R1

10 9

2 1 K1 C1

R9 R10

1-480059

950084-1

Fig. 3. Printed-circuit board for the updated copybit eliminator.

ELEKTOR ELECTRONICS SEPTEMBER 1995

C3

IC2

R2

IC1

38

AUDIO & HI-FI

Contents
C1 = 47 nF C2, C4 = 100 nF C3 = 10 F, 16 V S e m i c o n d u c t o r s: D1 = LED, 3 mm, yellow D2 = LED, 3 mm, red I n t e g r a t e d c i r c u i t s: IC1 = MACH210 (Order no. 956504-1 see p. 70) IC2 = 74HCU04 I n d u c t o r s: L1 = 1 mH M i s c e l l a n e o u s: K1 = 10-way right-angle box header S1 = switch with single make contact PCB Order no. 950084 (see p. 70)
The board and IC may be ordered as a 1

package: Order no.950084-C [950084]

K1 pin no.

Connect in recorder to

Remarks

Jumpers on PCB

S o n y M D S-1 0 1 (MD recorder) 1 (CLK) 2 (UNLK) 3 (RXOUT) 4 (RXIN) 5 (REC/P) 6 (VCC) 7 (GND) IC510 pin 21 (128fs) or IC505 pin 6 (256fs) IC103 pin 5 IC103 pin 65 CNP103 (connector) pin 4 IC111 pin 70 CNP103 pin 7 CNP103 pin 6 128 256
LOCK

break track between through metallization and connector

P h i l i p s D C C-9 0 0 (DCC recorder) 1 (CLK) Q441 pin 26 (256fs) Q441 pin 9 2 (UNLK) 3 (RXOUT) coaxial: J421 (connector) pin 7 optical: J421 (connector) pin 3 signal side of C457 (150 pF) 4 (RXIN) 5 (REC/P) not known 6 (VCC) J421 (connector) pin 25 J421 (connector) pin 4 7 (GND) S o n y D T C-5 9 E S (DAT recorder) 1 (CLK) IC307 pin 58 (128fs) IC307 pin 31 2 (UNLK) 3 (RXOUT) IC302 pin 6 IC301 pin 8 4 (RXIN) IC309 pin 9 5 (REC/P) IC322 pin 3 6 (VCC) 7 (GND) chassis S o n y D T C-6 9 0 (DAT recorder) 1 (CLK) R320 (256fs) eponymous wire bridge 2 (UNLK) 3 (RXOUT) IC302 pin 6 R316 at side of IC302 4 (RXIN) not known 5 (REC/P) 6 (VCC) eponymous wire bridge eponymous wire bridge 7 (GND) S o n y D T C-7 5 0 E S (DAT recorder) 1 (CLK) IC307 pin 58 (128fs) IC307 pin 31 2 (UNLK) 3 (RXOUT) IC307 pin 52 IC301 pin 8 4 (RXIN) IC309 pin 8 5 (REC/P) IC322 pin 3 6 (VCC) 7 (GND) chassis

256
UNLK

at mother board side at mother board side break track to J421 link to VCC

128
UNLK

break track to this pin fit heat sink on to IC

256
UNLK

disconnect resistor at IC302 side link to VCC

128
UNLK

break track to this pin fit heat sink on to IC

Connections between K1 and relevant points in various recorders.

ELEKTOR ELECTRONICS SEPTEMBER 1995