Murdocca en Español

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Chapter 1: Introduction
Principios de Arquitectura de Computadoras

Miles Murdocca y Vincent Heuring
Capitulo 1: Introduccin
Principios de Arquitectura de Computadoras por M. Murdocca and V. Heuring
1999 M. Murdocca and V. Heuring
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Contenido del Captulo

1.1 Introduccin. Planteo General 1.2 Una Breve Historia 1.3 El modelo de Von Neumann 1.4 El Modelo de Interconexin a travs de Bus 1.5 Niveles de Mquina 1.6 Compatibilidad hacia Arriba 1.7 Los Niveles 1.8 Un Sistema de Computacin Tpico
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Algunas Definiciones
La Arquitectura de computadoras trata sobre el comportamiento funcional de un sistema de computacin visto por un programador (en aspectos tales como que un nmero entero ocupa 32 bits).
La organizacin de computadoras muestra relaciones estructurales no visibles para un programador (tales como la frecuencia de reloj o el tamao fsico de la memoria).
Existe un concepto de niveles en la arquitectura de computadoras. La idea es que una computadoras bsica puede estudiarse en base a diferentes niveles. Desde el nivel alto en el que el usuario corre programas, al nivel mas bajo, donde existen transistores y cables.
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Maquina calculadora de Pascal

Realizaba operaciones aritmticas bsicas(a mediados del 1600). No tena elementos bsicos para considerarla una computadora. Recin despues que Babbage (1800) introdujo los conceptos de control y clculo mecnico en una misma mquina se pudo reconocer en ellas partes bsicas de una computadora digital actual.
(Fuente: IBM Fotografa de Archivo.
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El Modelo de von Neumann

El modelo de Von Neumann est formado por 5 elementos principales: (1) unidad de entrada; (2) unidad de salida; (3) unidad aritmtico-lgica (4) unidad de memoria; (5) unidad de control.
Unidad de Memoria
U.de Entrada
Unidad de Aritmetica y logica(ALU)
U.de Salida
U.de Control
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El modelo de Interconexin de Bus

Una mejora al modelo de von Neumann, es el modelo de bus que tiene una CPU (ALU y control), memoria, y unidades entrada/salida. La Comunicacin entre componentes es manejada por un camino compartido llamado bus del sistema, formado por los buses de datos, direcciones, y control. Tambien hay un bus de energia. Algunas arquitecturas pueden tener tambien un bus I/O separado.
CPU (ALU, Registros, y Control) Memoria Entrada y Salida (I/O)
System Bus
Bus de Datos Bus de Direcciones Bus de Control

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Niveles de las Maquinas

Hay un nmero de niveles en una computadora (depende del autor) que va desde el nivel del usuario, hasta el nivel de transistor. Avanzando desde arriba hacia abajo, los niveles se hacen menos abstractos a medida que la estructura interna de la computadora se hace visible.
Alto Nivel Nivel de Usuario: ProgramasAplicaciones Lenguajes de Alto Nivel Lenguaje ensamblador/Codigo maquina Control Microprogramado / Cableado U.Funcionales (Memoria, ALU, etc.) Compuertas Logicas Bajo Nivel Transistores y Cables
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Una Computadora Tpica

Drive de Diskette Drive de CD-ROM Drive de Disco Duro
Monitor
Ranuras para conectar Tarjetas de expansin
Teclado
Ranuras para memorias internas CPU (Microprocesador debajo del disipador de calor
Principios de Arquitectura de Computadoras por M. Murdocca y V. Heuring
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La Placa Madre
Los cinco componentes de von Neumann se ven claramente en esta Placa Madre, en el contexto del modelo de interconexin por bus.
Input / output
(Source: TYAN Computer, http://www.tyan.com)
Plug-in expansion card slots
Pentium II processor slot (ALU/control)
Battery Power supply connector
Memory
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Manchester University Mark I

Las Supercomputadoras, que se fabrican en pequeas cantidades y con un precio elevado, estn siendo reemplazadas por mquinas de produccin masiva, bajo precio y mejor relacin costo/rendimiento.
(Source: http://www.paralogos.com/DeadSuper)
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Ley de Moore
A igual precio las computadoras duplican su potencia cada 18 meses. Esta observacion debe considerarse seriamente : Una innovacion en la arquitectura que se hace para obtener un rendimiento cuadruple en tres aos puede llegar a ser irrelevante: Las arquitecturas que existan para entonces tal vez ya ofrezcan un cuadruple rendimiento y verse totalmente diferentes para cuando la modificacion se esperaba que estuviera disponible
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Chapter 2: Data Representation
Principles of Computer Architecture

Miles Murdocca and Vincent Heuring
Principles of Computer Architecture by M. Murdocca and V. Heuring
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Chapter Contents
2.1 Introduction 2.2 Fixed Point Numbers 2.3 Floating Point Numbers 2.4 Case Study: Patriot Missile Defense Failure Caused by Loss of Precision 2.5 Character Codes
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Fixed Point Numbers

Using only two digits of precision for signed base 10 numbers, the range (interval between lowest and highest numbers) is [-99, +99] and the precision (distance between successive numbers) is 1. The maximum error, which is the difference between the value of a real number and the closest representable number, is 1/2 the precision. For this case, the error is 1/2 1 = 0.5. If we choose a = 70, b = 40, and c = -30, then a + (b + c) = 80 (which is correct) but (a + b) + c = -30 which is incorrect. The problem is that (a + b) is +110 for this example, which exceeds the range of +99, and so only the rightmost two digits (+10) are retained in the intermediate result. This is a problem that we need to keep in mind when representing real numbers in a finite representation.
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Weighted Position Code

The base, or radix of a number system defines the range of possible values that a digit may have: 0 9 for decimal; 0,1 for binary. The general form for determining the decimal value of a number is given by:
Example: 541.2510 = 5 102 + 4 101 + 1 100 + 2 10-1 + 5 10-2 = (500)10 + (40)10 + (1)10 + (2/10)10 + (5/100)10 = (541.25)10
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Base Conversion with the Remainder Method

Example: Convert 23.37510 to base 2. Start by converting the integer portion:
Integer 23/2 = 11/2 = 5/2 2/2 1/2 = = = 11 5 2 1 0 Remainder R1 R1 R1 R0 R1 Most significant bit Least significant bit
(23)10 = (10111)2
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Base Conversion with the Multiplication Method

Now, convert the fraction:
Most significant bit .375 .75 .5 2 2 2 = = = 0.75 1.5 1.0 0 0 Least significant bit
(.375)10 = (.011)2
Putting it all together, 23.37510 = 10111.0112.

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Nonterminating Base 2 Fraction

We cant always convert a terminating base 10 fraction into an equivalent terminating base 2 fraction:
.2 .4 .8 .6 .2 2 2 2 2 2 = = = = = 0.4 0.8 1.6 1.2 0.4
. . .
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Base 2, 8, 10, 16 Number Systems

Binary (base 2) 0 1 10 11 100 101 110 111 1000 1001 1010 1011 1100 1101 1110 1111 Octal (base 8) 0 1 2 3 4 5 6 7 10 11 12 13 14 15 16 17 Decimal (base 10) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Hexadecimal (base 16) 0 1 2 3 4 5 6 7 8 9 A B C D E F
Example: Show a column for ternary (base 3). As an extension of that, convert 1410 to base 3, using 3 as the divisor for the remainder method (instead of 2). Result is 1123
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More on Base Conversions

Converting among power-of-2 bases is particularly simple: 10112 = (102)(112) = 234 234 = (24)(34) = (102)(112) = 10112 1010102 = (1012)(0102) = 528 011011012 = (01102)(11012) = 6D16 How many bits should be used for each base 4, 8, etc., digit? For base 2, in which 2 = 21, the exponent is 1 and so one bit is used for each base 2 digit. For base 4, in which 4 = 22, the exponent is 2, so so two bits are used for each base 4 digit. Likewise, for base 8 and base 16, 8 = 23 and 16 = 24, and so 3 bits and 4 bits are used for base 8 and base 16 digits, respectively.
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Binary Addition
This simple binary addition example provides background for the signed number representations to follow.
Carry in Operands 0 0 + 0 0 0 0 0 + 1 0 1 0 1 + 0 0 1 0 1 + 1 1 0 1 0 + 0 0 1 1 0 + 1 1 0 1 1 + 0 1 0 1 1 + 1 1 1
Carry Sum out
Example: Carry Addend: A Augend: B Sum 1 1 1 1 0 0 0 0 0 1 1 1 1 1 0 0 + 0 1 0 1 1 0 1 0 1 1 0 1 0 1 1 0 (124)10 (90)10 (214)10
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Signed Fixed Point Numbers

For an 8-bit number, there are 28 = 256 possible bit patterns. These bit patterns can represent negative numbers if we choose to assign bit patterns to numbers in this way. We can assign half of the bit patterns to negative numbers and half of the bit patterns to positive numbers. Four signed representations we will cover are: Signed Magnitude Ones Complement Twos Complement Excess (Biased)
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Signed Magnitude
Also know as sign and magnitude, the leftmost bit is the sign (0 = positive, 1 = negative) and the remaining bits are the magnitude. Example: +2510 = 000110012 -2510 = 100110012 Two representations for zero: +0 = 000000002, -0 = 100000002. Largest number is +127, smallest number is -12710, using an 8-bit representation.
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Ones Complement
The leftmost bit is the sign (0 = positive, 1 = negative). Negative of a number is obtained by subtracting each bit from 2 (essentially, complementing each bit from 0 to 1 or from 1 to 0). This goes both ways: converting positive numbers to negative numbers, and converting negative numbers to positive numbers. Example: +2510 = 000110012 -2510 = 111001102 Two representations for zero: +0 = 000000002, -0 = 111111112. Largest number is +12710, smallest number is -12710, using an 8bit representation.
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Twos Complement
The leftmost bit is the sign (0 = positive, 1 = negative). Negative of a number is obtained by adding 1 to the ones complement negative. This goes both ways, converting between positive and negative numbers. Example (recall that -2510 in ones complement is 111001102): +2510 = 000110012 -2510 = 111001112 One representation for zero: +0 = 000000002, -0 = 000000002. Largest number is +12710, smallest number is -12810, using an 8bit representation.
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Excess (Biased)
The leftmost bit is the sign (usually 1 = positive, 0 = negative). Positive and negative representations of a number are obtained by adding a bias to the twos complement representation. This goes both ways, converting between positive and negative numbers. The effect is that numerically smaller numbers have smaller bit patterns, simplifying comparisons for floating point exponents. Example (excess 128 adds 128 to the twos complement version, ignoring any carry out of the most significant bit) : +1210 = 100011002 -1210 = 011101002 One representation for zero: +0 = 100000002, -0 = 100000002. Largest number is +12710, smallest number is -12810, using an 8bit representation.
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BCD Representations in Nines and Tens Complement

Each binary coded decimal digit is composed of 4 bits.
(a) 0 0 0 0 (0)10 (b) 1 0 0 1 (9)10 (c) 1 0 0 1 (9)10 0011 (3)10 0110 (6)10 0110 (6)10 0000 (0)10 1001 (9)10 1001 (9)10 0 0 0 1 (+301)10 Nines and tens complement (1)10 1 0 0 0 (301)10 Nines complement (8)10 1 0 0 1 (301)10 Tens complement (9)10
Example: Represent +07910 in BCD: 0000 0111 1001 Example: Represent -07910 in BCD: 1001 0010 0001. This is obtained by first subtracting each digit of 079 from 9 to obtain the nines complement, so 999 - 079 = 920. Adding 1 produces the tens complement: 920 + 1 = 921. Converting each base 10 digit of 921 to BCD produces 1001 0010 0001.
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3-Bit Signed Integer Representations
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Base 10 Floating Point Numbers

Floating point numbers allow very large and very small numbers to be represented using only a few digits, at the expense of precision. The precision is primarily determined by the number of digits in the fraction (or significand, which has integer and fractional parts), and the range is primarily determined by the number of digits in the exponent. Example (+6.023 1023):
Position of decimal point + Sign 2 3 6
Exponent (two digits)
Significand (four digits)

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Normalization
The base 10 number 254 can be represented in floating point form as 254 100, or equivalently as: 25.4 101, or 2.54 102, or .254 103, or .0254 104, or infinitely many other ways, which creates problems when making comparisons, with so many representations of the same number. Floating point numbers are usually normalized, in which the radix point is located in only one possible position for a given number. Usually, but not always, the normalized representation places the radix point immediately to the left of the leftmost, nonzero digit in the fraction, as in: .254 103.
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Floating Point Example

Represent .254 103 in a normalized base 8 floating point format with a sign bit, followed by a 3-bit excess 4 exponent, followed by four base 8 digits. Step #1: Convert to the target base. .254 103 = 25410. Using the remainder method, we find that 25410 = 376 80: 254/8 = 31 R 6 31/8 = 3 R 7 3/8 = 0 R 3 Step #2: Normalize: 376 80 = .376 83. Step #3: Fill in the bit fields, with a positive sign (sign bit = 0), an exponent of 3 + 4 = 7 (excess 4), and 4-digit fraction = .3760:
0 111 . 011 111 110 000

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Error, Range, and Precision

In the previous example, we have the base b = 8, the number of significant digits (not bits!) in the fraction s = 4, the largest exponent value (not bit pattern) M = 3, and the smallest exponent value m = -4. In the previous example, there is no explicit representation of 0, but there needs to be a special bit pattern reserved for 0 otherwise there would be no way to represent 0 without violating the normalization rule. We will assume a bit pattern of 0 000 000 000 000 000 represents 0. Using b, s, M, and m, we would like to characterize this floating point representation in terms of the largest positive representable number, the smallest (nonzero) positive representable number, the smallest gap between two successive numbers, the largest gap between two successive numbers, and the total number of numbers that can be represented.
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Error, Range, and Precision (cont)

Largest representable number: bM (1 - b-s) = 83 (1 - 8-4) Smallest representable number: bm b-1 = 8-4 - 1 = 8-5 Largest gap: bM b-s = 83 - 4 = 8-1 Smallest gap: bm b-s = 8-4 - 4= 8-8
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Error, Range, and Precision (cont)

A 2 B C D bs-1 + E 1 ((M - m) + 1) (b - 1) First digit of fraction
The number Sign bit of exponents
Remaining digits of Zero fraction
Number of representable numbers: There are 5 components: (A) sign bit; for each number except 0 for this case, there is both a positive and negative version; (B) (M - m) + 1 exponents; (C) b - 1 values for the first digit (0 is disallowed for the first normalized digit); (D) bs-1 values for each of the s-1 remaining digits, plus (E) a special representation for 0. For this example, the 5 components result in: 2 ((3 - 4) + 1) (8 - 1) 84-1 + 1 numbers that can be represented. Notice this number must be no greater than the number of possible bit patterns that can be generated, which is 216.
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Example Floating Point Format
3 2
1 1 2 4 1 8
0 1 8
1 4
1 2
1 b = 2 s = 3
3 2 M = +1 m = 2
Smallest number is 1/8 Largest number is 7/4 Smallest gap is 1/32 Largest gap is 1/4 Number of representable numbers is 33.
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Gap Size Follows Exponent Size

The relative error is approximately the same for all numbers. If we take the ratio of a large gap to a large number, and compare that to the ratio of a small gap to a small number, then the ratios are the same:
A large gap A large number A small gap A small number
bMs bM (1 bs) bms bm (1 bs)
bs 1 bs bs 1 bs
1 bs1 1 bs1
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Conversion Example
Example: Convert (9.375 10-2)10 to base 2 scientific notation Start by converting from base 10 floating point to base 10 fixed point by moving the decimal point two positions to the left, which corresponds to the -2 exponent: .09375. Next, convert from base 10 fixed point to base 2 fixed point: .09375 .1875 .375 .75 .5 2 2 2 2 2 = = = = = 0.1875 0.375 0.75 1.5 1.0
Thus, (.09375)10 = (.00011)2. Finally, convert to normalized base 2 floating point:
.00011 = .00011 20 = 1.1 2-4

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IEEE-754 Floating Point Formats

32 bits Single precision Sign (1 bit) Double precision 11 bits Exponent 8 bits Exponent 23 bits Fraction 64 bits 52 bits Fraction
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IEEE-754 Examples
Value (a) +1.101 25 (b) 1.01011 2126 (c) +1.0 2127 (d) +0 (e) 0 (f) + (g) +2128 (h) +NaN (i) +2128 Bit Pattern Sign Exponent 0 1000 0100 1 0000 0001 0 1111 1110 0 0000 0000 1 0000 0000 0 1111 1111 0 0000 0000 0 1111 1111 0 011 0111 1111 Fraction 101 0000 0000 0000 0000 0000 010 1100 0000 0000 0000 0000 000 0000 0000 0000 0000 0000 000 0000 0000 0000 0000 0000 000 0000 0000 0000 0000 0000 000 0000 0000 0000 0000 0000 010 0000 0000 0000 0000 0000 011 0111 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000
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IEEE-754 Conversion Example

Represent -12.62510 in single precision IEEE-754 format. Step #1: Convert to target base. -12.62510 = -1100.1012 Step #2: Normalize. -1100.1012 = -1.1001012 23 Step #3: Fill in bit fields. Sign is negative, so sign bit is 1. Exponent is in excess 127 (not excess 128!), so exponent is represented as the unsigned integer 3 + 127 = 130. Leading 1 of significand is hidden, so final bit pattern is:
1 1000 0010 . 1001 0100 0000 0000 0000 000
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Effect of Loss of Precision

According to the General Accounting Office of the U.S. Government, a loss of precision in converting 24bit integers into 24-bit floating point numbers was responsible for the failure of a Patriot antimissile battery.
Missile outside of range gate Range Gate Area
Validation action
Search action locates missile somewhere within beam
Missile
Patriot Radar System
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ASCII Character Code

ASCII is a 7-bit code, commonly stored in 8-bit bytes. A is at 4116. To convert upper case letters to lower case letters, add 2016. Thus a is at 4116 + 2016 = 6116. The character 5 at position 3516 is different than the number 5. To convert character-numbers into number-numbers, subtract 3016: 3516 - 3016 = 5.
00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F NUL SOH STX ETX EOT ENQ ACK BEL BS HT LF VT FF CR SO SI 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F DLE DC1 DC2 DC3 DC4 NAK SYN ETB CAN EM SUB ESC FS GS RS US 20 SP 21 ! 22 " 23 # 24 $ 25 % 26 & 27 ' 28 ( 29 ) 2A * 2B + 2C 2D 2E . 2F / 30 31 32 33 34 35 36 37 38 39 3A 3B 3C 3D 3E 3F 0 1 2 3 4 5 6 7 8 9 : ; < = > ? 40 @ 41 A 42 B 43 C 44 D 45 E 46 F 47 G 48 H 49 I 4A J 4B K 4C L 4D M 4E N 4F O 50 P 51 Q 52 R 53 S 54 T 55 U 56 V 57 W 58 X 59 Y 5A Z 5B [ 5C \ 5D ] 5E ^ 5F _ 60 ` 61 a 62 b 63 c 64 d 65 e 66 f 67 g 68 h 69 i 6A j 6B k 6C l 6D m 6E n 6F o CAN EM SUB ESC FS GS RS US SP DEL 70 p 71 q 72 r 73 s 74 t 75 u 76 v 77 w 78 x 79 y 7A z 7B { 7C | 7D } 7E ~ 7F DEL
NUL SOH STX ETX EOT ENQ ACK BEL BS HT LF VT
Null Start of heading Start of text End of text End of transmission Enquiry Acknowledge Bell Backspace Horizontal tab Line feed Vertical tab
FF CR SO SI DLE DC1 DC2 DC3 DC4 NAK SYN ETB
Form feed Carriage return Shift out Shift in Data link escape Device control 1 Device control 2 Device control 3 Device control 4 Negative acknowledge Synchronous idle End of transmission block
Cancel End of medium Substitute Escape File separator Group separator Record separator Unit separator Space Delete
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EBCDIC Character Code

EBCDIC is an 8-bit code.
STX DLE BS ACK SOH ENQ ESC BYP CAN RES SI SO DEL SUB NL LF
Start of text Data Link Escape Backspace Acknowledge Start of Heading Enquiry Escape Bypass Cancel Restore Shift In Shift Out Delete Substitute New Line Line Feed
RS PF DS PN SM LC CC CR EM FF TM UC FS HT VT UC
Reader Stop Punch Off Digit Select Punch On Set Mode Lower Case Cursor Control Carriage Return End of Medium Form Feed Tape Mark Upper Case Field Separator Horizontal Tab Vertical Tab Upper Case
00 NUL 20 DS 40 SP 01 SOH 21 SOS 41 02 STX 22 FS 42 03 ETX 23 43 04 PF 24 BYP 44 05 HT 25 LF 45 06 LC 26 ETB 46 07 DEL 27 ESC 47 08 28 48 09 29 49 0A SMM 2A SM 4A 0B VT 2B CU2 4B 0C FF 2C 4C < 0D CR 2D ENQ 4D ( 0E SO 2E ACK 4E + 0F SI 2F BEL 4F | 10 DLE 30 50 & 11 DC1 31 51 12 DC2 32 SYN 52 13 TM 33 53 14 RES 34 PN 54 DC1 Device Control 1 BEL Bell 15 NL 35 RS DC2 Device Control 2 SP 55 Space DC416 Device Idle BS Control 36 4 UCIL 56 CU1 Customer Use 1 NUL Null IL 37 2 EOT 57 CU217Customer Use CU318Customer CAN Use 38 3 58 SYN Synchronous Idle EM 39 59 IFS 19Interchange File Separator EOT End of Transmission CC 3A 5A ! ETB1A End of Transmission Block NAK Negative 1B CU1 Acknowledge 3B CU3 5B $ SMM Start of Manual Message 1C IFS 3C DC4 5C . SOS Start of Significance IGS 1D Interchange Group Separator IGS 3D NAK 5D ) IRS Interchange Record Separator IRS 3E 5E ; IUS1E Interchange Unit Separator 1F IUS 3F SUB 5F
60 61 62 63 64 65 66 67 68 69 6A 6B 6C 6D 6E 6F 70 71 72 73 74 75 76 77 78 79 7A 7B 7C 7D 7E 7F
80 81 a 82 b 83 c 84 d 85 e 86 f 87 g 88 h 89 i 8A , 8B % 8C _ 8D > 8E ? 8F 90 91 j 92 k 93 l 94 m 95 n 96 o 97 p 98 q 99 r : 9A # 9B @ 9C ' 9D = 9E " 9F
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 AA AB AC AD AE AF B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 BA BB BC BD BE BF
~ s t u v w x y z
C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 CA CB CC CD CE CF D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 DA DB DC DD DE DF
{ A B C D E F G H I
} J K L M N O P Q R
E0 E1 E2 E3 E4 E5 E6 E7 E8 E9 EA EB EC ED EE EF F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 FA FB FC FD FE FF
\ S T U V W X Y Z
0 1 2 3 4 5 6 7 8 9 |
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0000 NUL 0001 SOH 0002 STX 0003 ETX 0004 EOT 0005 ENQ 0006 ACK 0007 BEL 0008 BS 0009 HT 000A LF 000B VT 000C FF 000D CR 000E SO 000F SI 0010 DLE 0011 DC1 0012 DC2 0013 DC3 0014 DC4 0015 NAK 0016 SYN 0017 ETB 0018 CAN 0019 EM 001A SUB 001B ESC 001C FS 001D GS 001E RS 001F US 0020 SP 0021 ! 0022 " 0023 # 0024 $ 0025 % 0026 & ' 0027 0028 ( 0029 ) 002A * 002B + 002C 002D 002E . 002F / 0030 0 0031 1 0032 2 0033 3 0034 4 0035 5 0036 6 0037 7 0038 8 0039 9 003A : 003B ; 003C < 003D = 003E > 003F ? 0040 0041 0042 0043 0044 0045 0046 0047 0048 0049 004A 004B 004C 004D 004E 004F 0050 0051 0052 0053 0054 0055 0056 0057 0058 0059 005A 005B 005C 005D 005E 005F @ A B C D E F G H I J K L M N O P Q R S T U V W X Y Z [ \ ] ^ _ 0060 ` 0080 Ctrl 0061 a 0081 Ctrl 0062 b 0082 Ctrl 0063 c 0083 Ctrl 0064 d 0084 Ctrl 0065 e 0085 Ctrl 0066 f 0086 Ctrl 0067 g 0087 Ctrl 0068 h 0088 Ctrl 0069 i 0089 Ctrl 006A j 008A Ctrl 006B k 008B Ctrl 006C l 008C Ctrl 006D m 008D Ctrl 006E n 008E Ctrl 006F o 008F Ctrl 0070 p 0090 Ctrl 0071 q 0091 Ctrl 0072 r 0092 Ctrl 0073 s 0093 Ctrl 0074 t 0094 Ctrl 0075 u 0095 Ctrl 0076 v 0096 Ctrl 0077 w 0097 Ctrl 0078 x 0098 Ctrl 0079 y 0099 Ctrl 007A z 009A Ctrl 007B { 009B Ctrl 007C | 009C Ctrl 007D } 009D Ctrl 007E ~ 009E Ctrl 007F DEL 009F Ctrl CAN EM SUB ESC FS GS RS US SYN

00A0 NBS 00A1 00A2 00A3 00A4 00A5 00A6 00A7 00A8 00A9 00AA a 00AB 00AC 00AD 00AE 00AF 00B0 00B1 00B2 2 00B3 3 00B4 00B5 00B6 00B7 00B8 00B9 1 00BA o 00BB 00BC 1/4 00BD 1/2 00BE 3/4 00BF 00C0 00C1 00C2 00C3 00C4 00C5 00C6 00C7 00C8 00C9 00CA 00CB 00CC 00CD 00CE 00CF 00D0 00D1 00D2 00D3 00D4 00D5 00D6 00D7 00D8 00D9 00DA 00DB 00DC 00DD 00DE 00DF D Y y 00E0 00E1 00E2 00E3 00E4 00E5 00E6 00E7 00E8 00E9 00EA 00EB 00EC 00ED 00EE 00EF 00F0 00F1 00F2 00F3 00F4 00F5 00F6 00F7 00F8 00F9 00FA 00FB 00FC 00FD 00FE 00FF P P p p
Unicode Character Code
Unicode is a 16bit code.
NUL Null STX Start of text ETX End of text ENQ Enquiry ACK Acknowledge BEL Bell BS Backspace HT Horizontal tab LF Line feed Principles of Computer Architecture by M. Murdocca and V. Heuring
SOH EOT DC1 DC2 DC3 DC4 NAK NBS ETB
Start of heading End of transmission Device control 1 Device control 2 Device control 3 Device control 4 Negative acknowledge Non-breaking space End of transmission block
Cancel SP Space End of medium DEL Delete Substitute Ctrl Control Escape FF Form feed File separator CR Carriage return Group separator SO Shift out Record separator SI Shift in Unit separator DLE Data link escape Synchronous idle VT Vertical tab 1999 M. Murdocca and V. Heuring
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Chapter 3: Arithmetic
Principles of Computer Architecture

3-2
Chapter Contents
3.1 Overview 3.2 Fixed Point Addition and Subtraction 3.3 Fixed Point Multiplication and Division 3.4 Floating Point Arithmetic 3.5 High Performance Arithmetic 3.6 Case Study: Calculator Arithmetic Using Binary Coded Decimal
3-3
Computer Arithmetic
Using number representations from Chapter 2, we will explore four basic arithmetic operations: addition, subtraction, multiplication, division. Significant issues include: fixed point vs. floating point arithmetic, overflow and underflow, handling of signed numbers, and performance. We look first at fixed point arithmetic, and then at floating point arithmetic.
3-4
Number Circle for 3-Bit Twos Complement Numbers

Numbers can be added or subtracted by traversing the number circle clockwise for addition and counterclockwise for subtraction. Overflow occurs when a transition is made from +3 to -4 while proceeding around the number circle when adding, or from -4 to +3 while subtracting. Subtracting
-1 111 0 000 1 001
numbers
-2 110
010 2
101 -3 100 -4
011
Adding numbers
3-5
Overflow
Overflow occurs when adding two positive numbers produces a negative result, or when adding two negative numbers produces a positive result. Adding operands of unlike signs never produces an overflow. Notice that discarding the carry out of the most significant bit during twos complement addition is a normal occurrence, and does not by itself indicate overflow. As an example of overflow, consider adding (80 + 80 = 160)10, which produces a result of -9610 in an 8-bit twos complement format: 01010000 = + 01010000 = ---------10100000 = -96 (not 160 because the sign bit is 1.)
80 80
3-6
Ripple Carry Adder

Two binary numbers A and B are added from right to left, creating a sum and a carry at the outputs of each full adder for each bit position.
b3 a3
c3
b2 a2
c2
b1 a1
c1
b0 a0
c0
Full adder c4 s3
Full adder
Full adder
Full adder
s2
s1
s0
3-7
Constructing Larger Adders

A 16-bit adder can be made up of a cascade of four 4-bit ripplecarry adders.
a15 a14 a13 a12 b15 b14 b13 b12 c12 c16 4-Bit Adder #3 c4
a3 b3 b2
a2 b1
a1 b0
a0
. . .
c0 4-Bit Adder #0 0
s15
s14
s13
s12
s3
s2
s1
s0
3-8
Full Subtractor
Truth table and schematic symbol for a ripple-borrow subtractor:
ai bi bori 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1
diffi bori+1 0 1 1 0 1 0 0 1 0 1 1 1 0 0 0 1
bi ai bori Full subtractor bori+1 diffi (ai bi)
3-9
Ripple-Borrow Subtractor
A ripple-borrow subtractor can be composed of a cascade of full subtractors. Two binary numbers A and B are subtracted from right to left, creating a difference and a borrow at the outputs of each full subtractor for each bit position.
b3 a3
b2 a2
b1 a1
b0 a0
bor0 0
Full subtractor bor4 diff3
Full subtractor
Full subtractor
Full subtractor
diff2
diff1
diff0
3-10
Combined Adder/Subtractor
A single ripple-carry adder can perform both addition and subtraction, by forming the twos complement negative for B when subtracting. (Note that +1 is added at c0 for twos complement.) b3 b2 b1 b0 ADD / SUBTRACT
a3
a2
a1
a0 c0
Full adder
Full adder
Full adder
Full adder
c4 s3 s2 s1 s0
3-11
Ones Complement Addition

An example of ones complement integer addition with an endaround carry:
1 0 0 1 1 (12)10 + 0 1 1 0 1 (+13)10 100000 End-around carry + 1 0 0 0 0 1 (+1)10

The end-around carry is needed because there are two representations for 0 in ones complement. Both representations for 0 are visited when one or both operands are negative.
3-12
Number Circle (Revisited)

Number circle for a three-bit signed ones complement representation. Notice the two representations for 0.
+0 000 001
-0 111
Subtracting numbers
-1 110
010 2
101 -2 100 -3
011
Adding numbers
3-13
End-Around Carry for Fractions

The end-around carry complicates ones complement addition for non-integers, and is generally not used for this situation. The issue is that the distance between the two representations of 0 is 1.0, whereas the rightmost fraction position is less than 1.
0101 . 1 + 1110 . 0 10011 . 1 + 1.0 0100 . 1

(+5.5)10 (1.0)10
(+4.5)10
3-14
Multiplication Example
Multiplication of two 4-bit unsigned binary integers produces an 8-bit result.
1 1 0 1 1 1 1 1 0 0 0 1 1 0 1 0 1 1 1 0 1 0 1 0
(13)10 (11)10
Multiplicand M Multiplier Q
Partial products (143)10 Product P
1 0 0 0 1 1 1 1
Multiplication of two 4-bit signed binary integers produces only a 7-bit result (each operand reduces to a sign bit and a 3-bit magnitude for each operand, producing a sign-bit and a 6-bit result).
3-15
A Serial Multiplier
Multiplicand (M) m3 m2 m1 m0 4 4Bit Adder 4 Add Shift and Add Control Logic q0
Shift Right
a3 a2 a1 a0 A Register 4
q3 q2 q1 q0 Multiplier (Q)
3-16
Example of Multiplication Using Serial Multiplier

Multiplicand (M): 1 1 0 1 Initial values C 0 0 0 1 0 0 1 0 A 0 0 0 0 1 1 0 1 0 1 1 0 0 0 1 1 1 0 0 1 0 1 0 0 0 0 0 1 1 0 0 0 Q 1 0 1 1 1 0 1 1 1 1 0 1 1 1 0 1 1 1 1 0 1 1 1 1 1 1 1 1 1 1 1 1 Add M to A Shift Add M to A Shift Shift (no add) Add M to A Shift
Product
3-17
Example of Base 2 Division

(7 / 3 = 2)10 with a remainder R of 1. Equivalently, (0111/ 11 = 10)2 with a remainder R of 1.
11
0 0 1 0 R1 0111 11 01
3-18
Serial Divider
Divisor (M) 0 m3 m2 m1 m0 5 5Bit Adder 5 Shift and Add / Add / Sub Sub Control Logic Shift Left q0
a4 a3 a2 a1 a0 a4 5 A Register
q3 q2 q1 q0 Dividend (Q)
3-19
Division Example Using Serial Divider

Divisor (M): 0 0 0 1 1 Initial values A 0 0 0 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 1 0 0 1 0 1 1 Q 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 Shift left Subtract M from A Restore A (Add M to A) Clear q0 Shift left Subtract M from A Restore A Clear q0 Shift left Subtract M from A Set q0 Shift left Subtract M from A Restore A Clear q0 Quotient
0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 1 0 1 1
1 0 0 0 1 0 0 0 1 0 0 1 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0
Remainder
3-20
Multiplication of Signed Integers

Sign extension to the target word size is needed for the negative operand(s). A target word size of 8 bits is used here for two 4-bit signed operands, but only a 7-bit target word size is needed for the result.
1 1 1 1 (1)10 0 0 0 1 (+1)10 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 (+15)10 0 0 0 0 1 1 1 1 (Incorrect; result should be 1)
1 1 1 1 1 1 1 1 0 0 0 1 1 0 0 0 1 1 0 0 0 1 1 0 0 0 1 1 0 0 0 1 1 0 0 0 1 1 1 1 0 0 0 1 1 1
(1)10 (+1)10
(1)10
3-21
Carry-Lookahead Addition
Carries are represented in terms of Gi (generate) and Pi (propagate) expressions.
Gi = aibi and Pi = ai + bi c0 = 0 c1 = G0 c2 = G1 + P1G0 c3 = G2 + P2G1 + P2P1G0 c4 = G3 + P3G2 + P3P2G1 + P3P2P1G0

3-22
Carry Lookahead Adder

b3 a3 b2 a2 b1 a1 b0 a0
G3
P3 G2
P2 G1
P1 G0
Maximum gate delay for the carry generation is only 3. The full adders introduce two more gate delays. Worst case path is 5 gate delays.
c0 0
c4 Full adder
c3
c2
c1
Full adder
Full adder
Full adder
s3
s2
s1
s0
3-23
Floating Point Arithmetic

Floating point arithmetic differs from integer arithmetic in that exponents must be handled as well as the magnitudes of the operands. The exponents of the operands must be made equal for addition and subtraction. The fractions are then added or subtracted as appropriate, and the result is normalized. Ex: Perform the floating point operation: (.101 23 + .111 24)2 Start by adjusting the smaller exponent to be equal to the larger exponent, and adjust the fraction accordingly. Thus we have .101 23 = .010 24, losing .001 23 of precision in the process. The resulting sum is (.010 + .111) 24 = 1.001 24 = .1001 25, and rounding to three significant digits, .100 25, and we have lost another 0.001 24 in the rounding process.
3-24
Floating Point Multiplication/Division

Floating point multiplication/division are performed in a manner similar to floating point addition/subtraction, except that the sign, exponent, and fraction of the result can be computed separately. Like/unlike signs produce positive/negative results, respectively. Exponent of result is obtained by adding exponents for multiplication, or by subtracting exponents for division. Fractions are multiplied or divided according to the operation, and then normalized. Ex: Perform the floating point operation: (+.110 25) / (+.100 24)2 The source operand signs are the same, which means that the result will have a positive sign. We subtract exponents for division, and so the exponent of the result is 5 4 = 1. We divide fractions, producing the result: 110/100 = 1.10. Putting it all together, the result of dividing (+.110 25) by (+.100 24) produces (+1.10 21). After normalization, the final result is (+.110 22).
3-25
The Booth Algorithm

Booth multiplication reduces the number of additions for intermediate results, but can sometimes make it worse as we will see. Positive and negative numbers treated alike.
0 1 0 1 0 1 0 0 1 1 1 0 0 +1 0 0 1 0
(21)10 (14)10
Multiplicand Multiplier Booth recoded multiplier
Shift Shift Shift Add Subtract 1 1 1 1 1 1 0 1 0 1 1 0 (21 2)10 0 0 0 1 0 1 0 1 0 0 0 0 (21 16)10 0 0 0 1 0 0 1 0 0 1 1 0

(294)10 Product
3-26
A Worst Case Booth Example

A worst case situation in which the simple Booth algorithm requires twice as many additions as serial multiplication.
0 1 1 1 0 1 0 1 0 1 +1 1 +1 1 +1 1 0 0 (14)10 (21)10 Subtract 1 0 1 0 1 0 0 1 0 1 0 1 0 0 1 0 1 0 1 0 0 1 0 1 0 1 1 1 1 0 1 0 0 1 0 1 0 1 1 0 1 0 1 0 0 1 1 0 1 1 1 0 1 0 0 0 0 1 1 0 0 0 0 0 1 0 0 0 0 1 Multiplicand Multiplier Booth recoded multiplier
Add (14 1)10 1 0 0 0 (14 2)10 0 0 (14 4)10 0 0 (14 8)10 0 0 (14 16)10 0 0 (14 32)10 1 0 (294)10 Product
3-27
Bit-Pair Recoding (Modified Booth Algorithm)

0 0 1 1 1 0 0 1 0 1 0 1 +1 1 +1 1 +1 1 +1 +1 +1 0 0 0 0 0 0 0 0 1 1 1 0 0 0 0 0 0 0 1 1 1 0 0 0 0 0 0 0 1 1 1 0 0 0 0 0 0 0 0 1 0 0 1 0 0 1 1 0 (21)10 Multiplicand (14)10 Multiplier Booth recoded multiplier Bit pair recoded multiplier (14 1)10 (14 4)10 (14 16)10 (294)10 Product
3-28
Coding of Bit Pairs

Booth pair (i + 1, i) 0 0 0 +1 +1 +1 1 1 1 0 +1 1 0 +1 1 0 +1 1 Recoded bit pair (i) = = = = = = = = = 0 +1 1 +2 +1 2 1 Corresponding multiplier bits (i + 1, i, i 1) 000 or 111 001 110 011 010 100 101
3-29
0 0 mw ... PP 0,w q0 PP 0,2 0 0 m2
Multiplicand 0 0
m1 0 0 m0
Parallel Pipelined Array Multiplier
q0
PP 0,1
q0
PP 0,0 p0
q0
... q1 PP 1,2 q1 PP 1,1 q1 PP 1,0 p1 q1

Multiplier
PP 1,w
. . . qw PPw,2
. . . qw PPw,1
. . . qw PPw,0 pw qw
PPw,w
0 ... PP w+1,w FA p 2w-1 aj bj PP w+1,2 FA pw+3 Carry-in Full adder Carry-out m out
PP w+1,1 FA mi pw+2
PP w+1,0 FA pw+1
qj mi
Product
sum
3-30
Newtons Iteration for Zero Finding

The goal is to find where the function f(x) crosses the x axis by starting with a guess xi and then using the error between f(xi ) and zero to refine the guess. A three-bit lookup table for computing x0:
xi
B = First three bits of b .100 .101 .110 .111 Actual base 10 value of 1/B 2 1 3/5 1 1/3 1 1/7 Corresponding lookup table entry 10 01 01 01
f(x)
x x i+1
The division operation a/b is computed as a 1/b. Newtons iteration provides a fast method of computing 1/b.
3-31
Residue Arithmetic
Implements carryless arithmetic (thus fast!), but comparisons are difficult without converting to a weighted position code. Representation of the first twenty decimal integers in the residue number system for the given moduli:
Decimal 0 1 2 3 4 5 6 7 8 9 Residue 5794 0000 1111 2222 3333 4440 0551 1662 2073 3180 4201 Decimal 10 11 12 13 14 15 16 17 18 19 Residue 5794 0312 1423 2530 3641 4052 0163 1270 2381 3402 4513
3-32
Examples of Addition and Multiplication in the Residue Number System

29 + 27 = 56 Decimal 29 27 56 Residue 5794 4121 2603 1020 10 17 = 170 Decimal 10 17 170 Residue 5794 0312 2381 0282
3-33
16-bit Group Carry Lookahead Adder

A16-bit GCLA is composed of four 4-bit CLAs, with additional logic that generates the carries between the four-bit groups. GG0 = G3 + P3G2 + P3P2G1 + P3P2P1G0 GP0 = P3P2P1P0 c4 = GG0 + GP0c0 c8 = GG1 + GP1c4 = GG1 + GP1GG0 + GP1GP0c0 c12 = GG2 + GP2c8 = GG2 + GP2GG1 + GP2GP1GG0 + GP2GP1GP0c0 c16 = GG3 + GP3c12 = GG3 + GP3GG2 + GP3GP2GG1 + GP3GP2GP1GG0 + GP3GP2GP1GP0c0
3-34
16-Bit Group Carry Lookahead Adder

a12 a15 b12 b15 4 4 c12 a8 a11 b8 b11 4 4 c8 a4 a7 b4 b7 4 4 c4 a0 a3 b0 b3 4 4 c0
Each CLA has a longest path of 5 gate delays.

GP3
CLA3 4
CLA2 4 s8 s11
CLA1 4 s 4 s7 GP1 GG1
CLA0 4 s 0 s3 GP0 GG0
s12 s15 GG3 GP2
GG2
c16
Group Carry Lookahead Logic
In the GCLL section, GG and GP signals are generated in 3 gate delays; carry signals are generated in 2 more gate delays, resulting in 5 gate delays to generate the carry out of each GCLA group and 10 gates delays on the worst case path (which is s15 not c16).
3-35
HP 9100 Series Desktop Calculator

Source: http://www.teleport.com/ ~dgh/91003q.jpg. Uses binary coded decimal (BCD) arithmetic.
3-36
Addition Example Using BCD

Addition is performed digit by digit (not bit by bit), in 4-bit groups, from right to left. Example (255 + 63 = 318)10:
0 0000 (0)10 + 0000 (0)10 0000 (0)10
1 0010 (2)10 0000 (0)10 0011 (3)10
0 0101 (5)10 0110 (6)10 0001 (1)10
0 0101 (5)10 0011 (3)10 1000 (8)10
Carries (+255)10
(+63)10
(+318)10
3-37
Subtraction Example Using BCD

Subtraction is carried out by adding the tens complement negative of the subtrahend to the minuend. Tens complement negative of subtrahend is obtained by adding 1 to the nines complement negative of the subtrahend. Consider performing the subtraction operation (255 - 63 = 192)10:
9999 0063 9936

+
1 0000 1001
0 0010 1001 0001
1 0101 0011 1001
0 0101 0111 0010
Carries (+255)10 (63)10 (+192)10
9936 +0001 9937
0000
Discard carry
3-38
Excess 3 Encoding of BCD Digits

Using an excess 3 encoding for each BCD digit, the leftmost bit indicates the sign.
BCD Bit Pattern 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Normal BCD value 0 1 2 3 4 5 6 7 8 9 d d d d d d Excess 3 value d d d 0 1 2 3 4 5 6 7 8 9 d d d
Positive numbers
Negative numbers
3-39
A BCD Full Adder

Circuit adds two base 10 digits represented in BCD. Adding 5 and 7 (0101 and 0111) results in 12 (0010 with a carry of 1, and not 1100, which is the binary representation of 1210).
b3 a3 b2 a2 b1 a1 b0 a0 c0 0
Full adder c4
Full adder
Full adder
Full adder
Full adder
Full adder
Full adder
Full adder
s3
s2
s1
s0
3-40
Tens Complement Subtraction

Compare: the traditional signed magnitude approach for adding decimal numbers vs. the tens complement approach, for (21 - 34 = -13)10:
0021 + 9966 9987 Tens Complement
0021 0034 0013 Signed Magnitude
3-41
BCD Floating Point Representation

Consider a base 10 floating point representation with a two digit signed magnitude exponent and an eight digit signed magnitude fraction. On a calculator, a sample entry might look like: -.37100000 10-12 We use a tens complement representation for the exponent, and a base 10 signed magnitude representation for the fraction. A separate sign bit is maintained for the fraction, so that each digit can take on any of the 10 values 09 (except for the first digit, which cannot be zero). We should also represent the exponent in excess 50 (placing the representation for 0 in the middle of the exponents, which range from -50 to +49) to make comparisons easier. The example above now looks like this (see next slide):
3-42
BCD Floating Point Arithmetic

The example in the previous slide looks like this: Sign bit: Exponent: Fraction: 1 0110 1011 0110 1010 0100 0011 0011 0011 0011 0011 0011
Note that the representation is still in excess 3 binary form, with a two digit excess 50 exponent. To add two numbers in this representation, as for a base 2 floating point representation, we start by adjusting the exponent and fraction of the smaller operand until the exponents of both operands are the same. After adjusting the smaller fraction, we convert either or both operands from signed magnitude to tens complement according to whether we are adding or subtracting, and whether the operands are positive or negative, and then perform the addition or subtraction operation.
4-1
Chapter 4: The Instruction Set Architecture
Captulo 4: La Arquitectura del Conjunto de Instrucciones
4-2
Contenidos de Captulo
4.1Componentes de Hardware de la Arquitectura del Set de Instrucciones 4.2 ARC, Una Computadora RISC 4.3 Pseudo Operaciones 4.4 Ejemplos de Programas en Languaje Ensamblador 4.5 Accediendo a Datos en MemoriaModos de Direccionamiento 4.6 Enlaces a Subrutinas y Punteros 4.7 Entreada y Salida en Lenguaje Ensamblador
4-3
La Arquitectura del Set de Instrucciones

La Vista de la Arquitectura del Set Instrucciones (ISA) de una mquina corresponde al nivel de : lenguaje ensamblador / lenguaje de mquina Un compilador traduce un lenguaje de alto nivel, que es independiente de la arquitectura, a lenguaje ensamblador, el cual es dependiente de la arquitectura. Un ensamblador traduce programas en lenguaje assembler a cdigos binarios ejecutables. Para lenguajes compilados como C y Fortran, los cdigos binarios son ejecutados directamente por la mquina. Java para la traducin a nivel de byte. La mquina virtual Java, que est a nivel de lenguaje ensamblador, interpreta directamente los bytes (hay implementaciones de hardware de la JVM, en las que el cdigo de byte Java es ejecutado directamente.)
4-4
Revisin del Modelo de Bus de Sistema

Un programa compilado es copiado desde el disco duro en la memoria. La CPU lee las instrucciones y los datos desde la memoria, ejecuta las instrucciones y almacena los resultados nuevamente en la memoria.
CPU (ALU, Registros, y Control)
Memoria
Entrada y Salida (I/O)
System Bus
Bus de Datos Bus de Direcciones Bus de Control

4-5
Tamaos ms comunes de los datos

Un byte est compuesto de 8 bits. Dos nibbles forman un byte. Los datos de media palabra, palabra, palabra doble y cudruple estn compuestos por bytes como se ve a continuacin:
Bit Nibble Byte 16-bit word (halfword) 32-bit word 64-bit word (double) 128-bit word (quad) 0 0110 10110000 11001001 10110100 01011000 11001110 01011000 11001110 00001011 10100100
01000110 00110101 01010101 11101110 01010101 11101110 10100110 01000100
10011001 10110000 01111000 10110000 01111000 11110010 10100101
01011000 11110011 00110101 11110011 00110101 11100110 01010001
4-6
Formatos Big-Endian y Little-Endian

En una mquina direccionable por byte el dato ms pequeo que se puede buscar en memoria es el byte. Las palabras multi bytes se almacenan como secuencias de bytes, y se direccionan a partir del byte menos significativo de la palabra almacenada. Cuando se utilizan palabras de mas de un byte, hay dos alternativas en la forma de almacenar sus bytes en memoria: el byte mas significativo se almacena en la direccin mas baja de memoria (big-endian). El byte menos significativo se almacena en la direccin mas baja (little-endian). Byte
31 MSB
Big-Endian
LSB 0
31 MSB
Little-Endian
LSB 0
x+1
x+2
x+3
x+3
x+2
x+1
La direccin de la palabra es x para ambos formatos.

4-7
Mapa de Memoria para ARC

Datos Las direcciones Direcciones 32 bits de memoria estan 0 Reservado para ordenadas en forma sistema operativo consecutiva. 2048 Espacio del Usuario Cada locacin numerada corresponde a una palabra en ARC. Tope de la pila El nico nmero Pila del Sistema que identifica a Final de la pila cada palabra 231 4 se conoce como Disco su direccin. Terminal Impresora 232 4 byte 232 1
Entrada Direccin Control de datos
MEMORIA Puntero de pila
Espacio I/O Salida de Datos
4-8
Vista Abstracta de una CPU

La CPU consiste de una seccin de datos que contiene registros y una ALU, y una seccin de control, que interpreta las instructiones y realiza las transferencias entre registros. La seccin de datos se conoce como "camino de datos" o "datapath".
Registros
Unidad Control
ALU
Datapath (Seccin deDatos)

Sistema
Seccin de Control
4-9
El Ciclo Fetch-Ejecucin
Los pasos que sigue una unidad de control para ejecutar un programa son: (1) Buscar de la memoria la siguiente instruccin a ejecutar. (2) Decodificar el opcode (cdigo de operacin). (3) Leer operando(s) desde la memoria principal, si hubiera alguno. (4) Ejecutar la instruccin y almacenar resultados. (5) Ir al paso 1. Esto se conoce como el ciclo fetch-ejecucin.
4-10
Trayectoria de Datos "Datapath"

Registro Fuente 1 (rs1) Desde el Bus de Datos
Registro Fuente 2 (rs2)
Conjunto de Registros
La Unidad de Control selecciona funciones en Registros y ALU
Al Bus de Direcciones
ALU
Al Bus de Datos Estado a la Unidad de Control
Al Registro de Destino (rd)
El datapath de ARC est formado por una coleccin de registros conocidos el archivo de registros y la unidad aritmetico lgica (ALU).
4-11
Arquitectura de las Instrucciones ARC

La ISA de ARC es un subconjunto de la ISA de SPARC.
Nemonico Significado Cargar registro desde la memoria Almacenar un registro en la memoria Cargar los 22 bits mas significativos de un registro Operacin lgica AND bit a Bit Operacin lgica OR bit a bit Operacin lgica NOR bit a bit Desplazar a derecha (lgico)agrega ceros a la izq. Sumar Salto Llamado a subrutina Salto y Enlace (retorno de subrutina) Bifurcacin o Salto por igual Bifurcacin o Salto por negativo Bifurcacin o Salto por acarreo Bifurcacin o Salto por desborde u "overflow" Bifurcacin o Salto incondicional
Memoria
ld st sethi andcc
Lgicas
orcc orncc srl
Aritmeticas
addcc call jmpl be
Control
bneg bcs bvs ba
4-12
Formato de lenguaje ensamblador ARC

El formato de lenguaje ensamblador ARC es el mismo del lenguaje ensamblador SPARC.
Operandos Operandos Etiqueta Nemnico fuentes Destino
Comentario
lab_1:
addcc
%r1, %r2, %r3
!Ejemplo cdigo assembler
4-13
Registros ARC visibles por el usuario

Registro 00 Registro 01 Registro 02 Registro 03 Registro 04 Registro 05 Registro 06 Registro 07 Registro 08 Registro 09 Registro 10 PSR 32 bits
%r0 [= 0] %r1 %r2 %r3 %r4 %r5 %r6 %r7 %r8 %r9 %r10 %psr
Registro 11 Registro 12 Registro 13 Registro14 Registro 15 Registro 16 Registro 17 Registro 18 Registro 19 Registro 20 Registro 21
%r11 %r12 %r13 %r14 [%sp] %r15 [link] %r16 %r17 %r18 %r19 %r20 %r21
Registro 22 Registro 23 Registro 24 Registro 25 Registro 26 Registro 27 Registro 28 Registro 29 Registro 30 Registro 31
%r22 %r23 %r24 %r25 %r26 %r27 %r28 %r29 %r30 %r31
PC 32 bits
%pc
4-14
Instrucciones ARC y Formatos PSR

op
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
Formato SETHI Formato de salto
0 0 0 0 0
rd cond
op2 op2
imm22 disp22
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
Formato de llamada a subrutina
0 1
disp30 i
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
Formatos Aritmticos
1 0 1 0
rd rd
op3 op3
rs1 rs1
0 0 0 0 0 0 0 0 0 1 simm13
rs2
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
1 1 Formatos de Memoria 1 1
rd rd
op3 op3
rs1 rs1
0 0 0 0 0 0 0 0 0 1 simm13
rs2
op 00 01 10 11
Format SETHI/Branch CALL Aritmticas Memoria
op2
Inst.
op3 (op=10) 010000 010001 010010 010110 100110 111000 addcc andcc orcc orncc srl jmpl
op3 (op=11) 000000 ld 000100 st
cond salto 0001 0101 0110 0111 1000 be bcs bneg bvs ba
010 branch 100 sethi
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
PSR
n z v c
4-15
Signed Integer Byte Signed Integer Halfword Signed Integer Word Signed Integer Double s
7 6
Signed Formats
s
15 14 0
s
31 30 0
s
63 62 32
31
Unsigned Formats Unsigned Integer Byte

7 0
Formatos de Datos ARC
Unsigned Integer Halfword

15 0
Unsigned Integer Word

31 0 Tag 31 2 1 0
Tagged Word Unsigned Integer Double

63
32
31
Floating Point Formats Floating Point Single Floating Point Double s

31 30
exponent
23 22
fraction
0
s
63 62
exponent
52 51
fraction
32
fraction
31 0
Floating Point Quad
s
127 126
exponent
112 113
fraction
96
fraction
95 64
fraction
63 32
fraction
31 0
4-16
Pseudo-Operaciones ARC
Pseudo-Op
.equ .begin .end .org .dwb .global .extern .macro
Uso
X .equ #10
Significado
Asignar a X el valor (10) 16 .begin Comienzo de traduccin .end Fin de traducccin .org 2048 Cambiar contador de posicion a 2048 .dwb 25 Reservar un bloque de 25 palabras .global Y Y se usa en otro modulo .extern Z Z est definido en otro modulo .macro M a, b, ... Definir macro M con parametros
.endmacro .if <cond> .endif
.endmacro .if .endif
formales: a, b, ... Fin de definicin de Macro Ensamblar si <cond> es cierta Fin estructura condicional
Las pseudo-ops son instrucciones del assembler. No son parte de la ISA (Instruction Set Architecture).
4-17
Ejemplo de Programa ARC

Un programa ARC en lenguaje assembler que suma dos enteros:
! Este programa suma dos numeros enteros .begin .org 2048 prog1: ld [x], ld [y], addcc %r1, st %r3, jmpl %r15 x: 15 y: 9 z: 0 .end
%r1 %r2 %r2, %r3 [z] + 4, %r0
!Carga x en !Carga y en !%r3 %r1 !Guarda %r3 !Retorna de
%r1 %r2 + %r2 en z subrutina
4-18
! Uso de los Registr os : ! ! ! ! .begin .org 2048 a_start .equ 3000 %r1 %r2 %r3 %r4 %r5

! Este programa sum a LENGTH numer o s L ongitud del arr eglo a Direccin de inicio del arr eglo a La Suma parcial P u nter o dentro del arr eglo a Contiene u n element o de a ! Comienzo del ensa mbl ado ! Inicio del program a en 2048 ! Direccin del arr eglo a
Un ejemplo de programa mas Complejo
loop:
ld [length], %r1 ! %r1 l ong. del arr eglo a ld [address],%r2 ! %r2 direccin de a andcc %r3, %r0, %r3 ! %r3 0 andcc %r1, %r1, %r0 ! Test # re stantes element o s be done ! Fin alizar cuando length=0 addcc %r1, -4, %r1 ! Decrement ar l ongitud arreglo addcc %r1, %r2, %r4 ! Direccin prximo element o ld %r4, %r5 ! %r5 Memor ia [%r4] addcc %r3, %r5, %r3 ! Sum ar n uevo element o en r3 ba loop ! Repe t ir l azo .
Un programa ARC que suma cinco enteros.
done: length: address:
jmpl
%r15 + 4, %r0 ! Re orno a rutina de llamada 20 a_start a_start 25 10 33 5 7 ! 5 numer o s (20 bytes) e n a ! Inicio del arr eglo a
.org a:
! length/4 val ores siguientes
.end
! Fin en s a mbl ado
4-19
Mquinas de Una, Dos y Tres Direcciones

Consideremos como la Expresin A = B*C + D puede evaluarse por instrucciones de una, dos y tres direcciones. Asumimos que: Las palabras de Direcciones y datos son de 2 bytes. Los Opcodes son de 1 byte. Los operandos se mueven desde y hacia la memoria de a una palabra (dos bytes) por vez. Instruciones de Tres-Direcciones: En este tipo de instrucciones, la expresin A = B*C + D puede ser codificada como: mult add B, C, A D, A, A
Esto es, multiplicar B por C y guardar el resultado en A. ( mult y add son operaciones genricas; no son instrucciones ARC.) Sumar D con A y guardar el resultado en la direccin A. El tamao del programa es 72 = 14 bytes. El trfico de memoria es 14 + 2(23) = 26 bytes.
4-20
Mquinas de una, dos y tres direcciones

Instrucciones de dos direcciones: Para instrucciones de dos direcciones uno de los operandos es sobreescrito por el resultado. El cdigo para la expresin A = B*C + D es: load mult add B, A C, A D, A
El tamao del programa es 3(1+22) 15 bytes. El trfico de memoria: 15 + 22 + 223 31 bytes.
4-21
Mquinas de una, dos y tres direcciones

Instrucciones de una direccin (Acumulador): Aqu se usa un nico registro en la CPU para las operaciones internas conocido como acumulador. El cdigo para la expresin A = B*C + D es ahora: load mult add B C D
store A La instruccin load carga B en el acumulador, mult multiplica C por el acumulador y guarda el resultado en el mismo acumulador y add hace la suma correspondiente. La instruccin store guarda el acumulador en A. El tamao de programa es ahora: (2+1)4 12 bytes, y el trfico de memoria es 12 + 42 20 bytes.
4-22
Modos de Direccionamientos
Cuatro modos de calcular la direccin de un valor en memoria: (1) Un valor constante conocido al momento del ensamble, (2) los contenidos de un registro, (3) la suma de dos registros, (4) suma de un registro y una constante. La tabla d nombres a estos y a otros modos de direccionamientos.
4-23
Llamado a Subrutina Usando Registros

Llamado a subrutina utilizando registros.
! Rutina Invocante . . . ld ld call st . . . 53 10 0 [x], %r1 [y], %r2 add_1 %r3, [z]
! Rutina Invocada ! %r3 %r1 + %r2
add_1: addcc jmpl
%r1, %r2, %r3 %r15 + 4, %r0
x: y: z:
4-24
Llamado a subrutina Area de transferencia de datos

Llamado a subrutina con rea de transferencia de datos en un area separada de memoria. La direcin del rea de memoria est en un registro (en este caso: %r5).
! Rutina Invocante . . . st %r1, [x] st %r2, [x+4] sethi x, %r5 srl %r5, 10, %r5 call add_2 [x+8], %r3 ld . . . !Zona de transf.de datos x: .dwb 3 ! Rutina Invocada ! x[2] x[0] + x[1] add_2: ld ld addcc st jmpl %r5, %r8 %r5 + 4, %r9 %r8, %r9, %r10 %r10, %r5 + 8 %r15 + 4, %r0
4-25
Llamado a Subrutina Pila

Llamado a subrutina utilizando una pila para guardar los parametros.
! Rutina Invocante . . . %sp .equ addcc st addcc st call ld addcc . . . %r14 %sp, -4, %sp %r1, %sp %sp, -4, %sp %r2, %sp add_3 %sp, %r3 %sp, 4, %sp
! Rutina Invocada ! Los argumentos estan en la pila ! %sp[0] %sp[0] + %sp[4] %sp .equ add_3: ld addcc ld addcc st jmpl %r14 %sp, %r8 %sp, 4, %sp %sp, %r9 %r8, %r9, %r10 %r10, %sp %r15 + 4, %r0
4-26
Linea/* Programa en C mostrando llamados encadenados a subrutinas */ No.
Ejemplo de rutinas encadenadas

Un programa en C mostrando llamados encadenados
00 main() 01 { 02 int w, z; 03 w = func_1(1,2); 04 z = func_2(10); 05 } 06 int 07 int 08 { 09 10 11 12 13 } 14 int 15 int 16 { 17 18 19 20 21 } func_1(x,y) x, y; int i, j; i = x * x; j = i + y; return(j);
/* /* /* /*
Variables Subrutina Subrutina Fin de la
Locales */ a la func_1 */ a la func_2 */ rutina principal */
/* Calcula x * x + y */ /* Pase de Parametros a func_1 */ /* Variables Locales */
/* Retorna j a rutina invocante */
func_2(a) a;
/* Calcula a * a + a + 5 */ /* Pase de parametros a func_2 */
int m, n; /* Variables Locales */ n = a + 5; m = func_1(a,n); return(m); /* Retorna m a rutina invocante */
4-27
0 0

0 Beginning of stack frame %sp %sp %sp Stack 232 4 232 4
2 1
Rutinas encadenadas con Pilas (continuacin)
Free area
Free area
Free area
%r15 2 1
Stack 232 4
Stack
(a) Configuracion Inicial. w y z estn disponibles en la pila. (Linea 00 del programa.)
(b) (c) El llamado a rutina empuja Despues del Call la rutina los argumentos en la pila, invocada guarda el PC de la rutina antes de llamar a func_1. invocante (%r15)en la pila. (Linea 03 del programa.) (Line 06 del programa.) 0 0
Area Libre
Stack frame for func_1 Area Libre Area Libre
(a-f) comportamiento %sp de la Pila durante la ejecucin del programa en C mostrado con 232 4 anterioridad.
j i %r15 2 1
%sp
%sp Stack 232 4
Pila 232 4
Pila
(d) (e) Se reserva espacio en la pila para Los valores de Retorno de func_1, variables locales i func_1 se ubican en la y j. (Line 09 del pila, justo antes del retorno. programa.) (Line 12 del programa.)
(f) La rutina invocante "extrae" desde la pila los valores de retorno de func_1 (Line 03 del programa.)
4-28

func_1 Marco de pila 0
Area Libre
j i %r15 15 10 n m %r15 10
0 %sp Marco de Pila para func_2
Rutinas encadenadas con pilas (continuacin)
Area libre %sp

n m %r15 10
Area libre %sp

115 n m %r15 10
Pila 232 4 232 4
Pila
Marco de pila para func_2
Pila
(g) (h) Se crea un marco de pila para Se crea un marco de pila para la func_2 como resultado la func_1 como resultado del llamado a funcin de la del llamado a funcin de la linea 04 del programa. linea 19 del programa. 0
232 4
(i) func_1 coloca valores de retorno en la pila. (Linea 12 del programa.)
0 (g-k) Comportamiento de la Pila durante la ejecucin del programa en C mostrado con %sp anterioridad 232 4
Area Libre
Area Libre
115
%sp Pila 232 4
Pila
(j) func_2 coloca valores de retorno en la pila. (Linea 20 del programa.)

(k) Finaliza el programa. La pila se restaura a su configuracin. (Lineas 04 y 05 del programa.)

4-29
Direccin
Entrada y Salida para la ISA

Mapa de memoria para la ARC, mostrando el mapeo de memoria de I/O.
Contenido 32 bits
Reservado para rutinas de arranque y rutinas grficas Memoria de video ad. #1 Memoria de video ad. #2
216 217 219
Zona sin uso
222
Memoria de trabajo
Tope de la pila
Puntero de Pila(SP)
Pila de Sistema
223 4
Fondo de la pila
FFFFEC 16 Parpadeo de pantalla Touchscreen x FFFFF0 16 FFFFF4 16 Touchscreen y 224 4 byte

Espacio de I/O
224 1
4-30
Pantalla sensible al tacto

Un usuario seleccionando un objeto en una pantalla:
LEDs (Diodos emisores de Luz)

El Usuario interrumpe el haz
Detector
4-31
Diagrama de flujo para dispositivo I/O
Leer registro X Leer registro Y
Compare valores X e Y anteriores con los nuevos
No
Se modificaron XeY? Si Parpadeo de pantalla
Diagrama que ilustra la estructura de control de un programa que verifica una pantalla sensible al tacto.
Actualizar registros XeY

Principios de Arquitectura de Computadoras - M. Murdocca y V. Heuring
5-1
Chapter 5: Languages and the Machine

Captulo 5: Los Lenguajes y la Mquina
5-5
El Proceso de Ensamblado
* El proceso de transformar un programa en lenguaje ensamblador en un programa en lenguaje de mquina se conoce como proceso de ensamblado
* Los ensambladores comerciales proveen las siguientes prestaciones:

-- Permite al programador especificar la ubicacin de variables y programas
-- Provee expresiones nemnicas en el lenguaje de programacin para todas las instrucciones del lenguaje de mquina y modos de direccionamientos y traduce sentencias vlidas al lenguaje absoluto.
-- Permitir el uso de rtulos simblicos para representar direcciones y constantes
-- Ofrecerle al programador cificar la direccin de inicio de

un programa, si existiera.
-- Incluir un mecanismo que permita la definicin de variables en un programa escrito en lenguaje simblico y el uso de las mismas en otro programa ensamblado por separado. -- Proveer la expansin de macro rutinas (se definen una sola vez).
5-6
Ejemplo de ensamblado
Exploraremos como el proceso de ensamblado genera un programa ARC a travs del proceso de "Ensamblado a Mano".
! Este programa suma dos nmeros .begin .org 2048 ld [x], ld [y], addcc %r1, st %r3, jmpl %r15 15 9 0 .end
main:
%r1 %r2 %r2, %r3 [z] + 4, %r0
! ! ! ! !
Carga x en %r1 Carga y en %r2 %r3 %r1 + %r2 Almacena %r3 en z Retorno
x: y: z:
5-7
op SETHI Format
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
0 0 0 0 0
rd cond
op2 op2
imm22 disp22
Formato de instrucciones y formato del PSR para una mquina ARC
Branch Format
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
CALL format
0 1
disp30 i
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
Arithmetic Formats
1 0 1 0
rd rd
op3 op3
rs1 rs1
0 0 0 0 0 0 0 0 0 1 simm13
rs2
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
1 1 1 1
rd rd
op3 op3
rs1 rs1
0 0 0 0 0 0 0 0 0 1 simm13
rs2
Memory Formats
op 00 01 10 11
Format SETHI/Branch CALL Arithmetic Memory
op2
Inst.
op3 (op=11) 000000 ld 000100 st
cond branch 0001 0101 0110 0111 1000 be bcs bneg bvs ba
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
PSR
n z v c
5-8
Cdigo Ensamblado
ld [x], %r1 ld [y], %r2 st %r3, [z] jmpl %r15+4, %r0 15 9 0 1100 0010 0000 0000 0010 1000 0001 0100 1100 0100 0000 0000 0010 1000 0001 1000 1100 0110 0010 0000 0010 1000 0001 1100 1000 0001 1100 0011 1110 0000 0000 0100 0000 0000 0000 0000 0000 0000 0000 1111 0000 0000 0000 0000 0000 0000 0000 1001 0000 0000 0000 0000 0000 0000 0000 0000
addcc %r1,%r2,%r3 1000 0110 1000 0000 0100 0000 0000 0010
5-9
Referencia Previa
Un ejemplo de Referencia Previa
. . . callsub_r . . . st %r1, [w] . . . ! La subrutina es invocada aqu
sub_r:
! La subrutina se define aqu
5-10
! Este programa suma tantos numeros como indica " LENGTH " ! Uso del Registro : %r1 L ongitud del arreglo a ! %r2 Direccin de inicio del arreglo a ! %r3 La suma Parcial ! %r4 P untero al arreglo a ! %r5 contiene un elemento de a .begin ! comienzo de traduccin .org 2048 ! comienzo de program a en 2048 a_start .equ 3000 ! Direccin del arreglo a ld [length], %r1 ! %r1 l ong. del arreglo a ld [address],%r2 ! %r2 direccin de a andcc %r3, %r0, %r3 ! %r3 0 andcc %r1, %r1, %r0 ! Ver # elementos restantes be done ! Fin aliza cuando length=0 addcc %r1, -4, %r1 ! Decrement ar tamao arreglo addcc %r1, %r2, %r4 ! Direccin prximo elemento ld %r4, %r5 !%r5 direccin Memor ia [%r4] addcc %r3, %r5, %r3 ! Sum ar n uevo element o en r3 ba done: length: address: .org a: jmpl loop ! Repe S tir l azo .
Creando una
Tabla de Smbolos
Smbolo a_start length (a)
Smbolo a_start length address loop done a (b) Valor 3000 2092 2096 2060 2088 3000
Valor 3000
loop:
Value 3000 bytes) en
%r15 + 4, %r0 ! Ret or n o a rutina principal 20 a_start a_start 25 10 33 5 7
a_start ! 5 numer o s length

!
(20
Comienzo del arreglo a
! length/4 val ores siguientes
(a)
.end
! Fin de traduccin
5-11
Programa Ensamblado
Contador de posicin
Instruccin
Cdigo Objeto
2048 2052 2056 2060 2064 2068 2072 2076 2080 2084 2088 2092 2096 3000 3004 3008 3012 3016
.begin .org 2048 a_start .equ 3000 ld [length],%r1 ld [address],%r2 andcc %r3,%r0,%r3 loop: andcc %r1,%r1,%r0 be done addcc %r1,-4,%r1 addcc %r1,%r2,%r4 ld %r4,%r5 ba loop addcc %r3,%r5,%r3 done: jmpl %r15+4,%r0 length: 20 address: a_start .org a_start a: 25 -10 33 -5 7 .end
11000010 00000000 00101000 00101100 11000100 00000000 00101000 00110000 10000110 10001000 11000000 00000000 10000000 10001000 01000000 00000001 00000010 10000000 00000000 00000110 10000010 10000000 01111111 11111100 10001000 10000000 01000000 00000010 11001010 00000001 00000000 00000000 00010000 10111111 11111111 11111011 10000110 10000000 11000000 00000101 10000001 11000011 11100000 00000100 00000000 00000000 00000000 00010100 00000000 00000000 00001011 10111000 00000000 00000000 00000000 00011001 11111111 11111111 11111111 11110110 00000000 00000000 00000000 00100001 11111111 11111111 11111111 11111011 00000000 00000000 00000000 00000111
6-1
Chapter 6: Datapath and Control

Captulo 6: Datapath y Control
6-2
Contenido del captulo

6.1 Elementos bsicos de Microarquitectura 6.2 Una Microarquitectura para la mquina ARC 6.3 Control Cabledo
4-9
El Ciclo Fetch-Ejecucin
Los pasos que sigue una unidad de control para ejecutar un programa son: (1) Buscar de la memoria la siguiente instruccin a ejecutar. (2) Decodificar el opcode (cdigo de operacin). (3) Leer operando(s) desde la memoria principal, si hubiera alguno. (4) Ejecutar la instruccin y almacenar resultados. (5) Ir al paso 1. Esto se conoce como el ciclo fetch-ejecucin.
6-4
Una Microarquitectura en Alto Nivel

Una microarquitectura consiste de la unidad de control y de los registros visibles por el programador, unidades funcionales como la ALU, y todo registro adicional que requiera la Unidad de Control.
Registros U.de Control ALU
Datapath (Seccin de Datos)
Seccin de Control
BUS DE SISTEMA
4-11
Subconjunto de Instrucciones ARC

Nemonico Significado Cargar registro desde la memoria Almacenar un registro en la memoria Cargar los 22 bits mas significativos de un registro Operacin lgica AND bit a Bit Operacin lgica OR bit a bit Operacin lgica NOR bit a bit Desplazar a derecha (lgico)agrega ceros a la izq. Sumar Salto Llamado a subrutina Salto y Enlace (retorno de subrutina) Bifurcacin o Salto por igual Bifurcacin o Salto por negativo Bifurcacin o Salto por acarreo Bifurcacin o Salto por desborde u "overflow" Bifurcacin o Salto incondicional
Memoria
ld st sethi andcc
Lgicas
orcc orncc srl
Aritmeticas
addcc call jmpl be
Control
bneg bcs bvs ba
4-14
Instrucciones ARC y Formatos PSR

op
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
Formato SETHI Formato de salto
0 0 0 0 0
rd cond
op2 op2
imm22 disp22
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
Formato de llamada a subrutina
0 1
disp30 i
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
Formatos Aritmticos
1 0 1 0
rd rd
op3 op3
rs1 rs1
0 0 0 0 0 0 0 0 0 1 simm13
rs2
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
1 1 Formatos de Memoria 1 1
rd rd
op3 op3
rs1 rs1
0 0 0 0 0 0 0 0 0 1 simm13
rs2
op 00 01 10 11
Format SETHI/Branch CALL Aritmticas Memoria
op2
Inst.
op3 (op=11) 000000 ld 000100 st
cond salto 0001 0101 0110 0111 1000 be bcs bneg bvs ba
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
PSR
n z v c
6-7
C bus
0 1 2 3
A bus %r0 %r1 %r2 %r3 %r4 %r5 %r6 %r7 %r8 %r9
B bus

38
a0
A Decoder
a37
C 1 Decoder
c37
37
4 5 6 7 8
38
b0
b37
B Decoder
6 From Control Unit
CLOCK UNIT
10 %r10
Datapath ARC
32 64-to-32 MUX C Bus MUX
32
. . .
30 %r30 31 %r31
%pc
33 %temp0 34 %temp1 35 %temp2 36 %temp3 37
Data From Main Memory
%ir
32
Address To Main Memory
MUX Control Line (From Control Unit) 32
24
32
32
Data To Main Memory
To Control Unit
F0 F1 ALU F 2 F3
From Control Unit
4 n, z, v, c Set Condition Codes (SCC)
6-8
Operaciones ARC de la ALU

F3 F2 F1 F0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Operacin ANDCC (A, B) ORCC (A, B) NORCC (A, B) ADDCC (A, B) SRL (A, B) AND (A, B) OR (A, B) NOR (A, B) ADD (A, B) LSHIFT2 (A) LSHIFT10 (A) SIMM13 (A) SEXT13 (A) INC (A) INCPC (A) RSHIFT5 (A) Cambia Cdigo Condicin si si si si no no no no no no no no no no no no
6-14
Seccin de Datos (Datapath)
To A Decoder 6 A MUX
Select

Seccin de Control
Control Store Address Incrementer (CSAI) 11 1 00
8 11 00 = Next 01 = Jump 10 = Inst. Dec.
Microarquitectura de ARC
To C Decoder 6 C MUX
Select
MIR 0, rs1 A field
Area de trabajo
MIR C field 0, rd
To B Decoder 6 B MUX
Next Decode Jump CS Address MUX 11
MIR 0, rs2 B field
2048 palabras de Control 41 bit Almacenamiento

Select
%ir rd rs2
%i r rs1 ops
41
A A M U X B B M U X C C M U RW XDR ALU COND
Microcode Instruction Register (MIR)

JUMP ADDR
C bus
IR[13]
CLOCK UNIT
A bus
32
B bus
2
IR[30,31,19-24]
32
32 1
64-to-32 MUX C Bus MUX
F0 F1 ALU F 2 F3
3 4 4 %psr
Control branch logic (CBL)
4 n, z , v , c
Set Condition Codes
Data In RD WR Memoria Principal Address 232 byte Data Out

address space
Acknowledge (ACK)
6-15
Formato de Microcdigo
A M U X B M U X C M U RW X D R ALU COND
JUMP ADDR
6-16
Valores para el campo COND de la Microcdigo

C2 C1 C0 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 Operacin Usar NEXT ADDR Usar JUMP ADDR if n = 1 Usar JUMP ADDR if z = 1 Usar JUMP ADDR if v = 1 Usar JUMP ADDR if c = 1 Usar JUMP ADDR if IR[13] = 1 Usar JUMP ADDR DECODE
6-17
Formato DECODE para la Direccin de la Microinstruccin

op 1 IR bits
31 30 24 23 22 21 20 19
op3 0 0 op2
6-19
Address
0000: 0001: 00// 1152: 00// 1280: 1281: 1282: 1283: 0//0 1600: 1601: 1602: 1603: 00// 1604: 1605: 1606: 1607: 00// 1608: 1609: 1610: 1611: 00// 1624: 1625: 1626: 1627: 00// 1688: 1689: 1690: 1691: 00// 1760: 1761:
Operation Statements
Microprograma parcial ARC
R[ir] AND(R[pc],R[pc]); READ; DECODE; / sethi R[rd] LSHIFT10(ir); GOTO 2047; / call R[15] AND(R[pc],R[pc]); R[temp0] ADD(R[ir],R[ir]); R[temp0] ADD(R[temp0],R[temp0]); R[pc] ADD(R[pc],R[temp0]); GOTO 0; / addcc IF R[IR[13]] THEN GOTO 1602; R[rd] ADDCC(R[rs1],R[rs2]); GOTO 2047; R[temp0] SEXT13(R[ir]); R[rd] ADDCC(R[rs1],R[temp0]); GOTO 2047; / andcc IF R[IR[13]] THEN GOTO 1606; R[rd] ANDCC(R[rs1],R[rs2]); GOTO 2047; R[temp0] SIMM13(R[ir]); R[rd] ANDCC(R[rs1],R[temp0]); GOTO 2047; / orcc IF R[IR[13]] THEN GOTO 1610; R[rd] ORCC(R[rs1],R[rs2]); GOTO 2047; R[temp0] SIMM13(R[ir]); R[rd] ORCC(R[rs1],R[temp0]); GOTO 2047; / orncc IF R[IR[13]] THEN GOTO 1626; R[rd] NORCC(R[rs1],R[rs2]); GOTO 2047; R[temp0] SIMM13(R[ir]); R[rd] NORCC(R[rs1],R[temp0]); GOTO 2047; / srl IF R[IR[13]] THEN GOTO 1690; R[rd] SRL(R[rs1],R[rs2]); GOTO 2047; R[temp0] SIMM13(R[ir]); R[rd] SRL(R[rs1],R[temp0]); GOTO 2047; / jmpl IF R[IR[13]] THEN GOTO 1762; R[pc] ADD(R[rs1],R[rs2]); GOTO 0;
/ Read an ARC instruction from main memory / 256-way jump according to opcode / Copy imm22 field to target register / Save %pc in %r15 / Shift disp30 field left / Shift again / Jump to subroutine
Comment Chapter 6: Datapath and Control
/ Is second source operand immediate? / Perform ADDCC on register sources / Get sign extended simm13 field / Perform ADDCC on register/simm13 / sources / Is second source operand immediate? / Perform ANDCC on register sources / Get simm13 field / Perform ANDCC on register/simm13 / sources / Is second source operand immediate? / Perform ORCC on register sources / Get simm13 field / Perform ORCC on register/simm13 sources
/ Is second source operand immediate? / Perform ORNCC on register sources / Get simm13 field / Perform NORCC on register/simm13 / sources / Is second source operand immediate? / Perform SRL on register sources / Get simm13 field / Perform SRL on register/simm13 sources
/ Is second source operand immediate? / Perform ADD on register sources
6-20
Microprograma Parcial ARC (continuacin)
1762: R[temp0] SEXT13(R[ir]); / Get sign extended simm13 field 1763: R[pc] ADD(R[rs1],R[temp0]); Chapter / Perform on register/simm13 sources 6: ADD Datapath and Control GOTO 0; 00// / ld 1792: R[temp0] ADD(R[rs1],R[rs2]); / Compute source address IF R[IR[13]] THEN GOTO 1794; 1793: R[rd] AND(R[temp0],R[temp0]); / Place source address on A bus READ; GOTO 2047; 1794: R[temp0] SEXT13(R[ir]); / Get simm13 field for source address 1795: R[temp0] ADD(R[rs1],R[temp0]); / Compute source address GOTO 1793; 00// / st 1808: R[temp0] ADD(R[rs1],R[rs2]); / Compute destination address IF R[IR[13]] THEN GOTO 1810; 1809: R[ir] RSHIFT5(R[ir]); GOTO 40; / Move rd field into position of rs2 field / by shifting to the right by 25 bits. 40: R[ir] RSHIFT5(R[ir]); 41: R[ir] RSHIFT5(R[ir]); 42: R[ir] RSHIFT5(R[ir]); 43: R[ir] RSHIFT5(R[ir]); 44: R[0] AND(R[temp0], R[rs2]); / Place destination address on A bus and WRITE; GOTO 2047; / place operand on B bus 1810: R[temp0] SEXT13(R[ir]); / Get simm13 field for destination address 1811: R[temp0] ADD(R[rs1],R[temp0]); / Compute destination address GOTO 1809; 00// / Branch instructions: ba, be, bcs, bvs, bneg 1088: GOTO 2; / Decoding tree for branches 2: R[temp0] LSHIFT10(R[ir]); / Sign extend the 22 LSBs of %temp0 3: R[temp0] RSHIFT5(R[temp0]); / by shifting left 10 bits, then right 10 4: R[temp0] RSHIFT5(R[temp0]); / bits. RSHIFT5 does sign extension. 5: R[ir] RSHIFT5(R[ir]); / Move COND field to IR[13] by 6: R[ir] RSHIFT5(R[ir]); / applying RSHIFT5 three times. (The 7: R[ir] RSHIFT5(R[ir]); / sign extension is inconsequential.) 8: IF R[IR[13]] THEN GOTO 12; / Is it ba? R[ir] ADD(R[ir],R[ir]); 9: IF R[IR[13]] THEN GOTO 13; / Is it not be? R[ir] ADD(R[ir],R[ir]); 10: IF Z THEN GOTO 12; / Execute be R[ir] ADD(R[ir],R[ir]); 11: GOTO 2047; / Branch for be not taken 12: R[pc] ADD(R[pc],R[temp0]); / Branch is taken GOTO 0; 13: IF R[IR[13]] THEN GOTO 16; / Is it bcs? R[ir] ADD(R[ir],R[ir]); 14: IF C THEN GOTO 12; / Execute bcs 15: GOTO 2047; / Branch for bcs not taken 16: IF R[IR[13]] THEN GOTO 19; / Is it bvs? 17: IF N THEN GOTO 12; / Execute bneg 18: GOTO 2047; / Branch for bneg not taken 19: IF V THEN GOTO 12; / Execute bvs 20: GOTO 2047; / Branch for bvs not taken 1999 M. Murdocca and V. Heuring 2047: R[pc] INCPC(R[pc]); GOTO 0; / Increment %pc and start over
6-22
Microstore Address A
A M U X
B M U X
C Chapter 6: Datapath and Control M U RW X D R ALU COND JUMP ADDR
Microprograma ARC Ensamblado
0 1 1152 1280 1281 1282 1283 1600 1601 1602 1603 1604 1605 1606 1607 1608 1609 1610 1611 1624 1625 1626 1627 1688 1689 1690 1691 1760 1761 1762 1763 1792
10000001000000100101010010100000000000000 00000000000000000000000010111100000000000 10010100000000000000100101011011111111111 10000001000000001111000010100000000000000 10010101001010100001000100000000000000000 10000101000010100001000100000000000000000 10000001000010100000000100011000000000000 00000000000000000000000010110111001000010 00000010000001000000100001111011111111111 10010100000000100001000110000000000000000 00000011000010000000100001111011111111111 00000000000000000000000010110111001000110 00000010000001000000100000011011111111111 10010100000000100001000101100000000000000 00000011000010000000100000011011111111111 00000000000000000000000010110111001001010 00000010000001000000100000111011111111111 10010100000000100001000101100000000000000 00000011000010000000100000111011111111111 00000000000000000000000010110111001011010 00000010000001000000100001011011111111111 10010100000000100001000101100000000000000 00000011000010000000100001011011111111111 00000000000000000000000010100011010011010 00000010000001000000100010011011111111111 10010100000000100001000101100000000000000 00000011000010000000100010011011111111111 00000000000000000000000010110111011100010 00000010000001100000000100011000000000000 10010100000000100001000110000000000000000 00000011000010100000000100011000000000000 00000010000001100001000100010111100000010
6-23
A
A M U X
B M U X
C Chapter 6: Datapath and Control M U RW X D R ALU COND JUMP ADDR
Microprograma ARC Ensamblado (continuacin)
1793 1 0 0 0 0 1 0 1 0 0 0 0 1 0 0 0 0 0 0 0 1 1 0 0 1 0 1 1 1 0 1 1 1 1 1 1 1 1 1 1 1 1794 1 0 0 1 0 1 0 0 0 0 0 0 0 0 1 0 0 0 0 1 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1795 0 0 0 0 0 0 1 1 0 0 0 0 1 0 1 0 0 0 0 1 0 0 0 1 0 0 0 1 1 0 1 1 1 0 0 0 0 0 0 0 1 1808 0 0 0 0 0 0 1 0 0 0 0 0 0 1 1 0 0 0 0 1 0 0 0 1 0 0 0 1 0 1 1 1 1 0 0 0 1 0 0 1 0 1809 1 0 0 1 0 1 0 0 0 0 0 0 0 0 1 0 0 1 0 1 0 0 0 1 1 1 1 1 1 0 0 0 0 0 0 1 0 1 0 0 0 40 1 0 0 1 0 1 0 0 0 0 0 0 0 0 1 0 0 1 0 1 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 41 1 0 0 1 0 1 0 0 0 0 0 0 0 0 1 0 0 1 0 1 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 42 1 0 0 1 0 1 0 0 0 0 0 0 0 0 1 0 0 1 0 1 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 43 1 0 0 1 0 1 0 0 0 0 0 0 0 0 1 0 0 1 0 1 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 44 1 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1 0 1 0 1 1 1 0 1 1 1 1 1 1 1 1 1 1 1 1810 1 0 0 1 0 1 0 0 0 0 0 0 0 0 1 0 0 0 0 1 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1811 0 0 0 0 0 0 1 1 0 0 0 0 1 0 1 0 0 0 0 1 0 0 0 1 0 0 0 1 1 0 1 1 1 0 0 0 1 0 0 0 1 1088 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 1 1 0 0 0 0 0 0 0 0 0 0 1 0 2 10010100000000100001000101000000000000000 3 10000100000000100001000111100000000000000 4 10000100000000100001000111100000000000000 5 10010100000000100101000111100000000000000 6 10010100000000100101000111100000000000000 7 10010100000000100101000111100000000000000 8 10010101001000100101000100010100000001100 9 10010101001000100101000100010100000001101 10 1 0 0 1 0 1 0 1 0 0 1 0 0 0 1 0 0 1 0 1 0 0 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 1 1 0 0 11 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 1 1 0 1 1 1 1 1 1 1 1 1 1 1 12 1 0 0 0 0 0 0 1 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 1 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 13 1 0 0 1 0 1 0 1 0 0 1 0 1 0 1 0 0 1 0 1 0 0 0 1 0 0 0 1 0 1 0 0 0 0 0 0 1 0 0 0 0 14 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 1 0 0 0 0 0 0 0 0 0 1 1 0 0 15 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 1 1 0 1 1 1 1 1 1 1 1 1 1 1 16 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 1 0 1 0 0 0 0 0 0 1 0 0 1 1 17 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 1 0 0 0 0 0 0 0 1 1 0 0 18 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 1 1 0 1 1 1 1 1 1 1 1 1 1 1 19 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 1 1 0 0 0 0 0 0 0 1 1 0 0 20 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 1 1 0 1 1 1 1 1 1 1 1 1 1 1 2047 1000000000000010000000011 10 1 1 M. 00 0 0 0 0 0and 0 0V. 00 0 Principles of Computer Architecture by M. Murdocca and V. Heuring 1999 Murdocca Heuring
6-27
Hardware Description Language

Prembulo MODULE: MOD_4_COUNTER. INPUTS: x. OUTPUTS: Z[2]. MEMORY: 0: Z 0,0; GOTO {0 CONDITIONED 1 CONDITIONED 1: Z 0,1; GOTO {0 CONDITIONED 2 CONDITIONED 2: Z 1,0; GOTO {0 CONDITIONED 3 CONDITIONED 3: Z 1,1; GOTO 0. END SEQUENCE. END MOD_4_COUNTER.
Secuencia HDL para un contador mdulo 4 reiniciable.

Sentencias
ON x, ON x}. ON x, ON x}. ON x, ON x}.
Eplogo
6-28
Circuito Derivado a partir de HDL

Diseo lgico para un contador mdulo 4 descripto en HDL.
Z[0]
SECCION de DATOS SECCION de CONTROL
Z[1]
D Q 0 CLK
D Q 1
D Q 2
D Q 3
6-29
MODULE: ARC_CONTROL_UNIT. Chapter 6: Datapath and Control INPUTS: OUTPUTS: C, N, V, Z. ! Fijadas por la ALU MEMORY: R[16][32], pc[32], ir[32], temp0[32], temp1[32], temp2[32], temp3[32]. 0: ir AND(pc, pc); Read 1; ! Bsqueda de la Instruccin ! Decodificar el campo op 1: GOTO {2 CONDITIONED ON ir[31]ir[30], ! formato Branch/sethi: op=00 4 CONDITIONED ON ir[31]ir[30], ! formato Call: op=01 8 CONDITIONED ON ir[31]ir[30], ! formato Aritmetico : op=10 10 CONDITIONED ON ir[31]ir[30]}. ! formato de Memoria: op=11 ! Decodficar campo op2 2: GOTO 19 CONDITIONED ON ir[24]. ! si es formato de salto ir a 19 3: R[rd] ir[imm22]; ! sethi GOTO 20. 4: R[15] AND(pc, pc). ! call:Guardar pc en registro 15 5: temp0 ADD(ir, ir). ! desplazar campo disp30 a izq. 6: temp0 ADD(ir, ir). ! desplazar nuevamente 7: pc ADD(pc, temp0); GOTO 0. ! Saltar a subrutina ! Colocar el segundo operando origen en temp0 para el formato Aritmetico 8: temp0 { SEXT13(ir) CONDITIONED ON ir[13]NOR(ir[19:22]), ! addcc R[rs2] CONDITIONED ON ir[13]NOR(ir[19:22]), ! addcc SIMM13(ir) CONDITIONED ON ir[13]OR(ir[19:22]), ! Remaining R[rs2] CONDITIONED ON ir[13]OR(ir[19:22])}. ! Instrucciones Aritmticas ! Decodificar el campo op3 para el formato Aritmetico 9: R[rd] { ADDCC(R[rs1], temp0) CONDITIONED ON XNOR(IR[19:24], 010000), ! addcc ANDCC(R[rs1], temp0) CONDITIONED ON XNOR(IR[19:24], 010001), ! andcc ORCC(R[rs1], temp0) CONDITIONED ON XNOR(IR[19:24], 010010), ! orcc NORCC(R[rs1], temp0) CONDITIONED ON XNOR(IR[19:24], 010110), ! orncc SRL(R[rs1], temp0) CONDITIONED ON XNOR(IR[19:24], 100110), ! srl ADD(R[rs1], temp0) CONDITIONED ON XNOR(IR[19:24], 111000)}; ! jmpl GOTO 20. ! cargar en temp0 el segundo operando fuente si es formato de Memoria 10: temp0 {SEXT13(ir) CONDITIONED ON ir[13], R[rs2] CONDITIONED ON ir[13]}. 11: temp0 ADD(R[rs1], temp0). ! Decodificar el campo op3 field para el formato de Memoria GOTO {12 CONDITIONED ON ir[21], ! ld 13 CONDITIONED ON ir[21]}. ! st 12: R[rd] AND(temp0, temp0); Read 1; GOTO 20. 13: ir RSHIFT5(ir).
HDL for ARC

Descripcin HDL de la Unidad de control ARC.
6-30
HDL para ARC (continuacin)
14: 15: 16: 17: 18: 19:
ir RSHIFT5(ir). ir RSHIFT5(ir). ir RSHIFT5(ir). ir RSHIFT5(ir). r0 AND(temp0, R[rs2]); Write 1; GOTO 20. pc { ! Instrucciones de salto (Branch) ADD(pc, temp0) CONDITIONED ON ir[28] + ir[28]ir[27]Z + ir[28]ir[27]ir[26]C + ir[28]ir[27]ir[26]ir[25]N + ir[28]ir[27]ir[26]ir[25]V, INCPC(pc) CONDITIONED ON ir[28]ir[27]Z + ir[28]ir[27]ir[26]C + ir[28]ir[27]ir[26]ir[25]N + ir[28]ir[27]ir[26]ir[25]V}; GOTO 0. 20: pc INCPC(pc); GOTO 0. END SEQUENCE. END ARC_CONTROL_UNIT.
6-31

IR[30] IR[31] D Q 1 D Q 2 IR[24] CS3 D Q 3
Circuito HDL-ARC
La seccin de control cableada de ARC: generacin de seales de control.
CS0 D Q 0 CLK
CS4 D Q 4 D Q 5 D Q 6
CS6 CS5 D Q 7 CS0
IR[21] CS10 D Q 8 D Q 9 CS9 D Q 10 D Q 11 CS11
CS8
CS13 D Q 12 CS12 D Q 13 D Q 14
CS14 D Q 15 CS15
CS16 D Q 16 D Q 17
CS17 D Q 18 CS18 D Q 19
CS19
CS20 D Q 20
6-32
Circuito HDL-ARC (continuacin)

IR[23] IR[22] IR[24]
Seccin de control cableado de ARC: Seales desde la seccin de datos de la unidad de control a la trayectoria de datos.
IR[20] IR[21] IR[28] Z IR[27] IR[28] IR[27] IR[26] C IR[28] IR[27] IR[26] IR[25] N IR[28] IR[27] IR[26] IR[25] C
IR[21] IR[19] IR[13] CS8
CS3 CS2 CS 0 CS4 CS1 ALU[0]
IR[19] IR[20] IR[21] IR[22]
0 IR[13] CS8 IR[13] CS10 CS5 CS6 CS12 0 0
A[1] A[3] A[4] A[0]
IR[23] IR[24]
IR[19] IR[22]
CS9 CS17 CS20 ALU[1]
CS18 CS8 CS16 CS10 IR[13] CS18
IR[13] IR[19] IR[21] IR[22] CS19 CS8
CS15 CS14 CS16 CS18 Write CS17 CS7 CS0 CS4 BMUX CS19 CS 20
CS13
A[2]
A[5]
IR[20]
C[2] CS9 CS3 CS12 CS9 AMUX B[0] Read B[1] C[0] B[2] C[3] B[3] C[4] B[4] CMUX C[1]
CS13
CS15 CS14
IR[13] CS8 IR[19] IR[20] IR[21] IR[22] IR[28] CS19
CS2 CS12 CS4 CS1 CS3 CS10 ALU[2] CS14 CS13 CS15
CS11 CS0 CS12
CS9
IR[24] IR[23] IR[22]
IR[19] IR[20] IR[21] IR[24] CS9 IR[23]
CS18 CS 20 CS17 CS16
CS5 CS6 CS11 CS8CS7 ALU[3]
IR[22] CS13 IR[21] IR[19] CS15 IR[20] CS14 CS16
CS20 CS19 CS17
C[5]
B[5]

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1-1

Principios de Arquitectura de Computadoras

Principios de Arquitectura de Computadoras por M. Murdocca and V. Heuring

1999 M. Murdocca and V. Heuring

Contenido del Captulo

Principios de Arquitectura de Computadoras por M. Murdocca and V. Heuring

1999 M. Murdocca and V. Heuring

Principios de Arquitectura de Computadoras por M. Murdocca and V. Heuring

1999 M. Murdocca and V. Heuring

Maquina calculadora de Pascal

(Fuente: IBM Fotografa de Archivo.

Principios de Arquitectura de Computadoras por M. Murdocca and V. Heuring

1999 M. Murdocca and V. Heuring

El Modelo de von Neumann

Unidad de Aritmetica y logica(ALU)

Principios de Arquitectura de Computadoras por M. Murdocca and V. Heuring

1999 M. Murdocca and V. Heuring

El modelo de Interconexin de Bus

Bus de Datos Bus de Direcciones Bus de Control

Principios de Arquitectura de Computadoras por M. Murdocca and V. Heuring

Niveles de las Maquinas

Principios de Arquitectura de Computadoras por M. Murdocca and V. Heuring

Una Computadora Tpica

Ranuras para conectar Tarjetas de expansin

Principios de Arquitectura de Computadoras por M. Murdocca y V. Heuring

1999 M. Murdocca and V. Heuring

(Source: TYAN Computer, http://www.tyan.com)

Plug-in expansion card slots

Pentium II processor slot (ALU/control)

Battery Power supply connector

Principios de Arquitectura de Computadoras por M. Murdocca and V. Heuring

1999 M. Murdocca and V. Heuring

Manchester University Mark I

Principios de Arquitectura de Computadoras por M. Murdocca and V. Heuring

1999 M. Murdocca and V. Heuring

Principios de Arquitectura de Computadoras por M. Murdocca and V. Heuring

1999 M. Murdocca and V. Heuring

Chapter 2: Data Representation

Principles of Computer Architecture

Chapter 2: Data Representation

Principles of Computer Architecture by M. Murdocca and V. Heuring

1999 M. Murdocca and V. Heuring

Chapter 2: Data Representation

Principles of Computer Architecture by M. Murdocca and V. Heuring

1999 M. Murdocca and V. Heuring

Chapter 2: Data Representation

Fixed Point Numbers

Principles of Computer Architecture by M. Murdocca and V. Heuring

1999 M. Murdocca and V. Heuring

Chapter 2: Data Representation

Weighted Position Code

Chapter 2: Data Representation

Base Conversion with the Remainder Method

Chapter 2: Data Representation

Base Conversion with the Multiplication Method

Putting it all together, 23.37510 = 10111.0112.

Chapter 2: Data Representation

Nonterminating Base 2 Fraction

Chapter 2: Data Representation

Base 2, 8, 10, 16 Number Systems

Chapter 2: Data Representation

More on Base Conversions

Chapter 2: Data Representation