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DEPARTME T O! E"E#TRO I#S A D #OMM$ I#ATIO V"SI Design %E# & '()* E+PERIME T O, - (.
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T/EOR01 A full adder is a logical circuit that performs an addition operation on three binary digits. The full adders produce a sum and carry value, which are both binary digits.
V/D" code1 library IEEE; use IEEE. T!"#$%I&"11'(.A##; use IEEE. T!"#$%I&"A)IT*.A##; use IEEE. T!"#$%I&"+, I%,E!.A##; entity fadder is port- a,b,cin . in bit; s,cout . out bit/; end fadder; architecture 0ehavioral of fadder is begin s 12 a 3or b 3or cin; cout 12 -a and b/ or -a and cin/ or -b and cin/; end 0ehavioral; TR$T/ TA2"E 1 In3ut #in 2 A 4 4 4 4 4 1 4 1 4 4 1 1 1 4 4 1 4 1 1 1 4 1 1 1 Out3ut S #out 4 4 1 4 1 4 4 1 1 4 4 1 4 1 1 1
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T/EOR01 A multiple3er or mu3 is a device that performs multiple3ing; it selects one of many analog or digital input signals and outputs that into a single line. In digital circuit design, the selector wires are of digital value. The number of selector pins is e;ual to #og5 -n/ <here n is the number of inputs. If A, 0, &, ! are input to a ( input multiple3er and 4 and 1 are select lines then the output is
V/D" #ODE library IEEE; use IEEE. T!"#$%I&"11'(.A##; use IEEE. T!"#$%I&"A)IT*.A##; use IEEE. T!"#$%I&"+, I%,E!.A##; entity mu3 is port-I.in bit"vector-6 downto 4/;&4,&1.in bit;f.out bit/; end mu3; architecture 0ehavioral of mu3 is begin f12--,$T &4/A,!-,$T &1/A,! I-4//$)-&4 A,!-,$T &1/A,! I-1//$)--,$T &4/A,! &1 A,! I-5//$)-&4 A,! &1 A,! I-6// after 14 ns; end 0ehavioral TR$T/ TA2"E1 &1 4 4 1 1 &4 4 1 4 1 = I4 I1 I5 I6
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T/EOR01 A demultiple3er -!>+?/ is a device which essentially performs the opposite operation to the >+?. That is, it functions as an electronic switch to route an incoming data signal to one of several outputs.
V/D" #ode entity demultiple3er is @ort - input . in std"logic"vector-4 downto 4/; s4 . in std"logic"vector-4 downto 4/; s1 . in std"logic"vector-4 downto 4/; s5 . in std"logic"vector-4 downto 4/; o4 . out std"logic"vector-4 downto 4/; o1 . out std"logic"vector-4 downto 4/;
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o5 . out std"logic"vector-4 downto 4/; o6 . out std"logic"vector-4 downto 4/; o( . out std"logic"vector-4 downto 4/; o7 . out std"logic"vector-4 downto 4/; o' . out std"logic"vector-4 downto 4/; o8 . out std"logic"vector-4 downto 4//; end demultiple3er; architecture 0ehavioral of demultiple3er is begin o4 12 -not s4 and not s1 and not s5 and input/; o1 12 - s4 and not s1 and not s5 and input/; o5 12 - not s4 and s1 and not s5 and input/; o6 12 - s4 and s1 and not s5 and input/; o( 12 -not s4 and not s1 and s5 and input/; o7 12 - s4 and not s1 and s5 and input/; o' 12 -not s4 and s1 and s5 and input/; o8 12 - s4 and s1 and s5 and input/; end 0ehavioral; TR$T/ TA2"E 1 A5 4 4 4 4 1 1 1 1 A1 4 4 1 1 4 4 1 1 A4 4 1 4 1 4 1 4 1 $+T !4 !1 !5 !6 !( !7 !' !8
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V/D" #ode library IEEE; use IEEE. T!"#$%I&"11'(.A##; use IEEE. T!"#$%I&"A)IT*.A##; use IEEE. T!"#$%I&"+, I%,E!.A##; entity FCflipflop is port - ,, ),, A,B, &#B.in bit; D. inout bit; D,. out bit.2G1G/; end FCflipflop; architecture 0ehavioral of FCflipflop is - 1: -
begin process - ,, ),, &#B/ begin if ),2G4G then D12G4G after 14 ns; elsif ,2G4G then D12G1G after 14 ns; elsif &#B2G4G and &#BGevent then D12 -A and not D/ or -not B and D/ after 14 ns; end if; D,12 not D; end process; end 0ehavioral; TR$T/ TA2"E 1 A 4 4 1 1 B 4 1 4 1 D ne3t Dprev 4 1 DHprev &omment hold state reset set toggle
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V/D" code1 #ibrary IEEE; use IEEE. T!"#$%I&"11'(.A##; use IEEE. T!"#$%I&"A)IT*.A##; use IEEE. T!"#$%I&"+, I%,E!.A##; entity tflip is port -T, &#B.in bit; D. inout bit; D,. out bit/; end tflip; architecture 0ehavioral of tflip is begin process -&#B/ begin if &#B2G4G and &#BGevent then D12 -T and not D/ or -not T and D/ after 14 ns; - 51 -
end if; D,12 not D; end process; end 0ehavioral; TR$T/ TA2"E1 T 4 4 1 1 D 4 1 4 1 Dne3t 4 1 1 4 &omment *old state *old state Toggle Toggle
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V/D" #ode 1 library IEEE; use IEEE. T!"#$%I&"11'(.A##; use IEEE. T!"#$%I&"A)IT*.A##; use IEEE. T!"#$%I&"+, I%,E!.A##; ---- +ncomment the following library declaration if instantiating ---- any ?ilin3 primitives in this code. --library +,I I>; --use +,I I>.J&omponents.all; entity encoder is port-a,b,c,d . in bit; 3,y . out bit/; end encoder; architecture 0ehavioral of encoder is begin 3 12 c or d; y 12 d or b; end 0ehavioral;
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V/D" code1 library IEEE; use IEEE. T!"#$%I&"11'(.A##; use IEEE. T!"#$%I&"A)IT*.A##; use IEEE. T!"#$%I&"+, I%,E!.A##; entity decoder is port-s1,s5,s6.in bit;d1,d5,d6,d(,d7,d',d8,d9.out bit/; end decoder; architecture 0ehavioral of decoder is begin d1 12 s1 and s5 and s6; d5 12 s1 and s5 and -not s6/; d6 12 s1 and -not s5/ and s6; d( 12 s1 and -not s5/ and -not s6/; d7 12 -not s1/ and s5 and s6; d' 12 -not s1/ and s5 and -not s6/; d8 12 -not s1/ and -not s5/ and s6; d9 12 -not s1/ and -not s5/ and -not s6/; TR$T/ TA2"E1 !ecimal !igit 5 4 1 5 6 ( 7 ' 8 4 4 4 4 1 1 1 1 4 4 1 1 4 4 1 1 1 4 1 4 1 4 1 4 1 4 !4 1 4 4 4 4 4 4 4 !1 4 1 4 4 4 4 4 4 !5 4 4 1 4 4 4 4 4 $utputs !6 !( 4 4 4 4 4 4 1 4 4 1 4 4 4 4 4 4
!7 4 4 4 4 4 1 4 4
!' 4 4 4 4 4 4 1 4
!8 4 4 4 4 4 4 4 1
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