Project Report

Design of ADC/DAC card and Interfacing With

8085 Microprocessor
Submitted By:
Pulkit Jain
Prateek Bhansali
Rocky Gupta

Abstract: In this project we attempt to design a simple ADC/DAC card which can be
easily interfaced with 8085 microprocessor kit for Data Acquisition(DAQ) purposes. We
extend our work by designing a PCB.

Keywords:
analog-to-digital, ADC, digital-to-analog, DAC,DATA ACQUISITION,8085

APPLICATION:
Commerical ADC/DAC cards can cost hundreds of dollars, not viable for teaching
purposes.This ADC/DAC card, which is much cheaper can be used for various purposes
such as to obtain the characteristics of various devices like BJT, diode, MOSFET,
inverter .It can be used with various kinds of transducers and sensors in undergraduate
laboratories as a teaching aid

INTRODUCTION:

Interfacing of ADC7574 with microprocessor

We used AD7574 which is a successive approximation 8-bit ADC. Since ADC does not
have the START-CONV pin so by doing a dummy write generating a CS bar, but
keeping RD bar high starts the conversion. The conversion time with R=184K and
C=100pf,the conversion time is 20 microsec We provide sufficient delay between
CS bar and RD bar to allow conversion before reading.
Vref= -10V

Since it is an 8-bit ADC so 1 LSB=10/256=39.1mv.

We decoded the I/O address 8XH with the help of address bit A7,for generating CS
bar.During the OUT instruction cycle the logic ensures that when IO/Mbar is high and
RD bar becomes low with A7 high, RD bar of ADC becomes low and data read is
performed in the T3 cycle of OUT instruction.

ASSEMBLY LANGUAGE`
LXI H,8800H
LOOP:OUT 80H
LXI B,8900H
LXI B,8900H
LXI B,8900H
LXI B,8900H
LXI B,8900H
LXI B,8900H
MOV M,A
INR L
JNZ LOOP
RST 1

MNEMONICS
21 00 88
D3 80
01 00 89
01 00 89
01 00 89
01 00 89
01 00 89
01 00 89
77
2C
C2 03 89
CF

INTERFACING OF DAC0800 WITH MICROPROCESSOR

We used DAC 0800 which is not microprocessor compatible so it was interfaced using
latch 74LS373.The latch enable(LE) is enabled at I/O address 8XH by the shown
decoding arrangement ,with I0Wbar low and A7 high in the T3 cycle of the IN
instruction and the digital word is made available to DAC for conversion.

ASSEMBLY LANGUAGE

MVI A,80H
DTOA : OUT 80H
MVI B,06H
MVI B,06H
MVI B,06H
MVI B,06H
INR A
JMP DTOA

MNEMONICS
3E
D3 80
06 06
06 06
06 06
06 06
3C
C3 02 88

To increase the versatility of ADC/DAC card, two ADC and two DAC were implemented
on four different I/O ports with the help of 8255A programmable peripheral interface
available on the kit.
The basic idea is to give input voltage to any DUT (Device Under Test ) through two
DAC ‘s connected to 8085 Microprocessor Kit by programmable peripheral device 8255
and sample the output of DUT as the input of ADC which is further connected to 8085
Microprocessor Kit.

For ADC 1 and ADC 2 :-

Connector Used - J2
Port used for ADC 1 - 40H (Port A)
Port used for ADC 2 - 41H (Port B)

For DAC 1 and DAC 2 :-

Connector Used - J1
Port used for DAC 1 - 00H (Port A)
Port used for DAC 2 - 01H (Port B)

APPLICATIONS
TESTING OF BJT CHARACTERSTICS:
MVI E,00 1E 00 E
00
LP1:LXI H,8800 21 00 88 H
8800
MVI D,00 16 00 D
00
MOV A,E 7B A
E
ACI 01H CE 01 A
A+1
MVI A,80 3E 80 Control Word Assigned
OUT 03H 43 03
MOV E,A 5F E
A
MVI A,E 7B A
E
OUT 01H D3 01 PORT 01
A
LP:MOV A,D 7A A
D
OUT 00H D3 00 PORT 00H
A
MVI B,01 06 01 DELAY
MVI B,01 06 01 DELAY
MVI B,01 06 01 DELAY
MVI A,92H 3E 92 A
92H ADC ‘S HAVE PORT A and B AS
OUT 43H D3 43 INPUT
PORT43
A
MVI A,0F 3E 0F A
OF
OUT 43H D3 43 DISABLE RD bar FOR PORT A
MVI A,0D 3E 0D
OUT 43H D3 43 DISABLE RD bar FOR PORT B
MVI A,08 3E 08
OUT 43H D3 43 ENABLE CS bar FOR PORT A
MVI A,09 3E 09
OUT 43H D3 43 DISABLE CS bar FOR PORT A
MVI A,0A 3E 0A
OUT 43H D3 43 ENABLE CS bar FOR PORT B
MVI A,0B 3E 0B
OUT 43H D3 43 DISABLE CS bar FOR PORT B
LXI B,8900H 01 00 89 DELAY
LXI B,8900H 01 00 89 DELAY
LXI B,8900H 01 00 89 DELAY
DCR H 25 H
87H shift the MEMORY Pointer TO 87XX
MVI A,0E 3E 0E
OUT 43H D3 43 ENABLE RD bar FOR PORT A
IN 40H DB 40 READ FROM PORT A
MOV M,A 77 87XX
A
MVI A,OF 3E 0F
OUT 43H D3 43 DISABLE RD bar FOR PORT A
INR H 24 H
88H
MVI A,0C 3E 0C
OUT 43H D3 43 ENABLE RD bar FOR PORT B
IN 41H DB 41 READ FROM PORT B
MOV M,A 77 88XX
A
MOV A,0D 3E 0D
OUT 43H D3 43 DISABLE RD bar FOR PORT B
INR L 2C L
L+1
JZ LP1 CA LP1 JUMP ON ZERO
INR D 14 D
D+1
JMP LP C3 LP JUMP TO LOOP

Testing of Inverter Characteristics:

INVERTER PLOT USING BC147

The Analog Input given to the circuit was a ramp varying linearly from 0-10 Volts . The
ramp was generated using DAC and analog output was sampled using ADC to
Microprocessor Kit.

Output Characteristics on Oscilloscope

INVERTER PLOT USING IC 7404