from Proc. IEEE Southeast Symp. on System Theory, pp.

216-221, 2011

Built-In Self-Test for Multipliers in Altera Cyclone II Field Programmable Gate Arrays
Michael A. Lusco, Justin L. Dailey and Charles E. Stroud
Dept. of Electrical and Computer Engineering Auburn University, Alabama, USA
AbstractThis paper describes a Built-In Self-Test (BIST) approach designed to verify the integrity of the embedded multiplier cores in Altera Cyclone II Field Programmable Gate Arrays (FPGAs). This approach uses an architecture independent test algorithm implemented with parameterized VHDL to support all FPGAs in the Cyclone II family. The BIST is capable of detecting faults within all of the multipliers modes of operation in three downloads and can identify the location of faulty multiplier(s). 1

I. INTRODUCTION Continuous increases in complexity of Field Programmable Gate Arrays (FPGAs) present an increase in the difficulty of testing these devices and their application systems. Implementing a Built-In Self-Test (BIST) approach in an FPGA takes advantage of the configurable nature of these devices to obtain an efficient and economical testing method by creating testing components within the FPGA itself [1]. Since FPGAs are fully erasable and reprogrammable the device does not suffer any area overhead or delay penalties after the test has been executed and the intended system application function has been downloaded. However, as a result of their programmability, the FPGA components must be tested in multiple configurations and the number of configurations dominates the total testing time as each test configuration must be downloaded to the device to complete the test [2]. In this paper, we discuss the development of BIST configurations to test the 2s complement multipliers in Altera Cyclone II FPGAs in order to verify their integrity for system operation. We have determined that they can be completely tested by downloading three BIST configurations. Running the BIST procedure on these two configurations allows us to detect all of the detectable faults that may occur within the multipliers. Implementation of these BIST configurations is done using a VHDL model [2]. The VHDL model is parameterized so that the number and configuration mode of the multipliers under test are easily specified by the user to test any device within the Cyclone II FPGA family via minor generic edits and subsequent synthesis of the VHDL model [2]. This high-level approach using VHDL allows us to avoid dealing with many low-level details of the design when applying the test to multiple multipliers as well as multiple devices [2]. However, by using VHDL we will not be able to match the speed of a custom tailored low-level design (one that
1 This work was supported in part by the National Science Foundation Grant CNS-0708962.

is specific to a particular device and less portable), nor the level of control over component placement and routing as will be discussed in more detail in this paper. We begin with an overview of the test algorithms and the basic BIST architecture is presented in Section II before we discuss specifics about the BIST implementation in Section III. The test procedure is discussed in Section IV and in Section V we discuss experimental results from actual implementations in all FPGAs in the Cyclone II family. Finally, a summary and conclusions are given in Section VI. II. BACKGROUND The BIST approach consists of three main components: the test pattern generators (TPGs), circuits under test (CUT), and the output response analyzers (ORAs). This test architecture is based on a testing approach initially proposed in [3]. The TPGs supply a set of test vectors to the inputs of the multipliers under test. These test patterns are algorithmic test patterns specifically for multipliers which will be discussed later. A pair of test pattern generators is routed to alternating multipliers which are arranged in columns on the device. The multipliers which are being tested are identically configured and will produce the exact same output response when stimulated by the TPGs if they are in fact fault free [2]. The resulting output from each multiplier is monitored by a pair of ORAs implementing a comparison-based test. The ORAs compare corresponding outputs from two different multipliers to monitor for any mismatch resulting from a fault. The ORA comparison is done in a circular manner as shown in Figure 1 [2]. Each output from each multiplier is routed to a pair of ORAs which performs a comparison of the routed output to the equivalent output routed from a different multiplier [2]. This method is used in order to prevent fault escape due to equivalent faults in adjacent multipliers going undetected [2]. If a mismatch between any pair of outputs is detected a failure indication will be set.

Fig. 1 Circular Comparison BIST Architecture [2]

from Proc. IEEE Southeast Symp. on System Theory, pp. 216-221, 2011 The test algorithm, which is executed by the TPGs, is based on testing approaches originally proposed for Booth multipliers in [4] and for modified-Booth/Wallace-tree multipliers in [5] and [6]. A combination of these test algorithms was later shown in [7] to provide architecture independent testing of multipliers and was used to test embedded multiplier cores in Xilinx Virtex-4 and Virtex-5 FPGAs [8]. All of these approaches use an 8-bit binary up-counter to test any size multiplier and, as a result, provides cost efficient testing in terms of both area overhead and test time. The testing approach described in [7] provides high fault coverage (>99%) regardless of the multiplier architecture. This approach is especially useful for our application as we cannot be sure exactly which type of multiplier architecture is employed in the Altera Cyclone II devices. However, the Cyclone II handbook [9] does describe the IO necessary to instantiate and use the embedded multiplier cores as shown in Figure 2 and summarized in Table I. Each multiplier can be configured as two 9-bit multipliers or a single 18-bit multiplier. Also each input, each sign bit, and the output of the multiplier core can optionally include a pipeline register. These pipeline registers are controlled by several additional signals including a single clock, clock enable, and asynchronous clear. from one BIST configuration to the next and causing a longer test time. Using the VHDL-based BIST approach of [2][3] in conjunction with the architecture independent multiplier test algorithm discussed in [7], we will show that a parameterized VHDL-based approach can be used to efficiently and effectively test all multipliers in any Altera Cyclone II device, even though the underlying architecture is unknown. By using a high-level design language, our testing procedure is straightforward to implement and does not require any low-level customization when testing different devices. III. THE BIST MODEL Our parameterized VHDL model consists of four main entities: the TPGs, the ORA, the Test Controller, and the CUTs (in this case the multipliers). These entities are combined and used to test the multipliers on the FPGA by running the previously mentioned BIST algorithm. Our specific approach uses a circular comparison method which is shown in Figure 1. We use two TPGs to drive alternating multipliers under test and each multiplier output is connected to two ORAs. In this way we provide redundancy to prevent fault escape when testing, with the exception of a few highly unlikely cases [1]. We are assured that any fault within a TPG will be detected as long as an equivalent fault is not present within the other TPG. The circular comparison architecture also protects against equivalent faults in adjacent multipliers remaining undetected due to the comparison of each components output to two other multipliers [2]; only in the case of equivalent faults in all multipliers under test would a fault escape detection. A. The Test Pattern Generator
Fig. 2 Functional Model of Embedded Multipliers [6] TABLE I Inputs and Outputs of Embedded Multipliers [6] Port Type Descriptions Data A Input Port A (9-bits or 18 bits) Data B Input Port B (9-bits or 18 bits) SIGNA Input Sign bit for Port A SIGNB Input Sign bit for Port B ACLR Input Asynchronous Clear for registers CLOCK Input Clock for registers ENA Input Clock enable for registers Data Out Output Multiplier Output (18 bits or 36 bits)

The BIST approach described in [2] and [3] used VHDL to construct and interconnect the TPGs, CUTs, and ORAs while the BIST approach in [8] used a device-specific netlist format to also specify the placement of the TPGs, CUTs, and ORAs in the FPGA. The latter approach requires considerable expertise and development effort to contend with the device specific netlist format but in turn provides faster test time since partial reconfiguration can be used to change the test configurations of the CUTs while the TPGs, ORAs, and routing remain constant. The VHDL based BIST approach in [2] and [3] is easier to implement since VHDL is used but requires a full download of all BIST configurations since the placement and routing of the TPGs and ORAs cannot be constrained to remain constant

The TPG is responsible for generating the necessary test vectors to test the different multipliers in the Altera FPGA. We use three separate algorithms to test the multipliers applied over four test phases. Each algorithm consists of 256 algorithmically generated test vectors. For our purposes a 10bit counter is used as the basis for the TPG, where the eight least significant bits (LSBs) of the counter are used to generate the 256 test vectors, and the remaining two most significant bits (MSBs) are used to control the current test phase. This results in a total of 1024 test vectors applied over the four test phases in each BIST configuration. When the last test phase has completed the 10-bit counter reaches the maximum value and a done flag indicates the BIST sequence has completed. A summary of the four phases is given in Table II. The first three phases (00, 01, 10) are used to implement the 4x4, 3x5, and 5x3 versions of the multiplier algorithm as discussed in [7]. An 8-bit example of the 4x4 test algorithm is shown in Figure 3a. In the 4x4 algorithm, the four MSBs of the 8-bit counter are replicated and applied to one of the multipliers input ports (Input A) while the four LSBs of the counter are replicated and applied to the other input port (Input B). Figure 3b shows an 8-bit example using the 5x3 algorithm. The 5x3 algorithm uses the five MSBs from the 8-bit counter and applies them to Input A of the multiplier then applies the

from Proc. IEEE Southeast Symp. on System Theory, pp. 216-221, 2011 remaining three LSBs to Input B of the multiplier. The 3x5 algorithm is similar to the 5x3 except that the five MSBs are applied to Input B and the three LSBs are applied to Input A. In our application, both the 5-bit and 3-bit inputs are extended by repetition to fill the entire input width.
TABLE II TPG BIST Sequence Phase BIST Sequence 00 4x4 Algorithm 01 5x3 Algorithm 10 3x5 Algorithm 11 Tests ENA and ACLR

In order to obtain the required data at the multiplier output, which is the input to the output pipeline register, we apply the data illustrated in Figure 4 and obtained by the associate logic equations.
Port A 0xFF 0xFF 0xFF 0x01 0x10 0x00 x x x x x x x Port B 0xFF 0x01 0x10 0xFF 0xFF 0x00 = = = = = = = Output 0XFE01 0x00FF 0x7FE0 0x00FF 0x7FE0 0x0000

A8 = Q6 + Q7 A[7:1] = Q6 A0 = Q6 + Q7 Q5

B8 = Q5 + Q7 B[7:1] = Q5 B0 = Q5 + Q7 Q6

Fig. 4 TPG Data (w/ Logic Equations) Supplied to Pipeline Registers

(a) 4x4 Test Algorithm

(b) 5x3 Test Algorithm Fig. 3 Multiplier Test Algorithms

After running the 4x4, 3x5, and 5x3 algorithms, the last phase produces deterministic test patterns used to test the control inputs to the multiplier registers including the asynchronous clear (ACLR) and clock enable (ENA). These control bits generated from certain counter bits so that they are toggled periodically during the final test phase according to the following logic equations: ENA = (Q8 Q9 (Q2 Q4 + Q3 Q4)) ALCR = (Q8 Q9 (Q3 Q4 + Q2 Q4)) The input data to the registers must also be driven with deterministic test patterns. The Port A and Port B registers are easily controllable, leaving the output pipeline register requiring specific data to fully test the ENA and ALCR inputs.

B. The Output Response Analyzer The ORAs constantly compare outputs from two different multipliers for discrepancies caused by faults. The output of the ORA is an active-low pass bit, such that logic 1 is indicative of a faulty multiplier. As illustrated in Figure 5, each ORA takes the output from two multipliers (R1 and R2) and bit-wise exclusive-ORs (XORs) them together to determine if they are the same value. If any of the bits of R1 and R2 are not the same then a fault has occurred and the output of the particular XOR gate(s) will be logic 1. To detect this case in the VHDL model, the XOR outputs are compared to an all zeros vector in an active-low equal-to comparator (a logic 0 output indicates equality). The output of the comparator is now the active-low pass bit that will become the output of the ORA. The next step in the ORA is to latch any failures into a flipflop so that after the test is completed any observed failures can be retrieved. To do this, the output from the comparator is fed into an OR gate which also includes the feedback from the flipflop. This will cause a failure (logic 1) to feedback into the flip-flop and remain until the end of the test when it can be retrieved. The multiplexor in Figure 5 is used to form a shift-register from the ORA outputs. This allows the user to shift out the results from the BIST sequence and use the diagnostic procedure described in [2] to identify any faulty multiplier(s). The final component of the ORA circuitry is an overall pass/fail bit. This bit, shown in Figure 5, is the logical OR of all the ORA outputs. If any single ORA reports a failure then this bit will also show a failure, providing a quick method for determining if the embedded multipliers are fault-free without accessing the shift-register chain.

Fig. 5 ORA Architecture and Overall Pass/Fail Bit

from Proc. IEEE Southeast Symp. on System Theory, pp. 216-221, 2011 C. The Multipliers Each multiplier to be tested is instantiated separately via a VHDL generate statement using two Altera VHDL primitives, cycloneii_mac_mult and cycloneii_mac_out. The first primitive controls the main multiplier core including a number of configuration options and its input and output. The cycloneii_mac_out is also required and is used to connect the output of the cycloneii_mac_mult to the rest of the BIST logic. Both of these primitives have a number of generics which control the multiplier mode and the associated configuration bits. In addition to the input and output width (9 bits or 18 bits), the most significant control bits are those which control the pipeline registers on the input and output of the multiplier. Each input port, the output port, and each input sign bit can be separately pipelined to increase the maximum clock frequency of the multiplier. To instantiate these multipliers in VHDL without a pipeline register, the string none is passed to each of the generic parameters; however, to include a pipeline register the generic is set to the string 0. These values were determined by inspecting the Verilog definition of the primitives. In addition to these configuration generics, the primitives also require the I/O summarized in Table I. The number of multipliers instantiated varies by device and input width of the multipliers under test. Table III shows the number of multiplier cores in each device of the Cyclone II family. It is important to understand that the numbers in the table are not cumulative [9]. For example, the EP2C5 can either have up to 13 18x18 multipliers or 26 9x9 multipliers, not both at the same time. It can however, have a combination of both in which case an 18x18 multiplier counts as two 9x9 multipliers. However, we do not mix 9x9 and 18x18 multipliers in the same BIST configuration as it complicates the BIST development. Due to this restriction and the different pipeline configuration options, three BIST configurations are required to fully test the multipliers.
TABLE III Cyclone II Devices and Multipliers # Embedded # 9x9 # 18x18 Multipliers Multipliers Multipliers 13 26 13 18 36 18 18 36 18 26 52 26 35 70 35 86 172 86 150 300 150

For our test procedure three BIST configurations are required to fully test the multipliers (as determined by fault simulations discussed in the next section). These three BIST configurations are summarized in Table IV. To achieve these configurations on an EP2C35 device, for example, we first set BISTConfig=Configuration1 to instantiate the 18x18 multiplier configuration and set MultiplierCores=35 so that we instantiate all the multipliers in the device (according to Table III). In addition, the Configuration1 constant causes the pipeline registers for Port A, Sign A, Port B, and Sign B to be disabled and the output register to be enabled. We then synthesize this model using the Quartus II software. For the second configuration we change BISTConfig=Configuration2 leaving MultiplierCores unchanged. Configuration2 will automatically select the 9x9 multiplier mode and will only enable the pipeline registers for Port A (including the sign bit register). In the third configuration we set BISTConfig=Configuration3 which will enable the pipeline register only on the Port B and the sign B register. We then synthesize these configurations. Now all three configurations are ready for download and execution in the actual device(s).
TABLE IV BIST Configurations Port A Port B Register Register Disabled Disabled Enabled Disabled Disabled Enabled

BIST Config 1 2 3

Output Register Enabled Disabled Disabled

Input Size N 18 bits 9 bits 9 bits

Device EP2C5 EP2C8 EP2C15 EP2C20 EP2C35 EP2C50 EP2C70

IV. THE TEST PROCEDURE All of the previously discussed aspects of the BIST approach are implemented in a single parameterized VHDL file with two generics: BISTConfig which defines the BIST configuration to be executed and MultiplierCores which specifies the number of 18x18 multipliers to be tested in the BIST configuration. From BISTConfig the input width is determined. This parameterized model relies heavily on the VHDL generate statement during synthesis to produce the final BIST model. The VHDL model consists of 514 non-commented lines of code.

After the BIST has completed, results can be retrieved by viewing the overall pass/fail bit and optionally accessing the contents of the ORA shift register. The BIST VHDL model includes a small serial peripheral interface (SPI) wrapper that makes the test results, done flag, pass/fail flag, and reset signal available over a four-wire SPI interface. This was done in an effort to help automate testing since Boundary Scan interface access to the core of the FPGA is not provided by our development board. While the VHDL model developed is parameterized and can be synthesized to any Cyclone II device (an advantage of using VHDL), some constraints are necessary for the top-level IO, such as the reset, clock, and shift signals, depending on the device and application. In addition, it is possible to constrain the multiplier placement to known locations using a constraints file. Unfortunately this process is tedious and device specific; however, it does offer some distinct advantages during diagnosis. Specifically if the physical locations of the multipliers are known, then it is easy to identify the faulty multiplier(s) based on the shift-register output and the algorithm described in [1]. If multiplier placement is not constrained, diagnosis is still possible; however, the user must use the chip planner from Quartus II to determine which ORA outputs corresponds to which multipliers. The VHDL model also allows for testing of a subset of a devices multipliers by setting MultiplierCores to a value less than the number of 18x18 multipliers available in the device. By testing fewer multipliers at once the maximum BIST clock speed may increase and/or power dissipation may reduce.

from Proc. IEEE Southeast Symp. on System Theory, pp. 216-221, 2011 Unfortunately this only offers limited advantages as test time is largely spent downloading to the device [1] when power usage is also highest [9]. However, this technique could be used in conjunction with a constraints file to verify that the multipliers to be used in a given application are fault-free. V. EXPERIMENTAL RESULTS To determine the fault coverage of our approach a gate-level fault simulation model of the Altera Cyclone II embedded multipliers was developed based on datasheet information in [9]. Figure 6 summarizes the architecture used for fault simulations of a 9x9 multiplier but does not show the sign bits and their pipeline registers.
9 9
ENA ACLR

INA CBA

18 18
ENA ACLR

CBO

INB

9
ENA ACLR

CBB

ENA CLK ACLR

Fig. 6 - Multiplier Fault Simulation Model

An alternative approach to testing is to use only two BIST configurations with the second configuration enabling both Port A and B pipeline registers (including both sign bit registers) as illustrated at the bottom of Table V. In this case, the overall test time is reduced by 1/3 at the expense of a slight reduction in fault coverage in the pipeline registers as indicated in the table. Since a single reset input drives the asynchronous resets to all input and output registers in the 99 multiplier this causes a number of faults to remain undetected in the input pipeline registers due to multiplication by 0. Since 0n=n0=00, it was impossible to detect a single fault that would prevent one of the register bits from being reset. We also downloaded and verified the BIST configurations in an actual FPGA and emulated physical faults by reconfiguring some of the multipliers to be different from the remaining multipliers under test. For our experimental setup we used an Altera DE2 development board which contains a Cyclone II EP2C35 device. As shown in Table II the EP2C35 has 35 embedded multiplier cores which can operate with up to 70 9x9 multipliers or up to 35 18x18 multipliers [9]. An image of the post-synthesis design can be seen in Figure 7. For verification purposes, we connected the overall pass/fail bit and the output of the shift register containing the ORA outputs to LEDs on the DE2 development board. In addition we connected various other control signals to the board push buttons including reset and shift functionality. All four BIST configurations summarized in Table V were downloaded and executed to verify proper operation.

Each 99 multiplier is programmed by three configuration bits (CBs) designated CBA, CBB, and CBO in Figure 6 (along with configuration bits CBSA and CBSB for the sign bit registers for ports A and B). These configuration memory bits allow selection of pipeline registers at the input and output of the multiplier such that there can be zero, one, or two pipeline registers configured for each multiplier. Based on the gatelevel fault model with the test patterns produced by the TPG as described in Section III, we determined that the 9x9 multiplier could be completely tested in the three BIST configurations as summarized in Table V which gives the cumulative number of stuck-at faults and associated fault coverage for each of the three configurations for the complete circuit, the multiplier and the pipeline registers. Note that there is one undetectable fault in the multiplier as verified by fault simulation with exhaustive test patterns such that the cumulative effective fault coverage is 100% for three BIST configurations.
Fig. 7 BIST Configuration on an EP2C35 TABLE V 99 Multiplier BIST Fault Simulation Total Circuit Multiplier 5,580 3,564 # Total Faults 1 1 # Undetectable Faults 4,670 3,563 Config #1 (83.98%) (100%) CBA=0, CBB=0, CBO=1 522 0 Config #2 (93.05%) (100%) CBA=1, CBB=0, CBO=0 387 0 Config #3 (100%) (100%) CBA=0, CBB=1, CBO=0 864 0 Alternate Config #2 (99.17%) (100%) CBA=1, CBB=1, CBO=0

Registers 2,016 0 1107 (54.91%) 522 (80.80%) 387 (100%) 864 (97.77%)

Quartus II had no difficulty performing the routing for all multipliers simultaneously regardless of the BIST configuration implemented and regardless of the FPGA in the Cyclone II family. In addition for our DE2 development board with Cyclone II EP2C35 device, synthesis time was approximately 17 seconds, while download time took approximately three seconds. Download time dominates the time taken to perform the test procedure compared to the time needed to execute the 1024 clock cycle BIST sequence. Once the model has been synthesized, it does not need to be re-

from Proc. IEEE Southeast Symp. on System Theory, pp. 216-221, 2011 synthesized if it is being reapplied to another device of the same model unless the desired pins for results retrieval change. In addition to the implementation on our development board, we synthesized the parameterized VHDL model for every Cyclone II FPGA. A summary of the BIST clock frequency, resource usage, and synthesis time for each device is shown in Table VI for the BIST configuration summarized in Table IV. The LAB count is a count of the logic array block resources used in each configuration, and the FF count is the number of dedicated logic flip-flops used. Configuration 1 has a much faster maximum clock speed due to the pipeline register on the output of the multiplier. Configurations 2 and 3 only have a single pipeline register active on either Port A or Port B of the multiplier which causes both of these configurations to have a significantly lower clock speed. Configuration 2A includes pipeline registers for both the Port A and Port B and while it uses the same number resources as Configurations 2 and 3, it realizes clock speeds closer to that of Configuration 1. While not shown in the table, a maximum BIST clock frequency of approximately 160 MHz for 18x18 bit multipliers and 195 MHz for 9x9 bit multipliers can be achieved for smaller devices when all pipeline registers are enabled. Regardless it is evident that the bigger devices exhibit a much slower top clock speed due to the increase in multipliers and increased routing. In these larger devices, clock speed could be increased significantly by only testing a constrained subset of the multipliers in the device.
TABLE VI Resource Usage and Maximum BIST Clock Frequency Configuration 1 Configurations 2, 3 & 2A Synthesis Time (sec) LABs FFs fclk (MHz) LABs FFs fclk (MHz) 157.08 459 48 106.84 10 504 35 12 631 40 149.28 592 58 102.32 144.45 805 74 99.45 15 834 48 12 834 48 148.26 805 74 103.43 133.16 1045 92 91.12 17 1062 57 125.56 2234 194 84.56 37 2354 108 130.89 3815 322 91.39 110 3826 172

the embedded multiplier cores in Altera Cyclone II FPGAs. The BIST configurations are automatically generated from a 514-line parameterized VHDL model for any device within the Cyclone II family. The approach achieves 100% gate-level single stuck-at fault coverage for all multipliers in any Cyclone II device using three BIST configurations. Alternatively, two BIST configurations can be used to achieve 99.17% fault coverage with a third less testing time. Each BIST configuration requires only 1024 clock cycles for execution once the BIST configuration has been downloaded into the FPGA, and it should be noted that this execution time is independent of the size of the FPGA as well as the number of multipliers being tested in the FPGA since all multipliers are tested concurrently. The test algorithms used to test the multipliers have been previously shown to provide architecture-independent testing of multipliers such that it is not necessary to know the specific implementation or architecture of the multiplier cores in the Cyclone II FPGAs. Failing BIST results can be used to diagnose the specific faulty multiplier(s) for fault-tolerant applications. ACKNOWLEDGEMENTS The authors wish to acknowledge the efforts of Navit Yahdav, Billjason Tomas and Eric Ingram of Auburn University Department of Electrical and Computer Engineering who contributed to this project as part of the National Science Foundation Research Experience for Undergraduates. REFERENCES
[1] L-T. Wang, C. Stroud and N. Touba, System-on-Chip Test Architectures, Morgan Kauffman, 2008. [2] C. Stroud and S. Garimella, "Built-In Self-Test and Diagnosis of Multiple Embedded Cores in SoCs," Proc International Conf. on Embedded Systems and Applications, pp. 130-136, 2005. [3] S. Garimella and C. Stroud, "A System for Automated Built-In Self-Test of Embedded Memory Cores in System-on-Chip," Proc. IEEE Southeastern Symp. on System Theory, pp. 50-54, 2005. [4] D. Gizopoulos, A. Paschalis, and Y. Zorian, "An Effective BIST Scheme for Booth Multipliers," Proc IEEE International Test Conf., pp. 824-833, 1995. [5] A. Paschalis, N. Kranitis, M. Psarakis, D. Gizopoulus, and Y. Zorian, "An Effective BIST Architecture for Fast Multiplier Cores," Proc. Design, Automation and Test in Europe Conf., pp. 117-121, 1999. [6] D. Bakalis, E. Kalligeros, D. Nikolos, H. Vergos, and G. Alexiou, "Low Power BIST for Wallace Tree-based Fast Multipliers," Proc. IEEE International Symp. on Quality of Electronic Design, p. 433, 2000. [7] M. Pulukuri, G. Starr, and C. Stroud, "On Built-In Self-Test for Multipliers," Proc. IEEE Southeast Regional Conf., pp. 25-28, 2010. [8] M. Pulukuri and C. Stroud, "Built-In Self-Test of Digital Signal Processors in Virtex-4 FPGAs," Proc. IEEE Southeastern Symp. on System Theory, pp. 34-38, 2009. [9] Altera Corp., "Cyclone II Device Handbook Volume 1," 2007 (available at www.altera.com).

Device EP2C5 EP2C8 EP2C15 EP2C20 EP2C35 EP2C50 EP2C70

An interesting problem was encountered during synthesis of the VHDL model using the Quartus II software. One of the two TPG instantiations was constantly removed from the design by the synthesis tools. This was occurring due to having two identical TPGs in the model. The synthesis tools recognized this and removed the duplicated circuitry during optimization. This problem is an artifact caused by the use of VHDL for the BIST model. This problem was overcome by using a separate reset signal for each TPG rather than sharing one between them. This modification forces the software to synthesize both TPG components instead of incorrectly optimizing one away. Ultimately the two resets can be tied back together during pin assignment or on the board to prevent any timing issues. VI. SUMMARY AND CONCLUSIONS We have have presented a circular comparison-based BIST approach for completely testing and verifying the integrity of