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Resistive switches have a higher source to drain impedance than regular switches and reduce the strength of signals when the signal passes through them. Resistive switches have the same syntax as regular switches.
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Verilog Code
Using the switch primitives discussed first, the verilog description of the circuit is shown below.
module my_nor(out, A, B); output out; input A, B; wire c; supply1 pwr; //pwr is connected to Vdd supply0 gnd; //gnd is connected to Vss(ground) pmos (c, pwr, B); pmos (out, c, A); nmos (out, gnd, A); nmos (out, gnd, B); endmodule
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Show result
A = 1'b0; B = 1'b0; #10 A = 1'b0; B = 1'b1; #10 A = 1'b1; B = 1'b0; #10 A = 1'b1; B = 1'b1; #10 A = 1'b0; B = 1'b0; end initial $monitor($time, " endmodule
Simulation Result
The output of the simulation is shown below.
Simulation result
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Simulation Waveform
According truth table, when input contains 1, then output is 0.
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Verilog Code
We are now ready to write the verilog description for a full adder. First, we need to design our own inverter my_not and my_xor by using switches. We can write the verilog module description for the CMOS inverter from the switch-level circuit diagram. module my_not(out,in); //Define output input output out; input in; //Define power and gound supply1 pwr; supply0 gnd; //Instantiate the CMOS switches pmos (out,pwr,in); nmos (out,gnd,in); endmodule We need to design our xor module by using switches, too. We can write the verilog module description for CMOS xor form the switch-level circuit diagram.
module my_xor(out,a,b); output out; input a,b; wire c; my_not nt(c,a); //Instantiate the CMOS switches cmos (out,b,c,a); pmos (out,a,b); nmos (out,c,b); endmodule
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Now, the 1-bit full adder can be defined using the CMOS switch and my_not inverter. The verilog description for a 1-bit full adder is shown below.
//Define a CMOS Adder module adder(sum,cout,a,b,cin); //Define input output and internal wire output sum,cout; input a,b,cin; wire my_xor my_not my_not my_not my_not my_not d,e,f,g n1(f,a,b); n2(d,f); n3(e,cin); n4(g,b); n5(sum,h); n6(cout,i);
//Define instantiate CMOS switches cmos (h,e,d,f); cmos (h,cin,f,d); cmos (i,g,d,f); cmos (i,e,f,d); endmodule
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//Define stimulus module module stimulus; //Define input output reg a,b,cin; wire sum,cout; adder n1(sum,cout,a,b,cin);
Show result
initial $monitor($time," sum=%b cout=%b a=%b b=%b cin=%b",sum,cout,a,b,cin); initial begin #5 a=1'b0; b=1'b0; cin=1'b0; #5 a=1'b0; b=1'b0; cin=1'b1; #5 a=1'b0; b=1'b1; cin=1'b0; #5 a=1'b0; b=1'b1; cin=1'b1; #5 a=1'b1; b=1'b0; cin=1'b0; #5 a=1'b1; b=1'b0; cin=1'b1; #5 a=1'b1; b=1'b1; cin=1'b0; #5 a=1'b1; b=1'b1; cin=1'b1; end endmodule
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Simulation Result
Simulation result is shown below.
Simulation Waveform
According to mathematical equation, we can get waveform is shown below.
sum = ( a
b c in ) b )
c o u t = ( a b ) + c in ( a
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Verilog Code
The 2 to 1 multiplexer passes the input I0 to output if S=0 and passes I1 to OUT if S =1. The switch level description for the 2 to 1 multiplexer is shown below.
Complement of s
module my_mux (out, s, i0, i1); output out; input s, i0, i1; wire sbar ; my_nor nt(sbar, s, s); cmos (out, i0, sbar, s); cmos (out, i1, s, sbar); endmodule
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my_mux m1(OUT, S, I0, I1); initial begin I0 = 1'b1; I1 = 1'b0; S = 1'b0; #5 S = 1'b1; #5 I0 = 1'b0; I1 = 1'b1; S = 1'b0; #5 S = 1'b1; end //check results initial $monitor($time," OUT= %b, S= %b I0= %b, I1= %b",OUT,S,I0,I1); endmodule
Second combination
Simulation Result
When S=0, then OUT=I0, otherwise, when S=1, then OUT= I1.
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Simulation waveform
The simulation is used to waveform check 2 to 1 multiplexer correctly.
Ouput I0
Output I1
Output I0
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Verilog Code
We are now ready to write the verilog description for the CMOS Flip-Flop. We will use my_not module previous example. module dff ( q, qbar, d, clk); output q, qbar; input d, clk; wire e; wire nclk; my_not nt(nclk, clk); cmos (e, d, clk, nclk); cmos (e, q, nclk, clk); my_not nt1(qbar, e); my_not nt2(q, qbar); endmodule
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Simulation Result
When clk =0, output keep previous value. Otherwise, clk=1 input value is loaded.
Simulation Waveform
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