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UNIT 10

OBJECTIVE

General Objective

To know and understand the concept of digital analysis

and Programmable Logic Design for Sequential Logic
Circuit.

Specific Objective

At the end of this unit, you should be able to :-

Draw and simulate sequential logic circuits using single or multiple

discrete IC logic gates.

Draw and simulate various applications of sequential logic circuits.

Generate Timing Diagram for digital input and digital output signals.

Know how to build a Programmable Logic Design File for a simple

sequential logic circuit.

Know how to program a device using Programmable Logic Design

(PLD) Basics.

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INPUT

10.0

INTRODUCTION TO SEQUENTIAL LOGIC CIRCUIT SIMULATION

Sequential logic circuits are circuits that make use of logic gates and logic
devices and have one very important characteristic which is the control
element.

Control element is also known as control input. The output of the circuit can
be set and controlled by making the control element active or triggered.

Among examples of sequential logic circuits are flip-flops, counters, registers,

Analog-Digital and Digital-Analog Converters.

The sequential circuit uses both digital signals and digital stimulus as the input
sources.

The simulation setup and analysis for sequential circuit is the same as for
combinational circuit with one extra setting of in the Digital Setup. The
timing diagram for both input and output are generated by Probe using the
same method also.

10.1

APPLICATIONS OF SEQUENTIAL LOGIC CIRCUITS

There are many applications of the sequential logic circuit but this section will
only discuss a few applications such as synchronous decade counter, analog-todigital converter and registers.
10.1.1

SYNCHRONOUS DECADE COUNTERS

A synchronous decade counter circuit increases the complexity of the
analysis by adding 7476 J-K flip-flops. 7476 is located in the 7400 library.
When placed on the schematic, each flip-flop is listed as the A flip-flop on
separate chips.

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By double clicking on the flip-flop graphic, the user can change the
Package Reference Designator and the Gate. The pin number on the
schematic will change automatically.

In figure 10.1, the flip-flops and the AND gates have been renamed to
make the pin numbers correspond with the gates actually used in the
circuit construction. Pspice will not allow floating input but floating
outputs are acceptable and generate signals that can be graphed by Probe.

Figure 10.1

For a counter circuit the stimulus generator is not used as a data input
device but rather as a clock used to signal the counter to advance the
count.

DSTIM1 is a clock generator that generates digital signal with 1us set per
clock cycle. This would generate a sequence of 0s and 1s for infinity.
This allows the counter to complete its 0 to 9 count and start again
counting up to 5. The loop in the stimulus could have been repeated 30
times, 100 times, or repeated forever using 1 as the number of
repetitions.

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The transient analysis has been set to 16us, any number over 16 cycles
would do.

The second stimulus, HI, is a stimulus that is set high and left there. Its
purpose is to provide +5 Volts to the presets, the clears, and the J and K
input for the first flip-flop.

When flip-flops are used in a circuit, the Digital Setup within the Analysis
Setup must be set.

Clicking the Digital Setup box opens a window that allows the setting of
the initial conditions for the output of the flip-flops. For this circuit, all
flip-flops should be set to 0 (low), at time zero.

Figure 10.2 shows the traces of the up-counting circuit. Trace a is the
clock signal and traces b, c, d and e show bit levels starting with the least
significant bit. The plot makes it clear that the counter properly counts to
nine and restarts at zero without the counting glitches associated with
asynchronous counters.

Figure 10.2

Figure 10.3 shows the logic level at the inverting outputs are also
available. They indicate that this counter also counts down from 15 to 6,
and then restarts at 15.

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Figure 10.3
10.1.2 REGISTER AS A RING COUNTER

A ring counter circuit as in figure 10.4 is a counter that does not count
numbers, instead it counts events. The number of events it counts depends
on the number of flip-flops used in the circuit. This means that 4 flip-flops
used would count 4 events and 5 flip-flops would count 5 events. The fig
10.4 is a 4-bit ring counter which would count 4 events.

The outputs of the counter labeled as Qa, Qb, Qc and Qd would produce 4
binary combinations 1000, 0100, 0010 and 0001. Each combination is a
representative of an event. The events are usually used to drive or act as
inputs to other circuits.

Fig 10.4

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In designing a ring counter a few important steps have to be observed.

Firstly, at the start of the simulation, the ring counter is set at logic 1 at the
output of the first flip-flop. All other flip-flops are set at logic 0. This is
done by wiring DSTIM2 to the clear and preset inputs of the flip-flops and
its attributes set as below.

Secondly, a feedback from the output of the last flip-flop to the input of
the first flip-flop has to be established to ensure the data of the last flipflop is circulated back to the first flip-flop thus producing repeatedly the
four combinations.

Each time the clock triggers, the bit 1 initially in the first flip-flop would
be shifted to the next flip-flop. Upon arriving at the last flip-flop, the bit 1
is then circulated back to the first flip-flop. In this case the clock is set for
1 kHz as shown below.

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For simulation purposes, the transient analysis is run for 5ms.

After simulation, Probe is used to plot the traces for the outputs: Qa, Qb,
Qc and Qd along with clock signal. This is done by highlighting the trace
names.

The output displayed by Probe as in Figure 10.5 should agree with the
truth table of the ring counter. It is verified that initially the output
produced is 1000. After the clock triggers the first time, the output now is
0100. The second time the clock triggers the output is 0010. The third
clock triggers and the counter produce 0001. As the clock triggers again,
the output repeat the initial condition which is 1000.

Figure 10.5

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ACTIVITY 10a

TEST YOUR COMPREHENSION BEFORE PROCEEDING TO THE NEXT

INPUT!

CHECK YOUR ANSWERS IN THE FEEDBACK SECTION ON THE NEXT

PAGE.

Do the following exercises.

1.

Design and simulate a 5-bit ring counter as shown below. The counter should
be initialized at the start of the simulation.

a) Use four separate ICs for JK flip-flops

b) Set the clock at 1kHz
c) Use the preset and clear inputs to set the initial state to 1000.
d) Plot the timing diagram for the clock and outputs of the circuit.

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2.

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Design and simulate an asynchronous decade down counter as shown below.

The counter should be initialized at the start of the simulation. The initial
state should be the maximum number for the counter.

a) Minimize the number of ICs for JK flip-flops.

b) Set the clock at 1kHz.
c) Plot the timing diagram for the clock and all the outputs of the circuit.
d) Verify that the numbers are counted in correct order.

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d
FEEDBACK 10a

Answers :
1b. Set up clock to 1 kHz.

1c. Set up clear.

1d. Output timing diagram.

2b -2d. Please work it out and refer to your lecturer for the answer.

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INPUT

10.4

PROGRAMMABLE LOGIC DESIGN (PLD) BASICS IN LOGIC DEVICE

PROGRAMMING
10.4.1 CONSTRUCTING A REGISTERED DESIGN FOR BASIC FLIPFLOPS

This section will demonstrate a very simple registered design; a design of

all basic flip-flop types as shown in figure 10.6. The design will be
conceptualized by reviewing briefly the behavior of the D-type flip-flop.
The results for T, JK and SR flip-flops will then be presented.

The devices used in the examples only have D-type flip-flops. Thus, the
other flip-flops will be emulated using D-type flip-flops.

Figure 10.6 Basic Flip-Flops

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10.4.2 BUILDING THE D-TYPE FLIP-FLOP EQUATIONS

A D-type flip-flop presents the input data at the output after being clocked.
Its basic transfer function can be expressed as:
DT : = D
where pins DT (D True) and D are used as shown in Figure 10.6.

Note the use of := here instead of =. This indicates that the output is
registered for this equation. The difference is illustrated in Figure 10.7.
(PLD design syntax may vary. Refer to the appropriate language reference
manual.)

Figure 10.7 Registered vs. Combinational Equations

The complement signal can be generated with the statement:

DC : = /D

As shown in fig 10.6, preset and clear functions are added to the flip-flops.
This can be done with two input pins, called PR and CLR. To add these
functions to the true flip-flop signal, /CLR is added to every product term
and add one product term consisting only of PR. Likewise, for the
complement functions, /PR is added to every product term, and add one
product term consisting only of CLR. With these changes, the equation
now looks like:

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DT : = D * /CLR
+ PR
DC : = /D * /PR
+ CLR

In this way, when clearing the flip-flops, the active-HIGH flip-flops have
no product terms true, and go low; the active-LOW flip-flops have the last
product term true, and will therefore go HIGH. The reverse will occur for
the preset function.

There is still one hole in this design: what happens if preset and clear are
active at the same time? As it is now, both outputs will go HIGH. This
makes no sense since one signal is supposed to be the inverse of the other.
To rectify this, we can give the clear function priority over the preset
function. This can be done by placing /CLR on every product term for the
true flip-flop signal. The results are shown as follows:
DT : = D * /CLR
+ PR * /CLR
DC : = /D * /PR
+ CLR
The same basic procedure can be applied to all of the other flip-flops. The
equations are shown in Figure 10.8.

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EQUATIONS
; emulating all flip-flops with D-type flip-flops
DT : = D * /CLR
+ PR * /CLR
DC : = /D * /PR
+ CLR
TT : = T * /TT * /CLR
+ /T * TT * /CLR
+ PR * /CLR
TC : = T * /TC * /PR
+ /T * TC * /PR
+ PR * /CLR
JKC : = J * /JKT * /CLR
+ K * /JKC * /CLR
+ CLR
SRT : = S * /CLR
+ /P * SRT * /CLR
+ PR * /CLR
SRC : = R * /PR
+ /S * SRC * /PR
+ CLR
Figure 10.8 Flip-Flop Equation Section

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10.4.3 BUILDING THE REMAINING EQUATIONS AND COMPLETING

THE DESIGN FILE

Notice that in some of the equations above, the output signal itself shows
up in the equations. This is the way in which feedback from the flip-flop
can be used to determine the next state of the flip-flop. An equivalent logic
drawing of the TT equation is shown in Figure 10.9.

Figure 10.9 Feedback in the Equation for TT

Instruction included with the software package has to be followed in order
to complete the design file.
10.4.4 SIMULATING THE FLIP-FLOPS

After processing the design and correcting any mistakes, the simulation is
executed. The design file is to be simulated in the same manner as the
basic gates design.

10.4.5 PROGRAMMING A DEVICE

After simulating the design, and verifying that it works, it is time to program
a device. There are several steps to programming, but the exact operation
of the programmer naturally depends on the type of programmer being
used. Refer to the programmer manual being used for the specifics.

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The first thing to do after turning the programmer on is to select the device
type. This tells the programmer what kind of programming data to expect.
The device type is usually selected either from a menu or by entering a
device code. The programmer manual will have the details.
Next, a JEDEC file must be downloaded. To transfer the JEDEC file from
the computer to your programmer, a connection is needed as shown in
Figure 10.10.

Figure 10.10 A Connector Must Be Provided Between

Computer and the Programmer
If the programmer can perform functional tests, and a test is wished to be
performed, download the JEDEC file containing the vectors; otherwise,
download the JEDEC file without vectors.
To download data, the programmer must first be set up to receive data. The
programmer manual will tell how to do this.
Communication must be set up between the computer and the programmer.
Whichever communication program is installed must be invoked. This is
used to transmit the JEDEC file to the programmer. Follow the
instructions for the program to accomplish the next steps.
Before actually sending the data, verify the correct communication protocol.
Check to make sure what protocol the programmer is expecting; then set
up the baud rate, data bits, stop bits, and parity, to match the protocol.

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Once the protocol has been set up the JEDEC file must be downloaded.
Enter the name of the JEDEC file to be used. The computer will then
announce that it is sending data, and tell when it is finished. Note that just
because it says it has finished sending data does not mean that the data
was received correctly.
Once the data has been received, the programmer is ready to program a
device. Place a device in the appropriate socket, and follow the
instructions for the programmer to program the device. This procedure
programs and verifies the connection in the device, and, if a JEDEC file
containing vectors was used, will perform a functional test.
The programmer will announce when the programming procedure has been
completed. Then take the device and plug it into an application.
Program the example created before and test it to verify that the device
perform as expected.

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ACTIVITY 10b

TEST YOUR COMPREHENSION BEFORE PROCEEDING TO THE NEXT

INPUT!

CHECK YOUR ANSWERS IN THE FEEDBACK SECTION ON THE NEXT

PAGE.

Do the following exercises.

1. You are to use the 5-bit ring counter circuit given in activity 10a, Q1.
a) Build a design file for the logic circuit.
b) Create a JEDEC file from the design file you have created in 1(a).
c) Download the JEDEC file and program into a specific PAL device.
d) Plug the device into an application or test the device to verify whether it is
working correctly as expected.

2. You are to use the asynchronous decade down counter circuit given in activity 10a,
Q2.
a) Build a design file for the logic circuit.
b) Create a JEDEC file from the design file you have created in 2(a).
c) Download the JEDEC file and program into a specific PAL device.
d) Plug the device into an application consisting of a seven segment display. Test the
device to see whether the seven segment will display all the 10 decimal digits
sequentially and in descending order.

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FEEDBACK 10b

Answer :

Please refer to tour lecturer for the answers.

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SELF-ASSESSMENT

You are approaching SUCCESS! Try to answer ALL questions in this self-assessment
section and check your answers in the feedback section in the next page.
If you encounter any problem please discuss with your lecturer. Try your best and
SUCCESS is on your way! Good-Luck!!!
QUESTION 10.1
Draw and simulate a switch-tail counter given below. All flip-flops must be cleared at the
start of simulation and minimize on the number of ICs used.

a)

Set the clock to generate 1 kHz waveform for 20 cycles.

b)

Set the transient analysis for 20ms.

c)

Plot the clock signal and the outputs Qa, Qb, Qc and Qd.

d)

Plot the outputs of the decoder, Y0-Y9.

e)

State the decimel numbers that are generated by the circuit.

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FEEDBACK

Have you tried to answer ???

If YES , please check your answers to see whether it is correct or not.
ANSWERS TO SELF-ASSESSMENT
1a.

1b.

1c.

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1d.

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