EE241

Types of Flip-Flops
Latch Pair (Master-Slave)
L1
Data D Q Clk Clk

Pulse-Triggered Latch
L2 L
Data Clk D Q Clk

D Q Clk

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Flip-Flop Delay
l

Sum of setup time and Clk-output delay is the only true measure of the performance with respect to the system speed T = TClk-Q + TLogic + Tsetup+ Tskew

D Q Clk

Logic

D Q N Clk

TClk-Q
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TLogic

TSetup
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EE241

Delay vs. Setup/Hold Times

350 300 Minimum Data-Output 250 Clk-Output [ps] 200 150 100 50 0 -200 -150 -100 -50 0 Data-Clk [ps]
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Setup

Hold

50

100

150

200

Master-Slave Latches
Positive setup times l Two clock phases:
l

distributed globally generated locally

Small penalty in delay for incorporating MUX l Some circuit tricks needed to reduce the overall delay
l
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EE241

Master-Slave Latches
Case 1: PowerPC 603 (Gerosa, JSSC 12/94)
Vdd Vdd

Clk
D

Clkb
Q

Clkb

Clk

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T-G Master-Slave Latch

Feedback added for static operation Unbuffered input
input capacitance depends on the phase of the clock over-shoot and under-shoot with long routes wirelength must be restricted at the input

Clock load is high Low power Small clk-output delay, but positive setup

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EE241

Master-Slave Latches
Vdd Vdd

Case 2: C2MOS
Ck
D

Ckb

Q Ckb Ck

Vdd Clk

Vdd

Vdd

Vdd

Ck Ckb

Vdd Ck

Vdd

Feedback added for static operation Locally generated clock Poor driving capability Robustness to clock slope
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Ck

Ckb

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Pulse-Triggered Latches
First stage is a pulse generator
generates a pulse (glitch) on a rising edge of the clock

Second stage is a latch

captures the pulse generated in the first stage

Pulse generation results in a negative setup time Frequently exhibit a soft edge property Note: power is always consumed in the pulse generator

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EE241

Pulse-Triggered Latches
Case 1: Hybrid Latch Flip-Flop, AMD K-6 Partovi, ISSCC96
Vdd
Q Q

D Clk

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HLFF Operation
1-0 and 0-1 transitions at the input with 0ps setup time

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EE241

Hybrid Latch Flip-Flop

Flip-flops features:
single phase clock edge triggered, on one clock edge

Latch features: Soft clock edge property

brief transparency, equal to 3 inverter delays negative setup time allows slack passing absorbs skew

Hold time is comparable to HLFF delay

minimum delay between flip-flops must be controlled

Fully static Possible to incorporate logic

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Soft Edge Property

Also known as cycle borrowing, or slack passing In latch based designs, if longest path datum reaches latch before its setup time, clock skew does not affect cycle time If longest path reaches latch close to setup time, clock skew is directly subtracted from cycle time Flip-flop presents a hard edge - no slack passing. HLFF is a compromise - has a controlled transparency period, that can absorb skew Price is paid in the hold time

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EE241

Hybrid Latch Flip-Flop

Skew absorption

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Partovi et al, ISSCC96

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Pulse-Triggered Latches
Case 2: AMD K-7

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Courtesy of IEEE Press, New York. 2000

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EE241

Pulse-Triggered Latches
Case 3: Semi-Dynamic Flip-Flop (SDFF), Sun UltraSparc III, Klass, VLSI Circuits98
Vdd Vdd

Q Q
D Clk

Pulse generator is dynamic, cross-coupled latch is added for robustness. Loses soft edge on rising transition Latch has one transistor less in stack - faster than HLFF, but 1-1 glitch exists Small penalty for adding logic
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Pulse-Triggered Latches
Case 3: 7474, Texas Instruments64

S
Clk

Q R

D
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EE241

7474
Karnaugh maps for signals S and R
SR Clk, D 00 01 D 11 10 S DR S x x 1 1 1 0 0 Clk 0
R DS S 10 x 0 1 1

R 00 x x 01 1 1 11 1 1 10 1 1 Clk
D Clk, D

SR 00 x x x 01 1 1 0

R 11 1 1 0 10 1 1 Clk 1 Clk

00 01 11

S = Clk R D S
S
Clk

R = Clk S D R
Q

Q R

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Pulse-Triggered Latches
Case 4: Sense-amplifier-based flip-flop, Matsui 1992. DEC Alpha 21264, StrongARM 110 First stage is a sense amplifier, precharged to high, when Clk = 0 After rising edge of the clock sense amplifier generates the pulse on S or R The pulse is captured in S-R latch Cross-coupled NAND has different propagation delays of rising and falling edges

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EE241

Sense Amplifier-Based Flip-Flop

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Courtesy of IEEE Press, New York. 2000

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Flip-Flop Performance Comparison

Test bench
Data
D Q

200fF

Total power consumed Clk Q internal power Clock 200fF data power 50fF clock power Measured for four cases no activity (0000 and 1111) Delay is (minimum D-Q) maximum activity (0101010..) average activity (random sequence) Clk-Q + setup time

Stojanovic, Oklobdzija JSSC 4/99

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EE241

Flip-Flop Performance Comparison

Delay vs. power comparison of different flip-flops Flip-flops are optimized for speed with output transistor sizes limited to 7.5m/4.3 m Total transistor gate width is indicated
70

Total power [uW]

60 50 40 30 20 10 0 100

HLFF 54m mSAFF 64m SDFF 49 m

TG M-S 52m Original SAFF 60m

2

C MOS 80m
300 350 400 450 500

150

200

250

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Delay [ps]

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Energy Consumption
Energy Breakup in TG-MS (PowerPC603)

Always consume
q

8%

ECLK = E0-0 = E1-1 Eint = E1-0 E0-0 Eext = E0-1 E1-0

Clocked Nodes

When Q : 1-0 or 0-1

q

6fJ

Only when Q : 0-1

q

External Load 54% 42fJ

Internal Nodes 29fJ

Non-inverting Flops:
38%

Eavg = ECLK + Eext + (1- ) Eint

Inverting Flops:
q

Eavg = ECLK + (1-) Eext + Eint

( - probability of D : 0-1)

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EE241

Energy Dissipation
Comparison of Master Slave and Pulse-Triggered Flip-Flops
250 200

0--0 0--1 1--0 1--1

198 183

Energy [fJ]

150 114 114 101 102 100 64 50 31 23 14 0 14 23 42 30 36 85 59 103 94

57

TG FF

C2MOS

HLFF

SDFF

SAFF

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Resized for Energy/Delay

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Local Clock Gating

2

CKI
0.85

Q
0.85 0.5 0.85 1.2

D
0.5

DI

0.5

CKIB

CKIB

0.5

0.5

Data-Transition Look-Ahead Pulse Generator

0.85

0.5

0.85

0.5

XNOR

CKIB
0.85

Clock on demand Flip-flop

CP
0.5

CKI

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