Levels of Abstraction

1 System level
Processors, Memories, Peripherals
Word files, Records, Programs
HDL natural language
1 RTL level
Registers, ALU, CCUs
Bytes, words, double words
Block diagrams, state diagrams
1 Logic level
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1 Logic level
Gates, flip-flops
1,0, X: strong, weak, Z
Logic diagrams, boolean equations
1 Circuit level
R, C, L, Diodes, Transistors
Voltage, current, temperature
Schematic diagrams, circuit equations
1 Layout level
NPN, PNP transitors, CMOS
Values: voltage, current, temperature, fields
Device modes, incterconnects
VLSI Developments
LOGIC
DESIGN
CIRCUIT
DESIGN
LAYOUT
DESIGN
MASK FABRICATION
TRANSISTOR
DEVELOPMENT
DEVELOPMENT OF
ONSTITUENT
PROCESS TECH.
DEVICE
DEVELOPMENT
TEST &
ASSY.
RELIABILITY
EQIPMENT & PROCESS SIMULATORS
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PHYSICO-CHEMICAL MODEL
NUMERICAL CALCULATION AND CALCULATION ALGORITHMS
CIRCUIT SIMULATOR, LAYOUT & VERIFICATION TOOLS
LOGIC SIMULATOR
DEVICE SIMULATOR
Synthesis
logiccell
VDD
input
1 Synthesis is the stage in design flow which is concerned with translating
VHDL code into gates - and that's putting it very simply
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Algorithm Level
Synthesis
RTL Level
Synthesis
Circuit Level
Synthesis
Anexampleofstandardcelllayout.
VSS
wiring
Physical Level
Synthesis
System Functions often split b/w CPU & ASIC
1 Most economical means of implementing logic functions is to use uP
1 When uP is too slow or too busy to handle some fast I/O, an ASIC can
be used to implement high-speed concurrent operations
uP
Slow inputs
Slow outputs
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ASIC
Slow inputs
Fast inputs
Fast outputs
Control &
Feedback
System-on-Chip (SoC) Appraoch
1 SoC is the design approach of integrating the components of an
electronic system into a single chip
1 A single chip can perform the functions of an entire electronic system,
such as MPEG decoder, network router, or cellular phone
1 SoC designs often consume less power, less design/package cost &
more reliable than multichip systems that they are designed to replace
1 The key to SoC approach is integration. By integrating increasingly
more preassembled and verified blocks, which have dedicated more preassembled and verified blocks, which have dedicated
functions, into one chip, a sophisticated system is created in a timely
and economical fashion
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Why SoC?
1 System on Chip (SoC) bridges the gap between Hardware & Software &
their implementation
1 In SoC design, chips are assembled at IP block level (design reusable)
& IP interfaces rather than gate level
SoC Consists of
1 Current systems are complex & heterogeneous
contains different types of components
1 Half of Chip can be filled with :
1 Low-power processors
1 Interconnected by field-programmable buses
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1Analog
1RF
1Power
1MEMs
1IP
1Digital
Control
P
DSP
Interfaces
1Memory
SRAM
DRAM
FLASH
1 Interconnected by field-programmable buses
1 Embedded in 20Mbytes of distributed DRAM &
flash memory
1 Another Half: ASIC
1 Application Specific Integrated Circuit (ASIC)
1 Computational power will not result from multi-GHz
clocking but from parallelism, with below 200 MHz
This will simplify the design for correct
timing, testability, & signal integrity
SoC Flow
Generic
HW IP blocks
Generic
SW IP blocks
Specify
SoC
Architecture
platform
Partition
HW/SW
Integrate
Application
Specific
Electronic system level design
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Operating
system
Application
Specific
HW IPs
Integrate
Application
Specific IP block
into Arch. platform
Specific
SW IP Modules Integrate SW
Specific IP Modules
Functional
simulation
Low level
SW simulation HW design
flow
SW design
flow
HW & SW (low level)
FPGA platform
HW/SW
Co-simulation
SoC Flow
HW & SW (low level)
FPGA platform
Physical
design
Application
SW development
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Prototype
IC fabrication
HW/SW Verification on
application prototype
or development board
SW test
Prototype
IC fabrication
Ship ICs & SW to Clients
SoC Design Flow
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SoC Example
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SoC Examples
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Intellectual Property (IP) Core
Criteria
Classification
Hard Core Soft Core
Structure Pre-defined organization
Behavioural source code,
technology independent
1 In electronic design, intellectual property core (IP) core, or IP block is
reusable unit of logic, cell, or chip layout design that is IP of one party
1 IP cores may be licensed to another party or can be owned & used by
a single party alone
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technology independent
Modelling Modeled as a library component
Synthesizable with several
technologies
Flexibility Cannot be modified by designer Can be modified by the designer
Timing closure Timing ensured Timing not guaranteed
IP protection
Strong. Usually corresponds to a
layout
Weak. Source code
Example
FPGA Bitstream, GDSII file for IC
layout
VHDL, Verilog
Need for redesign
1 Many of electronic products have life more than 10- years, and
consequently have to be redesigned several times in order to exploit
new technology
1 It is common for electronics to modified and new functions to be added
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Increasing device & complexity/DSM
1 Exponential increase in device complexity
Increasing with Moore's law (or faster)!
1 More complex system contexts
System contexts in which devices are deployed (e.g.
cellular radio) are increasing in complexity
1 Require exponential increases in design productivity
We have exponentially more transistors!
C
o
m
p
l
e
x
i
t
y
Increasing device
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We have exponentially more transistors!
Design of each transistor is getting more difficult!
Deep submicron effects
1 Smaller geometries are causing a wide variety of
effects that we have largely ignored in the past:
Cross-coupled capacitances
Signal integrity
Resistance
Inductance
D
S
M

E
f
f
e
c
t
s
Heterogeneity on chip/Market Pressure
1 Greater diversity of on-chip elements
Processors
Software
Memory
Analog
More transistors doing different things!
Heterogeneity
Diversity
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More transistors doing different things!
Stronger market pressure
1 Decreasing design window
1 Less tolerance for design revisions
Time-to-market
Exponentially more complex, greater design risk,
greater variety, and a smaller design window!
A Quadruple-whammy
C
o
m
p
l
e
x
i
t
y
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Time-to-market
D
S
M

E
f
f
e
c
t
s
Heterogeneity
Real Time Embedded Systems
1 Electronic system containing CPU without an operating system visible
to end-user
1 It interacts with peripheral devices within fixed time constraints
1 Minimum of resources are employed to perform required tasks
1 In addition to functionality and cost, other constraints include power
management, fault tolerance, quality of services, security etc.
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CAD/EDA Tools
1 Computer Aided Design (CAD)/Electronic Design Automation (EDA)
1 Circuit Analysis Tools
Predict circuit behavior at all process corners from high to low level
1 Symbolic Layout Tools
To ease task of physical design; mask verification to ensure
manufacturability
Tools to do tedious, repetitive work such as routing, tiling a mosaic of
building-block cells, or verifying that layout and schematic match
1
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1 Problems:
Designing highly complex VLSI circuits (100K to xM FETs)
Classical, iterative procedures are unsuitable
Precise transistor models are necessary for reliable predictions 1 data
inflation
1 Solutions:
New design methodologies
Powerful design tools
High level design languages
Silicon compiler would be useful
Evolution of EDA industry
Results
(design productivity)
Synthesis Cadence, Synopsys
Whats next?
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Effort
(EDA tool
effort)
McKinsey S-Curve
Transistor entry Calma, Computervision, Magic
Schematic entry Daisy, Mentor, Valid
Why Low Power ?
1 Lifetime of a Device
Handhelds
Ubiquitous
1 Reduce Cost
Cooling
Packaging
1 High density on Chip-Portable
systems
Smaller Batteries
Reduce Weight
Exploding Market of Portable Devices,
SoC faces sever problem of Power Restrictions
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Servers
Ubiquitous
Computing
Desktops
Portables
Reduce Weight
Reduce Volume
1 Reliability
Thermal problems
Scaling problems
Electro-migration
1 Environmental Concerns
Office equipment accounted for
5% of total US commercial
Why Low Power?
1 Portable systems
Long battery life
Light weight
Small form factor
1 IC priority list
Power dissipation
1 Technology direction reduced voltage/power designs based on high
performance IC technology, high integration to minimize size, cost,
power, speed
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Power dissipation
Cost
Performance
1 Expected battery lifetime increase over next 10 years: 30-40%
1 IC densities/Operating frequency will be double every generation
Why Low Power?
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80% Ptotal
Sources of Power Dissipation
P
dyn
= C
L
V
DD
V
sw
f
021
120
VDD
In Out
CMOS
1 Short-Circuit Power
Short circuit path between
supply rails during
1 Dynamic Switching Power
Charging & Discharging
capacitors
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10-20% Ptotal
1-10% Ptotal
Source: Design Aids for Low Power, Jan M. Rabaey
P
sc
= V
DD
I
sc
P
stat
= VDD IIeak
1 Leakage Power
Leaking diodes &
transistors
C
L
I
SC
12345645
supply rails during
switching
Principles of Low Power Design
1 Reduce supply voltage
Quadratic effect dramatic
savings
Negative effect on performance
1 Reduce capacitance
Smaller devices, new
technologies
1 Design Space Exploration
Calculate bound under different constraints
Trade-off between Power, Area, Speed
2
Speed
Power
Quality
Noise
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technologies
Usually not design(er) parameter
1 Reduce switching frequency
Switching activity
Clock rate
1 Reduce glitches
1 Reduce short circuit currents
1 Reduce leakage currents
Clocks
I/O Drivers
Caches
Execution
Units
Control
40%
20%
15%
15% 10%
mProcessor
Source: Dr. Li-Rong Zheng (KTH)
2
CV P = V I P =
Area
Yield
Power Down Techniques
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Future of VLSI
Emergence of GSI (Giga-Scale Integration)
and TSI (Tera-Scale Intgration)
Use of Carbon Nano-Tubes
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Use of Carbon Nano-Tubes
ULSI (Ultra Large Scale Integration) & Wafer
Scale Integration and more developed versions
of SoC (System on Chip)