Вы находитесь на странице: 1из 8

1584

IEEE TRANSACTIONS ON POWER DELIVERY, VOL. 28, NO. 3, JULY 2013

A Low-Cost Power-Quality Meter With Series Arc-Fault Detection Capability for Smart Grid
Kostyantyn Koziy, Bei Gou, Member, IEEE, and Joel Aslakson
AbstractThis paper presents a low-cost digital single-phase power-quality measurement device for consumer use with a wide range of features, including series arc-fault detection, load trip on failure, and phase/neutral line wiring mix up indication. A wavelet multiresolution analysis technique was utilized for the voltage transient event detection and the current drop pattern recognition, specically to arc fault. The last feature also involved the use of adaptive thresholding, peak detection, and repetition frequency calculation. A computationally efcient and accurate Goertzel lter was used for total harmonic distortion calculation. In addition, this meter can measure phase fundamental frequency (using the zero-crossing technique), rms values, and power. MATLAB and MathCAD packages were used to build and simulate arc-fault model and phase voltage distortion, to design and test part of the developed algorithms, which were further implemented in Embedded C and Assembler programming languages. A prototype circuit board with the required sensors and relay, analog isolation, indication, user controls, communication link, and a low-cost microchip microcontroller (MCU) dsPIC33 was designed and built to validate implemented algorithms and conduct experiments. Index TermsArc fault, Goertzel algorithm, microcontroller, power quality (PQ), smart meter, total harmonic distortion (THD), wavelet.

Fig. 1. Series arc-fault condition.

I. INTRODUCTION LECTRICITY is extremely important for commercial and residential use. With the advent of smart grid, the concern about power quality (PQ) is growing due to the appearance of new components, which are sensitive to various powersupply disturbances. Examples include distributed generators, wide-area controllers, etc. Low PQ entails the loss of 10 billion Euros in Europe and $U.S.24 billion every year, and may cause unexpected power supply and equipment failures, electronic communication interference, possible human health problems, and reduced personnel efciency (e.g., due to the icker effect, image distortion on displays). Major defect types of electrical energy supply are briey listed here: 1) phase voltage harmonic distortions, which occur due to the nonlinear loads supplying unexpected currents;
Manuscript received July 27, 2012; revised December 06, 2012; accepted February 23, 2013. Date of publication April 16, 2013; date of current version June 20, 2013. Paper no. TPWRD-00788-2012. K. Koziy and B. Gou are with North Dakota State University, Fargo, ND 58102 USA (e-mail: kostyantyn.koziy@my.ndsu.edu; bei.gou@ndsu.edu). J. Aslakson is with the Fourware LLC, Fargo, ND 58102 USA (e-mail: jaslakson@fourware.com). Color versions of one or more of the gures in this paper are available online at http://ieeexplore.ieee.org. Digital Object Identier 10.1109/TPWRD.2013.2251753

2) voltage drop and brownout, which takes place because of high loads, load imbalance, as well as reactive power and failures in power-supply networks; 3) voltage spike may occur at the moment of high, reactive load connection or lightning strokes; 4) frequency deviation is not considered as a signicant PQ problem, since it has a small (or zero) impact on most of modern electronic devices utilizing phase locks or uncontrolled rectiers; for some conventional and inexpensive equipment, it may lead to a clock speed increase/decrease, motor speed variations, etc. [1] Another major type is arc fault which requires close attention because of the severe damage it can bring. Arc faults normally take place due to wiring problems. It is the reason for 40 000 home res in the U.S. annually. Typical equipment (thermal resettable circuit breakers (CBs) and fuses) is insensitive to this kind of fault, because of its short duration. Furthermore, it is not easy to distinguish arc-fault conditions from those occurring during the operation of noisy devices (switching regulators, motors, etc.) A lot of research has been accomplished to develop reliable methods and algorithms for the detection of this type of failure; however, the detection accuracy still needs to be improved. Two types of arc faults exist: series and parallel. The rst type shown in Fig. 1 is the most abundant and occurs when the single power conductor breaks. Maximum arc current is then limited by the load current due to the series connection, which is denitely smaller than the CB current rating and depending on the load and, hence, the arc current may or may not produce a signicant amount of heat to create a re [4]. The parallel arc fault shown in Fig. 2 occurs between the neutral/ground and phase conductor, when the insulator is damaged due to mechanical, temperature stress, or aging [5]. In this case, high-impedance arc rst melts and carbonizes the insulator, and later the low-impedance current path is formed. The path emerges from excessive heat, and if left uninterrupted, it could ignite a re. Smart meters with U.S.$100 are available in the current market, but with limited functions. As an example, the popular BLI 28000/31100 PowerCost Monitor with wireless connection, EKM 15IDS and iConserve smart meters are capable of

0885-8977/$31.00 2013 IEEE

KOZIY et al.: LOW-COST PQ METER

1585

Fig. 2. Parallel arc-fault condition.

studying the arc at high current and high plasma temperature conditions) and Mayrs arc model [10]. The later one describes arc conductance around zero current and assumes constant arc diameter and power loss. This model works best for relatively low currents (tens Amperes) and due to that reason, it is appropriate for arc fault modeling in home and ofce wiring. Mayrs arc model is based on energy balance theory, accordingly (1) represents a change of storing energy per-unit arc where length, is an input power per-unit arc length, is an arc current, is electric intensity in the arc column, and is a power loss per-unit arc length. This can be expressed in form of arc gap conductance

only measuring, displaying, and logging supply power and cost, respectively. The separately sold arc-fault circuit interrupters price varies from U.S.$50 (e.g., Connecticut Electric Q120AF0) to U.S.$500 (e.g., Siemens B215AF), depending on the complexity. Overvoltage and overcurrent protection units are usually sold as transient voltage suppressors, combined with resettable thermal fuses (e.g., PowerSure EMC-240B, U.S.$170 range) and are not capable of logging fault events at all. And meters with integrated harmonic analysis, such as total harmonic distortion (THD), are pricy (e.g., RS PM700MG, U.S.$300). No one from the aforementioned listed units offers phase/neutral miswiring detection. The main purpose of this paper is to design a low-cost development platform suitable for detecting and logging PQ-related problems listed before along with additional features. This type of smart meter can help avoid the use of expensive equipment in homes by using the low-cost device which resolves conict situations during judicial proceedings. In current system implementation, arc-fault detection is applied to the series arc fault considered as the most common one that occurs at homes and ofces and may lead to res. Voltage and current peak/rms values need to be monitored as primary power-related parameters, required for overvoltage/overcurrent protection. Phase voltage THD is among the measured and logged parameters since its unacceptable levels lead to overheating of inductors, transformers, and capacitors. Phase/neutral miswiring indication and protection are also important since they may lead to improper grounding and humans injury or death from electric shock. Furthermore, phase frequency is also monitored, even though it does not affect consumer low-power equipment greatly and usually degrades efciency only. II. PROPOSED ALGORITHMS AND DESIGN This section presents theoretical design of the algorithms for PQ measurements and series arc-fault detection. A. Series Arc Fault Model The arc fault itself can be dened as a self-supporting electrical discharge in conductive ionized gas [3], with the maximum current limited by circuit operation parameters. Arc may just reduce the lifetime of electrical devices (switch blades, generator, or motor brushes, etc.) or may become hazardous (e.g., in electrical wiring) and lead to dramatic outcomes like res and explosions. The arc fault carries discontinuous, nonlinear, and nonsinusoidal characteristics. A number of models exist to describe its behavior. Among them, the most popular are Cassie (used for

(2) By dening the arc time constant as (3) and arc length , (2) can be rewritten as

(4) is where arc voltage is , power loss in arc column or is arc voltage constant. Then, (4) becomes (5) and consequently (6) Rising velocity can also be expressed in a form of (7) where is an empirically derived value equal to 2.9e-5, is maximum arc current (load for series or short circuit for parallel arc fault), is the arc length, and is equal to and must be found experimentally. Using equations (6) and (7), it is possible to build a simulation model for the series arc-fault case. The MATLAB Simulink model is shown in Fig. 3. AC represents the power-supply source, RS models its internal resistance, RLOAD models load resistance (constant resistive load is assumed), and the VM1 block measures the

1586

IEEE TRANSACTIONS ON POWER DELIVERY, VOL. 28, NO. 3, JULY 2013

To be a wavelet, must obey particular rules: to be oscillatory, to decay to zero from both sides, and have a zero integral. The second rule means that operates as high-pass lter. For a wavelet function (also called mother wavelet), a scale function can be dened, which, briey speaking, has an inverted (mirrored) frequency response (works as a low-pass lter). The discrete wavelet transform (DWT) of the discrete signal is a digital implementation of continuous wavelet transform, expressed as (10)
Fig. 3. Series arc-fault simulation model.

voltage across arc . The differential equation editor (DEE) block calculates the arc current :

with scale parameter and shift . A special case of transform occurs when , and , which is called a dyadic transform. DWT then can be implemented as a multistage FIR digital lter with downsampling. lter outputs then decompose the signal to low-frequency (called approximated signal A) and high-frequency (called detailed signal D) components. C. Adaptive Threshold, Peak Detection, and Load Trip

(8) where is the initial condition (initial arc conductivity). Arc current is then created using the Controlled Current Source block and measured by AM1 block. Res structure collects the data along with time stamp. The Hit Crossing block is required for the optimization of the simulation algorithm time step. The Start block denes the start time of the arc fault. The following parameters were used in the simulation: , , 25 A, 2 mm, . System voltage is 120 V/60 Hz, RLOAD is 5O hms, RS is 1O hm, and arc start time is 0.03 s. Simulation results are shown in Fig. 7. B. Wavelet Transform and its Application The main advantage of wavelet transform (WT) is an ability to concentrate on the short-time interval for high-frequency components and long-time interval for low-frequency components, which helps to extract localized pulses and high-frequency oscillations in the presence of fundamental frequency. Continuous wavelet transform of the signal is dened as (9) where is a wavelet function, is the scale, and is shift factors. As can be seen, the wavelet function works as a lter and WT operation simply lters a signal of interest by convolving it with this function and multiplying the result by a normalization factor to preserve energy on different scales. Advancing the factor slides the lters window along the signal time line. Increasing the factor stretches the lters impulse response (narrowing its frequency-response shape and moving it towar the lower frequencies).

The thresholding method is used to detect spikes in noisy signal components, obtained by performing three-level DWT decomposition of the original signal. A method using adaptive thresholding needs to be developed to determine if the signal level is higher than a particular value. The main advantage of using adaptive thresholding over xed is the ability to detect weak and strong magnitude transient current spikes that occur during arc fault. The xed threshold set to a high level may miss small spikes, and setting it too low may produce fault detection. There are many techniques with their advantages and disadvantages for adaptively setting the threshold, since this is a very popular topic in many applications that utilize signal analysis (e.g., action potential detection in neurons, in mass spectrometry, image processing). In [6], the threshold was adapted to noise using the following equation: (11) where represents the maximum value within the signal frame, is the averaged absolute value, is the mean absolute deviation, and is some constant, dened by the user. In [7], the amplitude threshold was selected based on (12) where represents the bandpass ltered signal, and the constant multiplier was found heuristically. Another interesting method was developed and used in [8] for action potential recognition, and is mentioned like AdaBandFlt. According to it, the signal frame is rst split by subframes of a particular size (10 ms), and then the rms value for every subframe is calculated. Values are then sorted and the 25th percentile is found as . From it, the threshold for the current frame is calculated as (13)

KOZIY et al.: LOW-COST PQ METER

1587

count the number of samples between markers and then derive the fundamental frequency (14) With the currently used sampling rate, the frequency resolution is 0.12 Hz. E. Voltage and Current RMS Calculation The rms value for time series
Fig. 4. Proposed algorithm of peak detection and repetition rate calculation.

of length

is dened as (15)

with a previous threshold dened as . This algorithm with some modications (subframe size changed to 17 ms that corresponds to the fundamental period of the power supply, and the number of subframes in frame is equal to 8) was implemented in our design to adaptively calculate the threshold value for every acquired frame. The entire peak detection and repetition rate calculation sequence are given in Fig. 4. Every 8.3 ms, one of the direct memory access (DMA) buffers becomes completely full with phase current/voltage samples. When this occurs, current samples are then processed using 3-level db2 DWT, and the D3 vector is saved to separate the D3 buffer. When it gets 512 samples, which is equal to approximately 133 ms (8 fundamental periods), it is then split to eight equal subframes. RMS is then calculated for every subframe, sorting is then carried out, and the second element (25th percentile) is picked to calculate the threshold . After obtaining the threshold, the absolute value of the D3 buffer is calculated and the triangle FIR lter is applied to smooth the data (in order to avoid detection of two closely located peaks). Peak is assumed if current data sample value is above the threshold, bigger than the previous sample, and lower or equal to the consecutive sample. The same D3 buffer is updated with either 0 (no peak) or 1 (peak) values. Simulation results are presented in Section V. D. Zero-Crossing and Fundamental Frequency Calculation To simplify signal analysis (e.g., RMS, THD calculation), working on exactly one period of fundamental frequency is preferred, starting and ending at zero points. In other cases, additional computations may be required (involving the use of windows). For that reason, the system contains the algorithm (ZC) that detects the phase voltage zero crossing points. The phase voltage signal rst passes through the fourth-order BPF, with 4070 Hz passband. It helps to attenuate dc offset and high-frequency noise that may affect zero crossing accuracy. After that, the algorithm detects a rising (or falling) edge of a sinusoidal waveform. If it is found, a position marker is then generated and used by THD and rms algorithms as the zero point (taking into consideration lter delay) for data processing. Only voltage is used for marker generation since it has stable magnitude, waveform, and less noise in comparison to current. Markers are also used to calculate the fundamental frequency (Fu block). Since sampling frequency is known, it is possible to

Zero-crossing markers are used to precisely extract one fundamental period (which, by the way, may deviate from its nominal value by 2 Hz). The subroutine (written on Assembler) processes available data by calculating the sum of squares. Since the single DMA buffer contains only portion of the fundamental period, division by the number of samples and the squared root is performed when the end marker is detected. RMS is calculated for current and voltage (Irms and Urms blocks, respectively). F. THD Calculation THD represents the deviation of signal waveform from pure sinusoidal, and for voltage and can be expressed as (16) where is the th harmonic rms, and is the maximum specied order. For 120-V power-supply networks, the maximum allowable THD is 5% (IEEE 519). There are a couple ways of measuring this index. Among them is the Fourier-based method, which requires relatively high computational effort and the use of variable sampling frequency. It provides slow response if high precision is required since a number of fundamental periods must be acquired. Also, since the method requires fundamental frequency calculation and sampling frequency adjustments which cannot be done at the same time, error goes up. Another relatively simple method utilizes BP lters to measure the magnitude of every component. Parallel lter implementation is possible which gives an advantage for eld-programmable gate-array implementation. However, lter coefcients have to be recalculated depending on the fundamental frequency change. One interesting way of measuring THD is to utilize the Goertzel lter, which is widely used for DTMF tone detection in communication applications [8]. This is a second-order resonance lter that can be considered as special case of DFT for single frequency. It can be implemented recursively using innite impulse response (IIR) equation, where the current output sample is calculated as follows:

(17)

1588

IEEE TRANSACTIONS ON POWER DELIVERY, VOL. 28, NO. 3, JULY 2013

Fig. 5. Proposed algorithm of THD calculation (MCU implementation).

Fig. 6. Smart-meter hardware block diagram.

where is the current input sample, and are previous output samples, and and represent the lter central frequency and sampling frequency, respectively. Since we are not interested in the ltered signal itself, but only in its magnitude for every harmonic of interest, after one fundamental period ( samples) is passed through the lter, its squared magnitude can be obtained through (18) where the term is (19) Every harmonic requires separate computations. The maximum number of harmonics is limited to MCU speed. In the current system, 10 harmonics are taken into consideration. However, MCU has enough resources to double this value even without optimization. THD is then calculated as (20) The zero-crossing start and end markers are used to identify one fundamental period of signal starting at 0. Since the fundamental frequency is calculated in the other block, it is also used in the THD block to dene which set of coefcients to use in (18). Since the DMA buffer size is not sufcient to keep at least 1 fundamental period, the duration of the previous period is used to select coefcients (assuming that the frequency cannot signicantly change). All coefcients are stored in the lookup table. Algorithm implementation is shown in Fig. 5. To verify the method and its accuracy, MATLAB simulation was performed. The signal with known harmonics was synthesized and processed using the aforementioned algorithm. The calculated THD result with a current sampling rate was found to be identical to the theoretical to the fourth sign after the decimal point. Of course, error in real implementation will be higher due to Q15 format truncation and zero-point detection imperfection. III. HARDWARE DESIGN The novel smart-meter hardware block diagram is shown in Fig. 6. The system is assumed to be located inside a power distribution box, before outlets and loads. Three lines of a

single-phase ac source (Hot, Neutral, and Ground) are under monitoring. The Hot line can be disconnected from loads with a help of a relay (20 A/120 V, T90S5D125), which is controlled by microcontroller unit (MCU) dsPIC33 through the intermediate solid-state relay HSR312. The last one can commutate 300-mA/250 V loads and allows controlling externally connected units (e.g., backup device, generator) for feature expansion. The Hall-effect current sensor ACS756 is used for bidirectional load current monitoring on the Hot line. It has a frequency operation range of 120 kHz that allows to successfully detect short-duration current spikes and drops. Up to 50 A can be monitored, producing the unidirectional voltage output convenient for interfacing to the MCU analog-to-digital converter (ADC) unit. Since the sensor itself provides an isolation of 3 kV, there is no need for additional precautions. Two voltage dividers (designated as D) are used to attenuate and shift input ac voltage to the allowable ADC input range. One divider between Hot (H) and Neutral (N) lines is used to measure ac voltage, while the other one between N and Ground (G) is utilized for the N/H wiring mix up detection feature: in case of their reversed connection, the ac signal will appear between N and G. This failure condition is checked and indicated to the user by the system during the startup cycle. Optical isolation is used to separate the high-voltage (HV) power line from the low-voltage (LV) controller and user side. In the nal design, this block can be removed to reduce the entire device cost; however, for development purposes, this precaution is obligatory. The two-channel isolator is built around optocoupler LOC211 and operational ampliers [2]. The : input voltage is converted to current owing through a light-emitting diode (LED), which illuminates a photodiode on the opposite side. Photodiode current is then converted to voltage. Since the optocoupler contains a second photodiode that is used as a feedback for input stage to compensate for LED starvation and temperature inuence, the isolator has very good linearity (photovoltaic topology used in the system, meets 12-b ADC performance). The isolated dcdc converter (3.3 V/5 V) is used to provide power for the HV isolator input side. Since digital signal processing is used for all power-quality analysis, anti-aliasing (designated as AA) lters are required prior to signal connection to ADC. This function is accomplished using the LTC1564 continuous time eighth-order lowpass (LP) lter, which allows selecting the cutoff frequency in a range of 150 kHz with a 10-kHz step using pins. In addition, the device also operates as a programmable gain amplier

KOZIY et al.: LOW-COST PQ METER

1589

Fig. 8. Smart meter MCU rmware top-level diagram.

Fig. 7. Completely assembled smart meter system.

(PGA) and allows setting the gain within the range of 16 V/V. Two AA lters and ampliers are used for phase voltage and current signals. A simple RC LP lter is used for the H/N wiring mixup signal, since there is no need to make an accurate analysis of it. Filter outputs are then connected to the MCU ADC input channels. The microcontroller itself is a microchip high-performance low-power 16-b device, designed for medium-level digital-signal-processing (DSP) applications. It can operate on up to 40 MIPS, supports single-cycle execution of DSP-related commands (e.g., multiplication and accumulation), contains a 10/12-b multichannel ADC with 2/4 channel simultaneous sample-and-hold capability, a sufcient amount of random-access memory (RAM), a DMA controller, and a number of peripherals. The system was designed to support two MCU series: dsPIC30 and dsPIC33. A low-noise linear 3.3-V regulator (LDO) provides power for the MCU, its ADC reference, and peripherals. To display the information, two light-emitting diodes (LEDs) and 7-segment 8-digit LED display are used. Its operation is under control of the MAX6951 device which communicates with the MCU using the SPI bus. For user entry, two push buttons and one potentiometer (connected to the ADC) are available. The UART interface is used for communication with PC. The in-circuit serial programming (ICSP) interface is required to program and debug the MCU. For future system expansion, non-volatile (NV) ferroelectric memory support (for failure logging) and two-channel DAC (for real-time debug of processing data) were also added. A smart meter was assembled on the double-sided printed-circuit board (PCB), using proper routing techniques and shielding for noise reducing and stable operation. The completely assembled system is shown in Fig. 7. IV. FIRMWARE GENERAL STRUCTURE The overall structure of the current MCU rmware version is shown in Fig. 8. Phase current (I), voltage (U1) and wiring mix up fault voltage (U2) are connected to three ADC channels. After MCU reset and initialization, U2 is sampled for a short period of time to check if any voltage is present. If so, the system disconnects the load (Trip routine), sends error message on display, and halts. The user must reverse H/N wires and restart the system (currently implemented through the Reset button). When this

check is passed, U2 is no longer in use and ADC is set to simultaneously sample I and U2 channels with a 30.8-kHz sampling rate. This rate was found to be appropriate and universal to satisfy the needs of all algorithms. Every time sampling circuit stops sampling, two channels are sequentially converted by ADC and results are put to buffer. The system uses DMA to reduce the amount of MCU cycles required to transfer data from ADC to RAM. Two DMA buffers (called Ping-Pong buffers), 508 samples each, are assigned for that purpose (the maximum buffer size is limited by MCU hardware). Every new I and U1 samples are stored sequentially to one of them. When one buffer is full, a special ag is set to let data processing unit (DTU) know that information is ready to be processed. After that, the next buffer is going to be lled with a new portion of data. DTU must process all data before the other buffer becomes full. DTU contains a number of algorithms (explained in Section II) for power quality analysis. The band-pass lter (BPF) with 70-Hz passband is used to remove dc offset from U1 and lter out noise. It is then used for precise zero-crossing (ZC) detection, required for fundamental frequency calculation (Fu), phase voltage and current rms values (Urms, Irms), and THD. Arc-fault detection block stays apart. It involves the use of discrete wavelet transform (DWT), adaptive thresholding (AT), and peak-detection (PD) algorithms along with the peak repetition rate (PRR) calculation that is then used to make a decision about tripping the load. Shared variables are used to pass and exchange calculated and statistic information between algorithm blocks, read and process user input (CTRL, e.g., change parameter for displaying, trip the load, reset fault event counter), trip circuit, and update information on screen. The last procedure also involves the use of DMA:3rd buffer with eight words and is assigned for the light-emitting diode (LED) controller SPI communication. Everytime a display has to be updated, the system loads the buffer with control and data words. Then transmission is initiated and the rest of the task is held automatically by the DMA controller. NV memory, DAC, and UART communication interfaces (except the one used to display debug data) currently do not have any code support. It will be added in future rmware revisions in a future study. The next section shows the simulation results obtained from the proposed algorithms and the hardware designs. V. SIMULATION RESULTS This section presents simulation results and operation of algorithms used for power-quality measurements and series arc-fault detection.

1590

IEEE TRANSACTIONS ON POWER DELIVERY, VOL. 28, NO. 3, JULY 2013

Fig. 10. Series arc-fault feature extraction using DWT and db2.

Fig. 9. Series arc-fault simulation results.

A. Detection of Series arc Faults Based on the algorithm and hardware design presented in Section II, simulation results are obtained and shown in Fig. 9. Since the PQ meter is located before load wiring, there is no way to measure arc voltage, and only current information can be used to recognize the arc-fault-related patterns. As can be observed in Fig. 9, the series arc fault creates a distortion of sinusoidal load current. Due to this fact that it is obvious that by performing harmonic analysis, specic frequency components can be extracted, its level can be measured and based on some rule, a decision can be made to trip the load. The problem is that many electronic devices (e.g., switching regulators, inverters) also produce similar harmonic distortions, which makes it hard to distinguish. Fast Fourier transform (FFT) is usually utilized for frequency-domain analysis. However, it does require the analyzed signal to be stationary and periodic, which is not the case for power-supply current, containing disturbances. The other problem with FFT is the picket fence effect (resolution bias error), which is produced if a signal contains harmonics that are not integer multiples of resolution frequency. To overcome these drawbacks (along with couple others), a wavelet transform (WT) can be alternatively used to analyze signal timefrequency localization [11]. Daubechies Wavelets is a family of orthogonal wavelets with compact support. This allows extracting local signal disturbances with very high quality (ignoring fundamental components). Experimentally, it was found that series arc fault disturbances in load current lay within 2 4-kHz range, which corresponds to detail level 3 (D3) of DWT on the 30756-Hz sampling rate. Daubechies wavelets db2 were found appropriate for extracting arc-fault features. LPF and HPF FIR lter coefcients were then obtained and used in the algorithm. Results of its operation are shown in Fig. 10.

Fig. 11. Peak repetition rate and load-trip algorithm operation.

B. Adaptive Threshold, Peak Detection, and Load Trip Fig. 11 demonstrates adaptive thresholding and peak detection, repetition rate calculation using the average lter, and trip algorithm simulation graphs. After peaks have been identied, a nal step for the algorithm is to calculate their repetition rate and trip the relay if the rate is higher than the predened value. This operation is based on average (rectangular FIR) lter: the higher the repetition rate, the higher output lter will produce. In current test implementation, it is assumed that series arc fault condition is 4 spikes, appearing within two fundamental periods (33 ms). Then, we can dene lter width equal to 33 ms or 128 sample of detailed signal D3. Passing peak signal and monitoring lter output, the load must be tripped if lter output gets 4/128 0.03. VI. EXPERIMENTAL RESULTS Fig. 12 shows a real arc-fault algorithm operation on MCU, even though actual input arc-fault current sample test vector

KOZIY et al.: LOW-COST PQ METER

1591

patterns, and adjust coefcients appropriately. Also, additional algorithm optimization will help to free up more space for additional functionality like fault logging to NV memory, data output through the serial port, wireless communication with a host or between similar devices using a network like ZigBee, Ethernet-based control, and monitoring interface. Depending on the requirements, the system could be redesigned by removing some hardware elements (in particular, analog isolation, power supply, integrated-circuit-based antialiasing lters, and excess controls), making the device smaller and convenient to be installed in a power distribution box or outlet, which will be reported in our future research papers. REFERENCES
[1] M. Rashid, Power Electronics Handbook. London, U.K.: Academic Press, 2006, p. 1054. [2] Vishay Siliconix website, Designing linear ampliers using the IL300 optocoupler, Mar. 20, 2012. [Online]. Available: http://www.vishay. com/docs/83708/appn50.pdf [3] I. Khan and M. Critchley, Arc fault detector, 2000, vol. 25, no. 3, pp. 14. [Online]. Available: http://ebookbrowse.com/arc-fault-detector-paper-pdf-d245318580 [4] M. Naidu, T. Schoepf, and S. Gopalakrishnan, Arc fault detection scheme for 42 V automotive DC networks using current shunt, IEEE Trans. Power Electron., vol. 21, no. 3, pp. 633639, May 2006. [5] N. Zamanan, J. Sykulski, and A. K. Al-Othman, Arcing high impedance fault detection using real coded genetic algorithm, in Proc. IEEE 3rd Lasted Asians Conf., Power Energy Syst., Japan, Aug. 2021, 2007, pp. 197203. [6] M. Ma1, A. van Genderenl, and P. Beukelman, Developing and implementing peak detection for real-time image registration, in Proc. 16th Annu. Workshop Circuits, Syst. Signal Process., Nov. 2005, pp. 641652. [7] R. Q. Quiroga, Z. Nadasdy, and Y. Ben-Shaul, Unsupervised spike detection and sorting with wavelets and superparamagnetic clustering, Neural Comput., vol. 16, pp. 166187, 2004. [8] E. Bif, D. Ghezzi, A. Pedrocchi, and G. Ferrigno, Development and validation of a spike detection and classication algorithm aimed at implementation on hardware devices, Comput. Intell. Neurosci., vol. 2010, pp. 115, Nov. 30, 2009, Article ID 659050. [9] R. Beck and G. Dempster, Finite-precision Goertzel lters used for signal tone detection, IEEE Trans. Circuits Syst. II, Analog Digit. Signal Process., vol. 48, no. 6, pp. 691700, Jun. 2001. [10] J. L. Guardado, S. G. Maximov, E. Melgoza, J. L. Naredo, and P. Moreno, An improved arc model before current zero based on the combined Mayr and Cassie arc models, IEEE Trans. Power Del., vol. 20, no. 1, pp. 138142, Jan. 2005. [11] I. Daubechies, The wavelet transform, time-frequency localization and signal analysis, IEEE Trans. Inf. Theory, vol. 36, no. 5, pp. 9611005, Sep. 1990. [12] Bureau International des Poids et Measures, Evaluation of measurement dataGuide to the expression of uncertainty in measurement, Sep. 2008. [Online]. Available: http://www.bipm.org/en/publications/ guides/gum.html Kostyantyn Koziy received the B.Sc. degree in electrical engineering from North Dakota State University, Fargo, ND, USA, in 2012.

Fig. 12. Peak detection algorithm, implemented on MCU.

was retrieved from simulation and then used to substitute the ADC data buffer. The top graphic in Fig. 12 represents 40-A load current with additional noise, scaled according to the gain of the analog front-end circuit and ADC resolution. The middle graphic shows the actual state of the detailed signal D3 buffer, after all of the described operations. The calculated threshold value is depicted as TH. The bottom graphic shows the D3 buffer state after peak detection. With a lack of the measurement model [12] , this paper has difculty presenting devices that accurately estimate different measurement parameters. However, in general, using the 12-b ADC built-in typical MCU, with at a 30-kHz sampling rate, and applying proper signal conditioning and sensors, it is possible to achieve 2-2.5% full-scale accuracy in power measurements with a dynamic range around 50 (e.g., current of 0.5-25 A). This can be sufcient for consumer use. VII. CONCLUSION AND FUTURE WORK In our current work, a system was designed and developed that is capable of measuring single-phase PQ-related parameters and series arc-fault detection conditions in home and ofce wiring. The system is built around a low-cost microcontroller with DSP capabilities, contains all necessary elements (sensors, isolation, indication, and user control, load trip relay), and can be easily extended by adding features in rmware. It could be directly applied to smart grid due to its low-cost, wireless, and logging capabilities, a wide range of monitoring parameters and their derivatives, and integration exibility. The next step would be to perform experiments around arcfault generation, test how well an algorithm can recognize fault

Bei Gou (M13) received the Ph.D. degree in electrical engineering from Texas A&M University, College Station, TX, USA, in 2000. Currently, he is an Associate Professor in the Department of Electrical and Computer Engineering, North Dakota State University, Fargo, ND, USA.

Joel Aslakson is the Founder of startup company Fourware LLC, Fargo, ND, USA.