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Zero Threshold Pass Transistors

Zero Threshold Pass Transistors means zero threshold voltage of the n-MOS transistors in the pass gate network. Zero threshold voltage can be achieved via threshold adjustments implants which can eliminate the drop of threshold voltage. The n-MOS pass transistors have been applied in an adopting circuit called Complementary Pass Logic circuit (CPL). This CPL can minimize the complexity of full CMOS pass gate logic circuits. Instead of using a CMOS TG network, n-MOS pass transistor network has been chosen for the logic operations. All inputs are used in the complementary form. For instance, every input signal and its inverse must be supplied. Besides that the circuit also created complementary outputs, to be minimized by the consequent CPL stages. Hence, the CPL circuit consists of complementary; an n-MOS pass transistor logic network to produce complementary outputs, and CMOS output inverters to save the output signals [1]

How Zero Threshold Transistor Functioning

A composite CMOS gate is consists of whether NAND and NOR gates where it has nMOS pull down circuit and p-MOS pull up circuit. In order to achieve a Zero Threshold Pass Transistor, n-MOS pull down circuit is used. N-MOS pull down circuit is connected between the GND node and the gate output y as shown in Figure 1 below.

Figure 1: A generalized schematic of composite CMOS gate. The logic function implemented on the composite gate is represented in complemented form:

Where x is an n-bit input vector and y is a 1-bit output signal. In the n-MOS pull down circuit case, it specifies the zeros of function f when output y is connected to the GND node. Thus, n-MOS pull down circuit is complemented by the original function of n-MOS: The function allows zero threshold voltage to pass through the transistor. [2]

Figure 2: A diagram shows how n-MOS passes a 0 When input voltage is equal to , the p-MOS device will be cut-off and the input

voltage will pass through n-MOS hence be equal to

Figure 3: The marked flow of voltage and current in CMOS inverter When p-MOS is cut-off, the drain current for p-MOS, n-MOS is also equals to zero. When | and the drain current for

the drain to source voltage for n-MOS | |

= 0. As long as the p-MOS device is cut-off, the output voltage will always be zero, or | and input voltage is in the range of [3]

Zero Threshold Pass Transistor Advantages To prevent threshold voltage loss that causes the static power consumption and slower transition.

Reduce the overall noise immunity.

Makes the transistors more susceptible to sub threshold conduction in the OFF mode.


When using this Zero Threshold Pass Transistor, the body effect will still cause an increase in the threshold voltage

It also can cause leakage through multiple gates

Leakage Through Zero-Threshold Transistors

While these leakage paths are not critical when the device is switching constantly, they do pose a large energy overhead when the circuit is in the ideal state.

REFERENCES [1] Sung-Mo Kang and Yusuf Leblebici, CMOS digital integrated circuits: Analysis and Design, 3/e, Tata Mcgraw-hill, 2003. [2] [3] A.P.Paplinski, IC Design, July 31, 2001. Pg 6-7. docs-archive.com (n.d.). NMOS Inverter. Retrieved on January 1, 2014 from docs-archive.com: https://www.google.com/url?sa=t&rct=j&q=&esrc=s&source=web&cd=5&cad=rj a&ved=0CEQQFjAE&url=http%3A%2F%2Fwww.docsarchive.com%2Fview%2F6ad2d0f74279ddd5cda2aad76d0398b8%2FChapter16.1-NMOS-Inverter-University-of-SouthAlabama.pdf&ei=PQjEUpixJ8G3rge39YHQCA&usg=AFQjCNH6qvavvDzXFnI 0Z3E7IpU6KyoyUg&sig2=mxfxC88dXKp19B7nJ84RiA&bvm=bv.58187178,d. bmk