Problem Definition: FPGA implementation of D flip flop

PROGRAM CODE:
At first the on board clock frequenc of ! Mh" has to be reduced to a si#nificant le$el %& '"( for the proper functionin# of the flip flops) Reduction of clock frequenc %C*OC+ GE,( entit clk-#en is Port % clk-in : in ./D-*OG0C1 clk-out : out ./D-*OG0C(1 end clk-#en1 architecture 2eha$ioral of clk-#en is si#nal d : std-lo#ic1 be#in process %clk-in( $ariable a :inte#er :3 41 $ariable $ : std-lo#ic :3 5451 $ariable d : std-lo#ic1 be#in if %clk-in 3 5&5 and clk-in5e$ent( then a:3 a6&1 if %a3!444444( then d :3 5&51 a :3 41 else d :3 5451 end if1 if d3 5&5 then $ :3 not $1 end if1 end if1 clk-out 73 $1 end process1 end beha$ioral1 Pro#ram code for D flip flops entit dff is port %d8rst8clk : in std-lo#ic1 q8qbar : out std-lo#ic(1 end dff1 architecture 2eha$ioral of tff is be#in process%clk( be#in if %clk35&5 and clk5e$ent( then if rst3545 then q73 5451 else q 73 d1 end if1 end if1 end process1 end 2eha$ioral;

0ntroduction of Reducin# frequenc in d flip flops entit fp#adff is port %clk : in std-lo#ic1 rst : in std-lo#ic1 d : in std-lo#ic1 q : out std-lo#ic1 qbar : out std-lo#ic(1 end fp#adff1 architecture 2eha$ioral of fp#adff is component dff is Port % d8 rst8 clk : in std-lo#ic1 q : out std-lo#ic1 qbar : out std-lo#ic(1 end component1 component clk-#en is Port % clk-in : in ./D-*OG0C1 clk-out : out ./D-*OG0C(1 end component1 si#nal s : std-lo#ic1 be#in p& : clk-#en port map %clk8s(1 p9 : dff port map %d8rst8s8q8qbar(1 end 2eha$ioral1

F0,A* REPOR/
Desi#n .tatistics : 0O. : ! Cell usa#e : 2E*. : 94; : G,D : & : 0,< : ! : *=/& : >9 : *=/9 : ; : <CC : &

: ?ORC@ : >9 : F*0P F*PO.A *A/C'E. : BC : FD : 9 : FDE 1 & : C*OC+ 2=FFER : &

: 2=F GP: & : M=?C@ : D4 : 0O 2uffers: B :02=F : & :O2=F : &9

/R=/' /A2*E:
C*OC+ PD> .OFF .O, .O, .O, R./EP&!4FiAp sGitch C*C+EPD>EiAp sGitch DEP&!&EiAp sGitch HEP&>&FoAp *ED H2AREP&D9FoAp *ED .O,F.Gitch O, R./ P&!4 .OFF .O, .OFF .OFF D P&!& .OFFA.O, .OFFA.O, .O, .OFF H P&>& *OFF *OFF *O, *OFF H2AR P&D9 *O, *O, *OFF *O,

.OFFF.Gitch OFF *O,F*ED O, *OFFF*ED OF

Problem Definition: FPGA implementation of / flip flop

PROGRAM CODE:
At first the on board clock frequenc of ! Mh" has to be reduced to a si#nificant le$el %& '"( for the proper functionin# of the flip flops) Reduction of clock frequenc %C*OC+ GE,( .ame as before) Pro#ram code for / flip flops entit tff is port %t8rst8clk : in std-lo#ic1 q8qbar : out std-lo#ic(1 end tff1 architecture 2eha$ioral of tff is be#in process%clk( $ariable $ : std-lo#ic :3 5451 be#in if %clk35&5 and clk5e$ent( then if %rst35&5( then $ :3 5451 elsif %t35&5( then $ :3 not $1 end if1 q 73 $1 qbar 73 not $1 end if1 end process1 end 2eha$ioral1 0ntroduction of Reducin# frequenc in / flip flops entit fp#atff is port %clk8 t8 : in std-lo#ic1 q8 qbar: out std-lo#ic1(1 end fp#adff1 architecture 2eha$ioral of fp#atff is entit tff is component %t8clk : in std-lo#ic1 q8qbar : out std-lo#ic(1 end component1 component clk-#en is Port % clk-in : in ./D-*OG0C1 clk-out : out ./D-*OG0C(1 end component1 si#nal s : std-lo#ic1 be#in p& : clk-#en port map %clk8s(1 p9 : tff port map %t8s8q8qbar(1 end 2eha$ioral1

F0,A* REPOR/
Desi#n .tatistics : 0O. : C Cell usa#e : 2E*. : 9&4 : G,D : & : 0,< : ! :*=/&: >9 : *=/B : & : *=/9 : & :*=/! : ;

: <CC : & : ?ORC@ : >9 : *0P F*PO.A *A/C'E. : BC : FDR : B! : FDE 1 & : C*OC+ 2=FFER : &

: 2=F GP: & : M=?C@ : D4 : 0O 2uffers: ! :02=F : 9 :O2=F : 9 :FDRE : B

/R=/' /A2*E:
C*+ J 4 & & & & R./ & 4 4 4 4 4 R./ P&!4 .O, .OFF .OFF .OFF .OFF .OFF / 4 J 4 4 & & H, 4 qn 4 & 4 & / P&!& .OFF .O,A.OFF .OFF .OFF .O, .O, H,6& 4 qn 4 & & 4 H,6& P&>& *OFF *OFF *OFF *O, *O, *OFF HI,6& & qIn & 4 4 & HI,6& P&D9 *O, *O, *O, *OFF *OFF *O, .OFFF.Gitch OFF *O,F*ED O, *OFFF*ED OF

C*+ PD> .OFFA.O, .OFF .O, .O, .O, .O,

R./EP&!4FiAp sGitch C*C+EPD>EiAp sGitch DEP&!&EiAp sGitch

HEP&>&FoAp *ED H2AREP&D9FoAp *ED .O,F.Gitch O,