Chapter 4

Combinational Functions and Circuits

Dr. I. Damaj 1

Overview
„ Functions and functional blocks
„ Rudimentary logic functions
„ Decoding
„ Encoding
„ Selecting
„ Implementing Combinational Functions Using:
„ Decoders and OR gates
„ Multiplexers (and inverter)
„ ROMs
„ PLAs
„ PALs
„ Lookup Tables
Dr. I. Damaj 2

1
 Functions and Functional Blocks

„ The functions considered are those found to be very useful in design

„ Corresponding to each of the functions is a combinational circuit

implementation called a functional block.

„ In the past, many functional blocks were implemented as SSI, MSI,

and LSI circuits.

„ Today, they are often simply parts within a VLSI circuits.

Dr. I. Damaj 3

Rudimentary Logic Functions

„ Functions of a single variable X TABLE 4-1

„ Can be used on the Functions of One Variable
inputs to functional
blocks to implement X F=0 F=XF= X F=1
other than the block’s
intended function 0 0 0 1 1
1 0 1 0 1

V CC or V DD

1 F5
= 1 F=
5 1 X F=5 X
(c)

0 F=
5 0 F=
5 0
X F=5 X
Dr. I. Damaj 4
(a) (b) (d)

2
Multiple-bit Rudimentary Functions

„ Multi-bit Examples:
A F3 A
3 2
1 F2 1 2 4 4 2:1 F(2:1)
F F
0 F1 0 1
0 (c)
A F0 A
(a) (b) 3
„ A wide line is used to represent 4 3,1:0 F(3), F(1:0)
a bus which is a vector signal F
„ In (b) of the example, F = (F3, F2, F1, F0) is a bus. (d)
„ The bus can be split into individual bits as shown in (b)
„ Sets of bits can be split from the bus as shown in (c)
for bits 2 and 1 of F.
„ The sets of bits need not be continuous as shown in (d) for bits 3, 1, and 0
of F.
Dr. I. Damaj 5

Enabling Function

„ Enabling permits an input signal to pass through to an output

„ Disabling blocks an input signal from passing through to an output,

replacing it with a fixed value

„ The value on the output when it is disable can be Hi-Z (as for three-
state buffers), 0 , or 1
X
F
EN
„ When disabled, 0 output
(a)
„ When disabled, 1 output
X
F
EN

(b)
Dr. I. Damaj 6

3
 Decoding

„ Decoding - the conversion of an n-bit input code to an m-bit output

code with n ≤ m ≤ 2n such that each valid code word produces a
unique output code

„ Circuits that perform decoding are called decoders

„ Here, functional blocks for decoding are

„ called n-to-m line decoders, where m ≤ 2n, and
„ generate 2n (or fewer) minterms for the n input variables

Dr. I. Damaj 7

Decoder Examples
A D0 D1
„ 1-to-2-Line Decoder D 0=
5 A
0 1 0
1 0 1 A D 1=
5 A
„ 2-to-4-Line Decoder A0 (a) (b)
A1 A0 D0 D1 D2 D3
A1
0 0 1 0 0 0 D0 = A1 A0
0 1 0 1 0 0
1 0 0 0 1 0
1 1 0 0 0 1 D1 = A1 A0

(a)
D2 = A1 A0
ƒ Note that the 2-4-line
made up of 2 1-to-2-
D3 = A1 A0
line decoders and 4 AND gates.
Dr. I. Damaj (b) 8

4
 Decoder Expansion
„ General procedure given in book for any decoder with n inputs and
2n outputs.

„ This procedure builds a decoder backward from the outputs.

„ The output AND gates are driven by two decoders with their
numbers of inputs either equal or differing by 1.

„ These decoders are then designed using the same procedure until
2-to-1-line decoders are reached.

„ The procedure can be modified to apply to decoders with the

number of outputs ≠ 2n
Dr. I. Damaj 9

Decoder Expansion - Example 1

„ 3-to-8-line decoder
„ Number of output ANDs = 8
„ Number of inputs to decoders driving output ANDs = 3
„ Closest possible split to equal
„ 2-to-4-line decoder

„ 1-to-2-line decoder

„ 2-to-4-line decoder
„ Number of output ANDs = 4

„ Number of inputs to decoders driving output ANDs =

2
„ Closest possible split to equal
ƒ Two 1-to-2-line decoders
„ See next slide for result
Dr. I. Damaj 10

5
Decoder Expansion - Example 1

„ Result 4 2-input ANDs 8 2-input ANDs

D0
A0

D1

A1
D2

2-to-4-Line D3
decoder
D4

A2 D5

1-to-2-Line decoders D6

D7
Dr. I. Damaj 11

3-to-8 Line decoder

4.3 Decoding
Truth Table for 3–to–8-Line Decoder

An n-bit binary code could represent up to 2n distinct elements of Coded information

Dr. I. Damaj 12

6
 4.3 Decoding
3-to-8-Line Decoder

An n-bit binary code

Could represent up to
2n distinct elements of
Coded information

Dr. I. Damaj 13

Decoder with Enable

„ In general, attach m-enabling circuits to the outputs
„ See truth table below for function
„ Note use of X’s to denote both 0 and 1
„ Combination containing two X’s represent four binary
combinations
„ Alternatively, can be viewed asEN
distributing value of signal EN to 1 of
4 outputs A1
„ In this case, called a
A0
demultiplexer D0

EN A 1 A 0 D0 D1 D2 D3 D1

0 X X 0 0 0 0
1 0 0 1 0 0 0 D2
1 0 1 0 1 0 0
1 1 0 0 0 1 0
D3
1 1 1 0 0 0 1 14
Dr. I. Damaj

(a) (b)

7
 Encoding
„ Encoding - the opposite of decoding - the conversion of an m-bit
input code to an n-bit output code with n ≤ m ≤ 2n such that each
valid code word produces a unique output code

„ Circuits that perform encoding are called encoders

„ An encoder has 2n (or fewer) input lines and n output lines which
generate the binary code corresponding to the input values

„ Typically, an encoder converts a code containing exactly one bit that

is 1 to a binary code corresponding to the position in which the 1
appears.

Dr. I. Damaj 15

Encoder Example

„ A decimal-to-BCD encoder
„ Inputs: 10 bits corresponding to decimal digits
0 through 9, (D0, …, D9)
„ Outputs: 4 bits with BCD codes
„ Function: If input bit Di is a 1, then the output
(A3, A2, A1, A0) is the BCD code for i,
„ The truth table could be formed, but
alternatively, the equations for each of the four
outputs can be obtained directly.

Dr. I. Damaj 16

8
 Encoder Example (continued)

„ Input Di is a term in equation Aj if bit Aj is 1 in the

binary value for i.

„ Equations:
A3 = D8 + D9
A2 = D4 + D5 + D6 + D7
A1 = D2 + D3 + D6 + D7
A0 = D1 + D3 + D5 + D7 + D9

Dr. I. Damaj 17

Another Example
An encoder is a digital function that performs the inverse operation of a
decoder. It has 2n (or fewer) input lines and n output lines.

Dr. I. Damaj 18

9
 Another Example
„ For the 8-to-3-line encoder, the resultant
equations are:
„ A0 = D1 + D3 + D5 + D7
„ A1 = D2 + D3 + D6 + D7
„ A2 = D4 + D5 + D6 + D7

„ These equations can be implemented with

three 4-input OR gates.

Dr. I. Damaj 19

Priority Encoder

„ If more than one input value is 1, then the encoder just designed
does not work.

„ One encoder that can accept all possible combinations of input

values and produce a meaningful result is a priority encoder.

„ Among the 1s that appear,

„ it selects the most significant input position (or the least
significant input position) containing a 1
„ and responds with the corresponding binary code for that
position.

Dr. I. Damaj 20

10
Priority Encoder
„ Input D3 has the highest priority, so regardless of the values of
the other inputs, the output for A1A0 is 11.

„ The valid output (V) is set to 1 only when 1 or more of the inputs
are equal to 1.

Dr. I. Damaj 21

Priority Encoder

Dr. I. Damaj 22

11
 Selecting

„ Selecting of data or information is a critical function in digital

systems and computers

„ Circuits that perform selecting have:

„ A set of information inputs from which the selection is made
„ A single output
„ A set of control lines for making the selection

„ Logic circuits that perform selecting are called multiplexers

„ Selecting can also be done by three-state logic or transmission

gates

Dr. I. Damaj 23

Multiplexers
„ A multiplexer selects information from an input line
and directs the information to an output line
„ A typical multiplexer has n control inputs (Sn − 1, …
S0) called selection inputs, 2n information inputs (I2n −
1, … I0), and one output Y
„ A multiplexer can be designed to have m information
inputs with m < 2n as well as n selection inputs

Dr. I. Damaj 24

12
 2-to-1-Line Multiplexer
„ Since 2 = 21, n = 1
„ The single selection variable S has two values:
„ S = 0 selects input I0
„ S = 1 selects input I1
„ The equation:
Y = S’I0 + SI1
„ The circuit:
Enabling
Decoder Circuits

I0
Y
S
Dr. I. Damaj I1 25

2-to-1-Line Multiplexer (continued)

„ Note the regions of the multiplexer circuit shown:
1-to-2-line Decoder
„
2 Enabling circuits
„
„ 2-input OR gate
„ To obtain a basis for multiplexer expansion, we combine the
Enabling circuits and OR gate into a 2 ´ 2 AND-OR circuit:
„ 1-to-2-line decoder
„ 2 ´ 2 AND-OR
„ In general, for an 2n-to-1-line multiplexer:
„ n-to-2n-line decoder
„ 2n ´ 2 AND-OR

Dr. I. Damaj 26

13
Example: 4-to-1-line Multiplexer
„ 2-to-22-line decoder
„ 22 ´ 2 AND-OR
Decoder
S1

4 3 2 AND-OR
S0
Decoder
S1

S0
I0

Y
I1
Y

I2

Dr. I. Damaj I3 27

Other Selection Implementations

„ Three-state logic in place of AND-OR
S0
I0

I1
S1
Y
I2

I3

(b)
„ Gate input cost = 14 compared to 22 (or 18) for gate
implementation
Dr. I. Damaj 28

14
Other Selection Implementations
„ Transmission Gate Multiplexer
S0

S1

„ Gate input
cost = 8 I0 TG
(S0 5 0)

compared TG
(S1 5 0)
to 14 for I1
TG

3-state logic
(S0 5 1)

and 18 or 22 Y

TG
for gate logic I2
(S0 5 0)

TG
(S1 5 1)

TG
I3 (S0 5 1)
Dr. I. Damaj 29

Combinational Function Implementation

„ Alternative implementation techniques:
„ Decoders and OR gates
„ Multiplexers (and inverter)
„ ROMs
„ PLAs
„ PALs
„ Lookup Tables
„ Can be referred to as structured implementation methods
since a specific underlying structure is assumed in each
case
Dr. I. Damaj 30

15
 Decoder and OR Gates
„ Implement m functions of n variables with:
„ Sum-of-minterms expressions
„ One n-to-2n-line decoder
„ m OR gates, one for each output

„ Approach:
„ Find the truth table for the functions
„ Make a connection to the corresponding OR from the
corresponding decoder output wherever a 1 appears in the truth
table

Dr. I. Damaj 31

Decoder and OR Gates Example

„ Implement the following set of odd parity functions of (A7, A6, A5, A3)
P1 = A7 xor A5 xor A3
P2 = A7 xor A6 xor A3
A7 0 P1
A6 1
P4 = A7 xor A6 xor A5 2
„ Finding sum of A5 3
minterms expressions A4 4
5 P2
P1 = Σm(1,2,5,6,8,11,12,15) 6
P2 = Σm(1,3,4,6,8,10,13,15) 7
8
P4 = Σm(2,3,4,5,8,9,14,15) 9
„ Find circuit 10 P4
11
„ Is this a good idea? 12
13
14
15
Dr. I. Damaj 32

16
Multiplexer Approach 1
„ Implement m functions of n variables with:
„ Sum-of-minterms expressions
„ An m-wide 2n-to-1-line multiplexer
„ Design:
„ Find the truth table for the functions.
„ In the order they appear in the truth table:
„ Apply the function input variables to the
multiplexer inputs Sn − 1, … , S0
„ Label the outputs of the multiplexer with the
output variables
„ Value-fix the information inputs to the multiplexer using
the values from the truth table (for don’t cares, apply
either 0 or 1)

Dr. I. Damaj 33

Example: Gray to Binary Code

„ Design a circuit to
convert a 3-bit Gray Gray Binary
code to a binary code ABC xyz
000 000
„ The formulation gives 100 001
the truth table on the 110 010
right 010 011
011 100
111 101
„ It is obvious from this 101 110
table that X = C and the 001 111
Y and Z are more complex
Dr. I. Damaj 34

17
 Gray to Binary (continued)
„ Rearrange the table so Gray Binary
that the input combinations
are in counting order ABC xyz
000 000
„ Function x is the same as C 001 111
010 011
„ Functions y and z can 011 100
be implemented using 100 001
a dual 8-to-1-line
multiplexer by: 101 110
110 010
111 101
„ connecting A, B, and C to the multiplexer select inputs
„ placing y and z on the two multiplexer outputs
„ connecting their respective truth table values to the inputs
Dr. I. Damaj 35

Gray to Binary (continued)

0 D00 0 D10
1 D01 1 D11
1 D02 1 D12
0 D03 0 D13
0 D04 1 D14
Out Y Out Z
1 D05 0 D15
1 D06 0 D16
0 D07 1 D17
A S2 A S2 8-to-1
8-to-1
B S1 B S1
C S0 MUX C S0 MUX
„ Note that the multiplexer with fixed inputs is identical to a ROM with
3-bit addresses and 2-bit data!
Dr. I. Damaj 36

18
 Multiplexer Approach 2
„ Implement any m functions of n + 1 variables by using:
„An m-wide 2n-to-1-line multiplexer
„ A single inverter
„ Design:
„ Find the truth table for the functions.
„ Based on the values of the first n variables, separate the truth
table rows into pairs
„ For each pair and output, define a rudimentary function of the
final variable (0, 1, X, X’)
„ Using the first n variables as the index, value-fix the information
inputs to the multiplexer with the corresponding rudimentary
functions
„ Use the inverter to generate the rudimentary function X’

Dr. I. Damaj 37

Example: Gray to Binary Code

„ Design a circuit to
convert a 3-bit Gray Gray Binary
code to a binary code ABC xyz
000 000
„ The formulation gives 100 001
the truth table on the 110 010
right 010 011
011 100
111 101
„ It is obvious from this 101 110
table that X = C and the 001 111
Y and Z are more complex
Dr. I. Damaj 38

19
 Gray to Binary (continued)

„ Rearrange the table so that the input combinations are in counting

order, pair rows, and find rudimentary functions
Gray Binary Rudimentary Rudimentary
ABC xyz Functions of C Functions of C
for y for z

000 000
F=C F=C
001 111
010 011
F=C F=C
011 100
100 001
F=C F=C
101 110
110 010
F=C F=C
Dr. I. Damaj 111 101 39

Gray to Binary (continued)

„ Assign the variables and functions to the multiplexer inputs:

C D00 C D10
C D01 C D11
C C
C D02 Out Y C D12 Out Z
C D03 C D13

A S1 8-to-1 A S1 8-to-1
B S0 MUX B S0 MUX

„ Note that this approach (Approach 2) reduces the cost by almost half
compared to Approach 1.
„ This result is no longer ROM-like
„ Extending, a function of more than n variables is decomposed into several
sub-functions defined on a subset of the variables. The multiplexer then
selects among these sub-functions.
Dr. I. Damaj 40

20
 Read Only Memory

„ Functions are implemented by storing the truth table

„ Other representations such as equations more convenient

„ Generation of programming information from equations usually

done by software

„ Text Example 4-10 Issue

„ Two outputs are generated outside of the ROM
„ In the implementation of the system, these two functions are
“hardwired” and even if the ROM is reprogrammable or
removable, cannot be corrected or updated

Dr. I. Damaj 41

Using Read-Only Memories

Dr. I. Damaj 42

21
 Example:
Square of a 3-bit binary input

„ Text Example 4-10 Issue

„ Two outputs are generated outside of the ROM
„ In the implementation of the system, these two functions are “hardwired”
and even if the ROM is reprogrammable or removable, cannot be
corrected or updated
Dr. I. Damaj 43

Programmable Array Logic

„ There is no sharing of AND gates as in the ROM and PLA

„ Design requires fitting functions within the limited number of

ANDs per OR gate

„ Single function optimization is the first step to fitting

„ Otherwise, if the number of terms in a function is greater than

the number of ANDs per OR gate, then factoring is necessary

Dr. I. Damaj 44

22
Programmable Array Logic Example
„ Equations:
„ F1 = AB’C’ +A’BC’ +A’B’C + ABC
„ F2 = AB + BC + AC

AND Inputs
„ F1 must be Product
factored term A B C D W Outputs
since four
terms 1 0 0 1 — —
2 1 1 1 — — W = A’B’C + ABC
3 — — — — —
„ Factor out
4 1 0 0 — —
last two F1 = X = AB’C’+A’BC’+W
5 0 1 0 — —
terms as W 6 — — — — 1
7 1 1 — — —
F2 = Y = AB + BC +AC
8 — 1 1 — —
9 1 — 1 — —
10 — — — — —
11 — — — — —
Dr. I. Damaj 12 — — — — — 45

Programmable Array Logic Example AND gates inputs

Product A A B B C C D D W W
term
1

2 W

All fuses intact

4 (always 5 0)

5 F1

8 F2

10

11

12

Dr. I. Damaj D
X Fuse intact 46
1 Fuse blown

A A B B C C D D W W

23
Another Example
W(A,B,C,D) = Σm(2,12,13)
X(A,B,C,D) = Σm(7,8,9,10,11,12,13,14,15)
Y(A,B,C,D) = Σm(0,2,3,4,5,6,7,8,10,11,15)
Z(A,B,C,D) = Σm(1,2,8,12,13)

Dr. I. Damaj 47

Dr. I. Damaj 48

24
 Programmable Logic Array

„ The set of functions to be implemented must fit the available number of

product terms

„ The number of literals per term is less important in fitting

„ The best approach to fitting is multiple-output, two-level optimization (which

has not been discussed)

„ Since output inversion is available, terms can implement either a function or

its complement

„ For small circuits, K-maps can be used to visualize product term sharing and
use of complements

„ For larger circuits, software is used to do the optimization including use of

complemented functions
Dr. I. Damaj 49

Programmable Logic Array

F1 = AB + AC + ABC
F2 = AC + BC
Dr. I. Damaj 50

25
 Using Programmable Logic Arrays

Homework
Example 4 - 11

F1 = AB + AC + ABC
F2 = AC + BC
Dr. I. Damaj 51

Lookup Tables
„ Lookup tables are used for implementing logic in Field-Programmable
Gate Arrays (FPGAs) and Complex Logic Devices (CPLDs)

„ Lookup tables are typically small, often with four inputs, one output, and
16 entries

„ Since lookup tables store truth tables, it is possible to implement any 4-

input function

„ Thus, the design problem is how to optimally decompose a set of given

functions into a set of 4-input two- level functions.

„ We will illustrate this by a manual attempt

Dr. I. Damaj 52

26
 Lookup Table Example
„ Equations to be implemented:
F1(A,B,C,D,E) = A D E + B D E + C D E
F2(A,B,D,E,F) = A E D + B D E + F D E

„ Extract 4-input function:

F3(A,B,D,E) = A D E + B D E
F1(C,D,E,F3) = F3 + C D E
F2(D,E,F,F3) = F3 + F D E

„ The cost of the solution is 3 lookup tables

Dr. I. Damaj 53

Introduction to VHDL

Dr. I. Damaj 54

27
 Overview
„ Part 1 - Basics and Constructs
„ VHDL basics
„ Notation
„ Types & constructs
„ Signals
„ Entities and architectures
„ Libraries and packages
„ Structural VHDL Example
„ VHDL Operators
„ Concurrent VHDL Examples
„ Part 2 - Behavioral and Hierarchical Description
„ Part 3 - Finite State Machines
„ Part 4 - Registers and Counters
„ Part 5 - Algorithmic State Machine Example: Binary Multiplier

Dr. I. Damaj 55

VHDL Notation - 1
„ VHDL is:
„ Case insensitive
„ Based on the programming language ADA
„ Strongly-typed language
„ Comments
-- [end of line]

„ List separator: ,
„ Statement terminator: ;

Dr. I. Damaj 56

28
 VHDL Notation - 2
„ Types and values
„ Determined by use of packages (discussed later) that define various types
and type conversions

„ IEEE 1076 predefined types:

„ type bit has two values 0 and 1
„ type bit_vector is an array of bits with integers as indices
„ type integer has values over a specified range of integers
„ type boolean is (TRUE, FALSE)

„ IEEE 1164 predefined types:

„ type std_ulogic has nine values: 'U', -- Uninitialized, 'X', --
Forcing Unknown, '0', -- Forcing 0, '1', -- Forcing 1, 'Z', -- High Impedance, 'W', --
Weak Unknown, 'L', -- Weak 0, 'H', -- Weak 1, '-' -- Don't care.
„ type std_ulogic_vector is an array of bits with natural (non-negative)
numbers as the indices
„ subtype std_logic is std_ulogic with definitions for multiple signals
applied to a single wire
„ subtype X01Z is std_logic with the range X, 0, 1, Z

Dr. I. Damaj 57

VHDL Notation - 3
„ More on types
„ Most frequently used type: std_logic
„ Provides values needed for simulation, notably X and

„ Frequently used type: integer

„ Due to strong typing, essential for arithmetic

operations
„ Requires additional packages to be used to perform

type conversion between std_logic and integer

Dr. I. Damaj 58

29
 VHDL Notation - 4
„ Constants
„ Binary
„ Single bit: '0', '1'
„ Multiple bit: B"110001", B"11_0001" (underline
permitted for readability)
„ Other bases
„ Octal O"61", O"6_1"
„ Hex X"31", X"3_1"
„ Decimal 49
„ Real 49E+1
Dr. I. Damaj 59

VHDL Notation - 5
„ Identifiers
„ Examples: A, B1, abc, run, stop, c_in
„ Keywords
„ Words reserved for special meanings
„ Cannot be used as identifiers
„ Examples: entity, architecture, and, if
„ Shown here in color
„ Shown in text in bold

Dr. I. Damaj 60

30
 VHDL Constructs
„ Structural:
„ Describes interconnections of components (entities)
„ Analogous to logic diagrams or netlists
„ Concurrent VHDL or Dataflow:
„ Consists of a collection of statements and processes that
execute concurrently
„ Sequential VHDL:
„ Consists of the sequences of statements within processes
„ Logic described may be combinational or sequential

Dr. I. Damaj 61

Signal Declaration
„ Signals can be viewed as "wires"
„ Signals are concurrent and sequential objects
„ A port declaration is a signal declaration with in or out added
„ Examples:
signal a, b: std_logic;
signal widget: std_logic_vector(0 to 7);
-- 0 is MSB and 7 is LSB
signal c: std_logic_vector(2 downto 0);
-- 2 is MSB and 0 is LSB

port (DATA: in std_logic_vector(15 downto 0));

port (NA: out std_logic);

Dr. I. Damaj 62

31
 Entities and Architectures
„ entity
„ The primary hardware abstraction in VHDL
„ Provides: the entity name, the inputs and outputs
„ Analogous to a symbol in a block diagram

„ architecture
„ Specifies the relationships between the inputs and outputs of a
design entity
„ May be a mixture of structural, concurrent and sequential VHDL.

„ A given entity may have multiple, different architectures.

„ Examples of entities and architectures follow.

Dr. I. Damaj 63

Libraries and Packages

„ A library typically contains VHDL code or compiled VHDL code

„ A package consists of compiled VHDL code for multiple entities and associated
architectures

„ A package is stored in a library

„ Example: package func_prims is stored in library lcdf_vhdl

„ func_prims provides compiled code for the following delay-free gates: and2, …,
and5, or2, … or5, nand2, …, nand5, nor2, …, nor5, not, xor2, and xnor2 in
which integers 2 through 5 specify the number of gate inputs.

„ Generation of the lcdf_vhdl library and the func_prims package:

„ Generate a new library named lcdf_vhdl.
„ Using the lcdf_vhdl library as the "work" library, compile the file
func_prims.vhd (available from the VHDL web page) that contains the
component, entity and architecture descriptions for the package.

Dr. I. Damaj 64

32
 First Example to Illustrate Entities,
Architectures and Constructs
„ IC7283 - a 1-bit adder from a commercial IC

• C1

B0 •
A0 • • •

S0
• • •

C0 • • •
Dr. I. Damaj 65

A Structural VHDL Example

library IEEE, lcdf_vhdl; „ Instantiation of two packages from two libraries.

Applies only to the following entity.
use IEEE.std_logic_1164.all,
lcdf_vhdl.func_prims.all;

entity IC7283 is „ Declaration of entity IC7283

port (A0,B0,C0: in std_logic; „ Declaration of 3 inputs and 2 outputs of type
std_logic.
C1,S0: out std_logic);
„ End of entity declaration
end IC7283;

architecture structure of „ Declaration of architecture named structure for

entity IC7283
IC7283 is
component NOT1 „ Declarations of the gate components to be used
frompackage func_prims in library lcdf_vhdl
port(in1: in std_logic;
out1: out std_logic)
end component;
component NAND2
port(in1,in2: in std_logic;
out1: out std_logic);
end component;
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A Structural VHDL Example (continued)
component NOR2
port(in1,in2: in std_logic;
out1: out std_logic);
end component;

component AND2
port(in1,in2: in std_logic;
out1: out std_logic);
end component;

component XOR2
port(in1,in2: in std_logic; „ Declarations of 7 signals for use in
out1: out std_logic); interconnecting the gates
end component;

signal N1,N2,N3,N4,N5,N6,N7:
std_logic;
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A Structural VHDL Example (continued)

begin ƒ Beginning of the body of the architecture.

g0: NOT1 port map (C0,N3);
g1: NOT1 port map (N2,N5); ƒ There is an entry for each gate:
g2: NOT1 port map (N3,N6); gate_identifier:
g3: NAND2 port map (A0,B0,N1);
ƒ gate_name keywords port map signal list:
g4: NOR2 port map (A0,B0,N2); (input, output) or (input1, input2, output)
g5: NOR2 port map (N2,N4,C1);
g6: AND2 port map (N1,N3,N4);
g7: AND2 port map (N1,N5,N7);
g8: XOR2 port map (N6,N7,S0);

end structure;
ƒ End of architecture and description

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 VHDL Operators

„ Logical: and, or, nand, nor, xor, xnor, not

„ Relational: =, /=, <, <=, >, >=
„ Shift: sll, srl, sla, sra, rol, ror
„ Form is sdt - s is for shift, d is direction (d = l is for left, d = r is for right,
and t is type (t = l is for logical, and t = r is for rotate).
„ Adding +, -, &
„ & is concatenation which permits one-dimensional operands to be place
end-to-end to form a combined operand.
„ Example: For C_in and A(3:0), C_in & A is equivalent to a 5-bit register
with C_in as the MSB and A(0) as the LSB.
„ Sign +, -
„ Multiplying: * (multiply), /(divide), mod (modulus), rem (remainder)
„ Miscellaneous: abs (absolute value), ** (exponentiation)

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Concurrent VHDL

„ Signal assignment
„ Uses signal assignment operator <=
„ A signal is assigned its value after a delay, whether real or
a delta time, an infinitesimal interval required in VHDL
simulator implementations
„ Examples:
„ z <= a or b; --z assigned after an
--infinitesimal delta time
„ z <= a nand b after 10 ns; -- z assigned
-- after inertial delay of 10 ns
„ widget <= transport ("00" & a & b) after 10 ns;
-- assigned after transport delay of 10 ns;
-- & is the concatenation operator.
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Concurrent VHDL Example Using
Boolean Equations
„ The entity is the same as for the structural VHDL example

architecture dataflow_1 of IC7283 is

signal N1,N2: std_logic;
begin -- The assignment statements are
-- Boolean equations.
N1 <= not(A0 and B0);
N2 <= not(A0 or B0);
C1 <= not((N1 and (not C0)) or N2);
S0 <= ((not N2) and N1) xor (not(not C0));
end dataflow_1;

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Concurrent VHDL Example Using

"with select"
library IEEE, lcdf_vhdl;
use IEEE.std_logic_1164.all;

entity IC7283_ws is
port (Z: in std_logic_vector(2 downto 0);
CS: out std_logic_vector(1 downto 0));
end IC7283_ws;

architecture dataflow_2 of IC7283_ws is

begin

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 Concurrent VHDL Example Using "with select"

with Z select Defines Z as the

CS <= "00" when "000", conditioning signal.
"01" when "001",
"01" when "010", Forms truth table
"10" when "011", with inputs on the
"01" when "100", right and outputs on
"10" when "101", the left.
"10" when "110",
"11" when "111",
"XX" when Assigns XX to CS for
others; the other std_logic
end dataflow_2; triples on Z

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Second Example to Illustrate Entities,

Architectures and Constructs

„ Priority Encoder

Inputs Outputs

D4 D3 D2 D1 D0 A2 A1 A0 V
0 0 0 0 0 X X X 0
0 0 0 0 1 0 0 0 1
0 0 0 1 X 0 0 1 1
0 0 1 X X 0 1 0 1
0 1 X X X 0 1 1 1
1 X X X X 1 0 0 1

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 Concurrent VHDL Example Using "when else"

library IEEE
use IEEE.std_logic_1164.all;
entity priority_encoder_we is
port (D: in std_logic_vector (4 downto 0);
A: out std_logic_vector (2 downto 0);
V: out std_logic);
end priority_encoder_we;
architecture dataflow_3 of priority_encoder_we is
begin
A <= "100" when D(4) = '1' -- Can customize condition
else "011" when D(4 downto 3) = "01" -- on each
else "010" when D(4 downto 2) = "001" -- line.
else "001" when D(4 downto 1) = "0001"
else "000" when D = "00001"
else "XXX";
V <= not(D = "00000");
end dataflow_3;
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Concurrent "when else" vs. "with select"

„ with select
„ Has simple form with
„ condition signal stated only once

„ only one word per line, otherwise

„ Ideal for implementing binary (0,1) truth tables

„ when else
„ Has more complex form, but
„ Able to implement much more complex decision functions
„ condensed truth tables with 0, 1, X entries in rows

„ situations with limited cases of multiple condition signals

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Problems
„ 4.10, 4.11, 4.12, 4.21, 4.23, 4.24, 4.25, 4.27,
4.30, 4.31, 4.32, 4.33, 4.34, 4.35.

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