CHAPTER 3 CMOS Circuit Characterization

NonIdeal behaviors are because of associated resistance and capacitance with the MOS while functioning. These resistances and capacitances are responsible for propagation delay and power consumption, which is the major concern for digital designer.

Resistor Estimation
As the output of an inverter swings from HIGH to LOW or vice versa, the nMOS and the pMOS devices (respectively) might travel through various regions of operation, namely linear, saturation and velocity saturation. Each of these regions exhibit a different ON resistance for the MOS device. A decent approximation to the associated Req can be got by averaging the resistances that the device passes through during the output swing.

Capacitor Estimation
The MOSFET transistors exhibit a number of parasitic capacitance which must be accounted for in circuit design: gate-to-source capacitance (CGS), gateto-drain capacitance (CGD), gate-tobulk capacitance (CGB), source-to-bulk capacitance (CSB) and drain to bulk capacitance (CDB). In this work, our interest will be the switching region of the transistors and all the capacitances will be considered, with the exception of CGB. Although these capacitances are a nonlinear function of the voltage, the general approach is to assume them as a linear, time-invariant element. Given some technology parameters and the size the transistor (W/L), a value for each of these parasite capacitances can be computed.

Here are some equations

Modeling inverter input and output capacitance The CMOS inverter presents two externals nodes. In this case, equivalent capacitances at the input x. Cin x, and output y, Cout y, nodes can be simply computed using:

Propagation Delay
The delay of the CMOS inverter is a performance metric for how fast the circuit is. This delay is dependent upon the RC charging or discharging of the load capacitor by the pMOS or nMOS devices respectively and provides a quantitative feel for the time that is taken by the output of the inverter to completely respond to a change at its input.

Some definitions need to know as a designer Tr( Rise Time) : Time taken to rise from 10% to 90% Tf( Fall Time) : Time taken to fall from 90% to 10% Trf( Edge Rate) : (tr + tf )/2 tpHL( H-to-L propagation delay) : Time taken to fallfrom VOH to 50% tpLH( L-to-H propagation delay) : Time taken to rise from 50% to VOL tp( Propagation Delay) : (tpHL + tpLH)/2

Graphical Representation

Now that we can estimate the capacitance and resistance associated with the charging/discharing of the output of an inverter, we can also estimate any of the defined delays by viewing the output as a first-order RC network. Hence, the rise and fall times are estimated as follows:

Inverter Sizing

The goal is to minimise the delay of an inverter chain which is representative of a typical digital system. The input cap is denoted by Cg1 and the final load cap is CL. The delay of the j-th inverter stage is given by

Hence, the total delay through the system is

The minimum delay is found by equating N-1 partial derivatives to 0 and obtaining a set of constraints

The optimum size of each inverter is the geometric mean of its neighbours sizes This means that each inverter has a scale-up factor of f with respect to the preceding stage, the same effective fan-out and hence the same delay. Denoting the CL/Cg1 ratio by F, we have

The minimum delay is achieved as

F is called the effective fan-out and f , the stage ratio.

Optimizing Number of Stages

An optimum value has to be chosen for the number of stages N. If N is too large, Ntp0 becomes dominant and the intrinsic delay of the stages dominates. If N is too small, the effective fan-out becomes excessively large. Differentiating the delay expression with respect to the number of stages and equating to 0, we attain

This equation has to be solved numerically and gives an optimum value of 4 for f .

Power Consumption
The graph below shows the trend in increase in power consumption with increase in frequency and transistor density.

This shows that power consumption is increasing tremendously and the heat generated by this much consumption can be too high for chip to even sustain. This means either we cannot increase density or we cannot increase frequency. Designers have chosen former one and thats why we have seen a saturation in frequency of operations of digital chips.

Inverter Power Components

Power has three components Static power: when input isnt switching Dynamic capacitive power: due to charging and discharging of load capacitance Dynamic short-circuit power: direct current from VDD to Gnd when both transistors are on

Static Power Consumption

Static current: in CMOS there is no static current as long as Vin < VTN or Vin > VDD +VTP Leakage current: determined by off transistor Influenced by transistor width, supply voltage, transistor threshold voltages

Dynamic Power Consumption

Dynamic power consumption is because of transition of 0 to 1 or vice versa from input to input. During transition charge accumulates at parasitic capacitances and thus leads to power dissipation. Figure below shows

Where CL is effective load capacitance and f is frequency of transitions from 0 to 1 or vice versa.

Short Circuit Power Dissipation

Finite slope of the input signal causes a direct current path between VDD and GND for a short period of time during switching when both the NMOS and PMOS transistors are conducting.

Total Power Consumption

Reducing Power Consumption

Few points to reduce power consumption Lower the voltage (Vdd)!Quadratic effect on dynamic power Reduce capacitance Short interconnect lengths Drive small gate load (small gates, small fan-out) Reduce frequency: Lower clock frequency Lower signal activity Fast rise/fall times on input signal

Reduce input capacitance Insert small buffers to clean up slow input signals before sending to large gate Reducing leakage current: Small transistors (leakage proportional to width)