Lab - 01

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Mehran University of Engineering & Technology Jamshoro Institute of Information and Communication Technologies M.E- Electronic Systems Engineering ( rd Term! "dvanced #$%" &ased 'esign Lab Experiment No. 1
Name: _____________________________________________________ Roll No: ______________ Score:_________________ Signature:__________________________________ Date:___________

Introduction to #$%"( )E*+S, &oard( *ilin- ISE & ./'0

$E1#21M")CE 2&JECTI.E3
"fter the successful com4letion of this la5( students 6ill 5e a5le to3 Understand the Basic Designing Flow For F !"# Become $amiliar with Ne%&s' Board ()ilin% S*artan +, F !"Become $amiliar with )ilin% .S, Design So$tware# !et basic /nowledge about 0ardware Descri*tion Languages#

0"& 1E7UI1EME)TS3
1 with 2indows ) 3'0045 6*erating S&stem# )ilin% .S, Design Suite 1'#+ So$tware installed#

'ISCUSSI2)3 #ield $rogramma5le %ate "rray (#$%"!3

"n F !" is a de7ice that consists o$ thousands or e7en millions o$ transistors connected to *er$orm logic $unctions# 8he& *er$orm $unctions $rom sim*le addition and subtraction to com*le% digital $iltering and error detection and correction# "ircra$t5 automobiles5 radar5 missiles5 and com*uters are 9ust some o$ the s&stems that use F !"s )ilin%5 "ltera5 are 9ust a $ew com*anies that manu$acture F !"s# ,7en though there are se7eral F !" manu$acturers5 the& all share the same basic architecture conce*t# .t consists o$ three basic ca*abilities: in*ut3out*ut (.36- inter$aces5 basic building bloc/s5 and interconnections# *ilin- S4artan E #$%" 8he Ne%&s' circuit board as Shown in Figure1#1 is a com*lete5 read&-to-use circuit de7elo*ment *lat$orm based on a )ilin% S*artan +, F !"# .ts onboard high-s*eed USB' *ort5 1:;b&tes o$ R"; and R6;5 and se7eral .36 de7ices and *orts ma/e it an ideal *lat$orm $or digital s&stems o$ all /inds5 including embedded *rocessor s&stems based on )ilin%<s ;icroBla=e# 8he USB' *ort *ro7ides board *ower and a *rogramming inter$ace5 so the Ne%&s' board can be used with a noteboo/ com*uter to create a trul& *ortable design station# 8he Ne%&s' brings leading technologies to a *lat$orm that an&one can use to gain digital design e%*erience# .t can host countless F !"-based digital s&stems5 and designs can easil& grow be&ond the board using an& or all o$ the $i7e e%*ansion connectors# Four 1'-*in eri*heral ;odule ( mod- connectors can accommodate u* to eight low-cost mods to add $eatures li/e motor control5 "3D and D3" con7ersion5 audio circuits5 and a host o$ sensor and actuator inter$aces# "ll user accessible

$o6er Lab - 01 Jac?

.%" $ort

$mod 4o6er $mod Connector $o6er -' source ;um4er S6itch signals on the Ne%&s' board are ,SD and short-circuit *rotected5 ensuring a long o*erating li$e in an& en7ironment# 8he Ne%&s' board is $ull& com*atible with all 7ersions o$ the )ilin% .S, JT"% /eader tools5 including the $ree 2eb ac/# Now an&one can build real digital s&stems $or less than the *rice o$ a te%tboo/# 1eset &utton

$o6er select ;um4er

Mode select Jum4er

2scillator Soc?et Serial $ort

<=M/> 2scillator

$latform #lash

'one 0E' E-4ansion connector 8 0E's 8 Slide S6itches 9 4ush5uttons : Segment 'is4lay E-4ansion 'isconnect ;um4er

US& Connector

$S@, $ort

Cellular 1"M

(S'1"M!

S4artan E #$%"

Fig 1#1: N,)>S' S4artan E F !" Board3?it

#$%" 'esign #lo63

8he $ollowing diagram (Figure1#'- shows the basic ste*s o$ designing an F !" with )ilin% .S, Design Suite 1'#+ So$tware5 /nown as 0DL design $low#

Lab - 01

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Beha7ioral Simulation

Simulation with .S; simulator

Functional simulation

Design ,ntr& C0DL code

Design S&nthesis

Design .m*lementation

h&sical Reali=ation

Fig 1#': F !" Design $low diagram

A. 'esign Entry3 8he design entr& is the *rocess o$ entering Digital logic e%*ression or the Beha7ioral e%*ression o$ desired statement or desired *rocess# 2ith the ad7ance in technologies so man& newer methods o$ designing entr& are used $or sim*licit& and $aster designing# )ilin% .S, su**orts man& di$$erent 7arieties o$ design entr&5 o$ which some are listed as: State machines Flow charts Bloc/ diagram3 inter$ace based design (.BD 0ardware descri*tion languages (0DL- etc# '# Simulation3 Simulation is the *rocess o$ testing the logical or *rocessing $unctionalit& o$ designed logic# Se7eral /inds o$ So$tware and hardware 8ools to *ro7ide this $unctionalit&# 2ith )ilin% .Sim Simulator &ou can simulate &our design b& writing @8est benchesA and3or b& assigning ;anual wa7e $lows to in*uts and chec/ $unctionalit& o$ out*uts a$ter simulation# . Synthesi>e3 S&nthesis is a *rocess b& which an abstract $orm o$ desired circuit beha7ior (t&*icall& register trans$er le7el (R8L-- is turned into a design im*lementation in terms o$ logic gates# S&nthesis is one as*ect o$ electronic design automation# 2ith )ilin% .S, Design Suite user can con7ert the 0DL (hardware descri*tion language- or other /inds o$ designs created with Design entr& tool into the !ate le7el design $or an& F !" $amil&# 9. Im4lementation & $hysical 1eali>ation 8o *h&sicall& im*lement the design in a 1 LD or F !" chi*5 a de7elo*ment /it is necessar&# 8he de7elo*ment /it must be connected to a 1 running .S, in order $or the chi* to be *rogrammed#

*ilin- ISE 'esign Soft6are3 Introduction

8he .S,B so$tware controls all as*ects o$ the design $low# 8hrough the ro9ect Na7igator inter$ace5 &ou can access all o$ the design entr& and design im*lementation tools# >ou can also access the $iles and documents associated with &our *ro9ect#

Lab - 01

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$ro;ect )avigator Interface3

B& de$ault5 the ro9ect Na7igator inter$ace is di7ided into $our *anel sub windows5 as seen in Figure 1#+# 6n the to* le$t are the Start5 Design5 Files5 and Libraries *anels5 which include dis*la& and access to the source $iles in the *ro9ect as well as access to running *rocesses $or the currentl& selected source# 8he Start *anel *ro7ides Euic/ access to o*ening *ro9ects as well as $reEuentl& access re$erence material5 documentation and tutorials# "t the bottom o$ the ro9ect Na7igator are the 1onsole5 ,rrors5 and 2arnings *anels5 which dis*la& status messages5 errors5 and warnings# 8o the right is a ;ulti document inter$ace (;D.- window re$erred to as the 2or/s*ace# 8he 2or/s*ace enables &ou to 7iew design re*orts5 te%t $iles5 schematics5 and simulation wa7e$orms# ,ach window can be resi=ed5 undoc/ed $rom ro9ect Na7igator5 mo7ed to a new location within the main ro9ect Na7igator window5 tiled5 la&ered5 or closed# 8he $ollowing $igure 1#+5 shows the ro9ect Na7igator inter$ace

1
A , 9 < C

'

Start *anel 'esign *anel #iles anel 0i5raries anel Errors and Barnings anel Bor?s4ace

Fig 1#+: $ro;ect )avigator For the simulation5 .S, incor*orates a )ilin% 7ersion o$ .S.; Simulator# 8his *ower$ul Simulator is ca*able o$ simulating $unctional C0DL be$ore s&nthesis5 or Simulating a$ter the .m*lementation *rocess $or timing 7eri$ication#

Lab - 01

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./'0
C0DL is a hardware descri*tion language# .t describes the beha7ior o$ an electronic circuit or s&stem5 $rom which the *h&sical circuit or s&stem can then be attained (im*lemented-# C0DL stands $or C0S.1 0ardware Descri*tion Language# C0S.1 is itsel$ an abbre7iation $or Cer& 0igh S*eed .ntegrated 1ircuits5 an initiati7e $unded b& the United States De*artment o$ De$ense in the 1GH0s that led to the creation o$ C0DL# .ts $irst 7ersion was C0DL H45 later u*graded to the so-called C0DL G+# C0DL was the original and $irst hardware descri*tion language to be standardi=ed b& the .nstitute o$ ,lectrical and ,lectronics ,ngineers5 through the .,,, 104: standard# "n additional standard5 the .,,, 11:D5 was later added to introduce a multi-7alued logic s&stem# 'esign Entry3 8he basic design entities are constructed in C0DL using three di$$erent t&*es o$ design units# L.BR"R> declarations: 1ontains a list o$ all libraries to be used in the design# For e%am*le: ieee5 std5 wor/5 etc# ,N8.8>: S*eci$ies the .36 *ins o$ the circuit# "R10.8,18UR,: 1ontains the C0DL code *ro*er5 which describes how the circuit should beha7e ($unction-# 8o declare a L.BR"R> (that is5 to ma/e it 7isible to the design- two lines o$ code are needed5 one containing the name o$ the librar&5 and the other a use clause5 as shown in the s&nta% below# LIBRARY library_name; USE library_name.package_name.package_parts ; "t least three *ac/ages5 $rom three di$$erent libraries5 are usuall& needed in a design: ieee#std_logic_11:D ($rom the ieee librar&-5 standard ($rom the std librar&-5 and wor/ (wor/ librar&-# Their declarations are as follo6s3 L.BR"R> ieeeI US, ieee#std_logic_11:D#allI L.BR"R> stdI US, std#standard#allI L.BR"R> wor/I US, wor/#allI -- " semi-colon (I- indicates -- the end o$ a statement or -- declaration5 while a double -- dash (--- indicates a comment#

ENTITY

Lab - 01 ENTITY entity_name IS P RT ! p"rt_name# signal_m"$e signal_type; p"rt_name# signal_m"$e signal_type; ...%; END entity_name;

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"n ,N8.8> is a list with s*eci$ications o$ all in*ut and out*ut *ins ( 6R8S- o$ the circuit# .ts s&nta% is shown below# 8he mode o$ the signal can be .N5 6U85 .N6U85 or BUFF,R# "s illustrated in Figure '#+5 .N and 6U8 are trul& unidirectional *ins5 while .N6U8 is bidirectional# BUFF,R5 6n the other hand5 is em*lo&ed when the out*ut signal must be used (read- internall&# Finall&5 the name o$ the entit& can be basicall& an& name5 e%ce*t C0DL reser7ed words# ,%am*le: Let us consider the N"ND gate ENTITY nan$_gate IS P RT !a/ b# IN BIT; 0# UT BIT%; EN. nan$_gate;

8he meaning o$ the ,N8.8> abo7e is the $ollowing: the circuit has three .36 *ins5 being two in*uts (a and b5 mode .N- and one out*ut (%5 mode 6U8-# "ll three signals are o$ t&*e B.8# 8he name chosen $or the entit& was nand_gate#

ARCHITECTURE
8he "R10.8,18UR, is a descri*tion o$ how the circuit should beha7e ($unction-# .ts s&nta% is the $ollowing: AR&'ITE&TURE arc(itect)re_name +$eclarati"ns, BE-IN !c"$e% EN. arc(itect)re_name; * entity_name IS

"s shown abo7e5 architecture has two *arts: a declarati7e *art (o*tional-5 where signals and constants (among others- are declared5 and the code *art ($rom B,!.N down-# Li/e in the case o$ an entit&5 the name o$ an architecture can be basicall& an& name (e%ce*t C0DL reser7ed words-5 including the same name as the entit&<s# ,%am*le: Let us consider the N"ND gate once again# AR&'ITE&TURE be(a1e 0 23 a NAN. b; EN. be(a1e; * nan$_gate IS

Lab - 01

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8he meaning o$ the "R10.8,18UR, abo7e is the $ollowing: the circuit must *er$orm the N"ND o*eration between the two in*ut signals (a5 b- and assign (JJKL<<- the result to

1evie6 7uestion3
;a/e a table de$ining o*erators used in C0DL#

#inal "ssignment 3
1# 2rite down the C0DL codes $or )6R5 )-N6R and N6R gates# '# 2rite down the C0DL codes $or the $ollowing e%*ressions# >L ("MB-#1 NL "BMB1MD