EXPT NO:10 DATE:6-9-2013

RANDOM ACCESS MEMORY

AIM: To design and simulate a 32*8 RAM

SOFTWARE USED: Model SIM, Xillin THEORY: Random-access memory (RAM ) is a form of computer data storage. A randomaccess device allows stored data to be accessed directly in any random order. In contrast, other data storage media such as hard Disk DVD and magnetic tapes, as well as early primary memory types such as drum memory, read and write data only in a predetermined order, consecutively, because of mechanical design limitations. Therefore the time to access a given data location varies significantly depending on its physical location. Today, random-access memory takes the form of integrated circuit. Strictly speaking, modern types of DRAM are not random access, as data is read in bursts, although the name DRAM / RAM has stuck. However, many types of SRAM, ROM, OTP, and NOR flash are still random access even in a strict sense. RAM is normally associated with volatile types of memory (such as DRAM memory modules), where its stored information is lost if the power is removed. Many other types of non-volatile memory are RAM as well, including most types of ROM and a type of flash memory called NOR-Flash. The three main forms of modern RAM are static RAM (SRAM), dynamic RAM (DRAM) and phase-change memory (PRAM). In SRAM, a bit of data is stored using the state of a flip-flop. This form of RAM is more expensive to produce, but is generally faster and requires less power than DRAM and, in modern computers, is often used as cache memory for the CPU. DRAM stores a bit of data using a transistor and capacitor pair, which together comprise a memory cell. The capacitor holds a high or low charge (1 or 0, respectively), and the transistor acts as a switch that lets the control circuitry on the chip read the capacitor's state of charge or change it. As this form of memory is less expensive to produce than static RAM, it is the predominant form of computer memory used in modern computers. PROGRAM:
library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL; entity ram0 is Port ( clk : in STD_LOGIC; rst : in STD_LOGIC; rw : in STD_LOGIC; add : in integer range 0 to 31 ; din : in STD_LOGIC_vector(7 downto 0); dout : out STD_LOGIC_vector(7 downto 0)); end ram0; architecture Behavioral of ram0 is type mem is array (0 to 31) of std_logic_vector (7 downto 0); signal ram:mem; begin process(clk,rst,rw) begin if(rst='1')then for i in 0 to 31 loop ram(i)<="00000000"; end loop; dout<="00000000"; elsif(clk'event and clk='1')then if(rw='0')then ram(add)<=din; else dout<=ram(add);

end if; end if; end process; end Behavioral;

PROCEDURE: 1. Open a new project from Xilinx ISE6,a project navigation software tool. 2.Select a source file name as VHDL module and define the VHDL sources respectively the input and output ports. 3.Enter the program and save the file. 4.Check the syntax option from synthesis to know the error. 5.Go for the synthesize XST to view TTL schematic report(new list). 6. Launch Modelsim simulator from design entry utilites and enter the values of input ports. 7.Run the program to view the waveform representation of the output. 8.For implementation of the design,we should configure the design by connecting the fabrication kit to the computer. RESULT: Designed and simulated a 32*8 RAM