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Operating principle of Phase Locked Loops

Phase Locked Loop The block diagram showing operating principle of PLLis given in figure. As illustrated in this fig, the PLL consists of a phase detector, a low-pass filter and a voltage controlled oscillator. YOU MAY ALSO REFER: PHASE LOCKED LOOP ICs, DESIGN A PLL, PLL OPERATION, and PLL FM DEMODUATOR CIRCUIT

Phase Detector
A phase detector is basically a comparator that compares the input frequency fin with feedback frequency fout. The phase detector receives two digital signals, one from the input, the other feedback from the output. The loop is locked when these two signals are of the same frequency and have a fixed phase difference (A locked PLL is analogous to an op-amp not being saturated). The output of a phase detector is a dc voltage and therefore is often referred to as the error voltage, Ve. DC output voltage becomes maximum when the phase difference between the two frequencies fin and fout is radians or 180. Without input signal, the error voltage Ve is equal to zero and the VCO operates at a set frequency fr which is also called free-running frequency of the VCO. When the input signal frequency is the same as that from the VCO to the PC, the voltage, Vd, taken as output is the value required to hold the VCO in lock with the input signal. If the two input pulses to the PC are of exactly the same frequency and phase, the output of the PC is zero, otherwise there I will be an output proportional to their phase difference.

Low-pass filter
Low-pass filter is used to remove high frequency components and noise from the output of the phase detector. It affects the dynamic characteristics of the PLL including bandwidth, capture and lock ranges and transient response. The low-pass filter accepts the output from the phase detector, removes the high frequency noise and produces a dc level.

Voltage Controlled Oscillator (VCO)


Voltage-controlled oscillator generates frequency controlled by input voltage. The dc level output of a low-pass filter is applied as control signal to the voltage-controlled oscillator (VCO). The output frequency of the VCO is directly proportional to the input dc level. The VCO frequency is adjusted till it becomes equal to the frequency of the input signal. During this adjustment, PLL goes through three stages-free running, capture and phase lock. Best operation is obtained if the centre frequency of the VCO is set with the dc bias voltage midway in its linear

operating range. The amplifier allows this adjustment in dc voltage from that obtained as output of the filter circuit. When the loop is in lock, the two signals to the PC are necessarily of the same frequency although not necessarily in phase. A fixed phase difference between the two signals to the comparator results in a fixed dc voltage to the VCO. Variation in the input signal frequency then causes variation in the dc voltage to the VCO. Within a capture-and-Iock frequency range, the dc voltage will drive the VCO frequency to match that of the input. While the loop is trying to achieve lock, the output of the PC contains frequency components at the sum and difference of the signals compared. A low-pass filter passes only the lowerfrequency component of the signal so that the loop can obtain lock between input and VCO signals. Owing to the limited operating range of the VCO and the feedback connection of the PLL circuit, there are two important frequency bands specified for a PLL. The capture range of a PLL is the range of frequencies centred about the VCO free-running frequency fr, over which the output signal frequency of the VCO can acquire lock with the input signal frequency. Once the PLL has achieved capture, it can maintain lock with the input signal over a somewhat wider frequency range called the lock range.

MONOLITHIC PHASE-LOCKED LOOP (PLL) ICS


Although the evolution of the PLL began in the early 1930s but its cost outweighted its advantage in the beginning. Today the PLL is even available as a single package, typical examples of which are the Signetics SE/NE series such as 560, 561, 562, 564, 565 and 567. They only differ in operating frequency range, power requirements, and frequency and bandwidth (BW) adjustment ranges. SE/NE 565 is the most widely employed IC of the series. The device is available as a 14-pin DIP package and as a 10-pin metal can package. Its important electrical characteristics are given below:

PLL PIN IDENTIFICATION

Characteristics of SE/NE 565 PLL IC


1. Operating frequency range : 0.001 Hz to 500 kHz. 2. Operating voltage range : 6 to 12 V.

3. 4. 5. 6. 7. 8. 9.

Input impedance : 10 k Q typically. Output sink current :1mA typically. Output source current : 10 m A typically. Drift in VCO centre frequency with temperature : 300 ppm/ C typically. Drift in VCO centre frequency with supply voltage : 1.5 %/V maximum. Input level required for tracking : 10 mVrms minimum to 3 V peak-to-peak maximum. Bandwidth adjustment range : < 1 to > 60 %.

NE-SE 565 IC The block diagram and connection diagram of the SE/NE 565 IC is shown in figure. As shown in the figure, the PLL system consists of a phase detector or comparator (PC), a voltagecontrolled oscillator (VCO), an amplifier and R-C combination forming low-pass filter circuit. The input signals are fed to the phase detector through pins 2 and 3 in differential mode. The input signals can be direct-coupled provided that the dc level at these two pins is made same and dc resistances seen from pins 2 and 3 are equal. By shorting pins 4 and 5 output of VCO is supplied back to the phase comparator (PC). The output of PC is ijiternally connected to amplifier, the output of which is available at pins 6 and 7 through a resistor of 3.6 k Q connected internally. A capacitor C2 connected between pins 7 and 10 forms a low-pass filter with 3.6 k Q resistor. The filter capacitor C2 should be large enough so as to eliminate the variations in demodulated output and stabilize the VCO frequency. Voltage available at pin 7 is connected internally to VCO as a control signal. At pin 6 a reference voltage nominally equal to voltage at pin 7 is available allowing both the differential stages to be biased. Pins 1 and 10 are supply pins. The centre frequency of the PLL is determined by the free-running frequency of the VCO which is given as Fout = 1.2/4R1C1 Hertz where R1 and C1 are external resistor and capacitor connected to pins 8 and 9 respectively, as illustrated in figure. The free-running frequency fout of the VCO is adjusted, externally with Rt and C1, to be at the centre of the input frequency range. Resistor R1 must have a value between 2 and 20 kilo ohm. Capacitor C1 may have any value. The 565 PLL can lock to and track an input signal typically 60 % bandwidth with respect to fout as the centre frequency. The lock-range of PLL is given as

fL = 8fOUT / V Hertz where fout is free-running frequency of VCO in Hz and V = (+ V) (- V) and capture range is given as fC = [fL / 2 (3.6) (10)3 C2]1/2 The lock range usually increases with an increase in input voltage but falls with an increase in supply voltages. Design for determining the Free running frequency,Lock range

and Capture range of a PLL


In the earlier post about Phase Locked Loop IC we had discussed about the free-running frequency (fOUT), lock range (fL) and capture range (fc) equations. Here let us discuss about the appropriate values that can be given for fOUT, fL, and fc. Given below is the circuit of an NE/SE 565 IC or the PLL IC. We assume values for each parameter. +V = 12 Volt -V = -12 Volt R1 = 15 Kilo Ohms C1 = 0.01 Micro Farads C2 = 10 Micro Farads Free-running Frequency = 1.2 / 4R1 C1= 1.2 / (4*15*103* 0.01* 10-6) = 2 Kilo Hertz Lock Range, fL = 8fOUT / V Hertz = 8*2*103/ +12 (-12) = 2/3 Kilo Hertz Capture Range, fC = [fL / 2 (3.6) (10)3 C2]1/2 = [fL / 2*3.6*103*C2]1/2 = 54.29 Hertz From the above calculations, the relationship between free-running frequency, lock range and capture range are illustrated in the figure given below.

Block Diagram of NE SE565 PLL

Design of PLL

How a PLL works ?

Operation of PLL Consider VCO operating without input signal at free-running frequency fr and input signal of frequency fIN increasing from zero is applied to the PC. If the input frequency is less than f IN1, then the error voltage Ve is zero as illustrated in figure and VCO operates at a frequency fr. When the input signal frequency fIN reaches a frequency fin1 (the lower edge of the capture range), then the output or error voltage Ve jumps from zero to some negative voltage with beat notes of frequency (difference between input signal frequency and actual VCO output signal frequency;

fIN fOUT. The error voltage Vg is then filtered, amplified and amplified voltage Vd is applied to the control terminals of the VCO. The instantaneous frequency of VCO decreases because fOUT falls for negative values of Vd and increases for positive values of Vrf. At some instant of time, the decreasing frequency of the VCO equals fIN l (lower edge of the capture range), then lock results-in, and the output signal frequency of the VCO may be equal to the input signal frequency (that is,fOUT = fIN). The VCO frequency locks with input signal frequency up to fIN2 (the upper end of the lock range). If the input signal frequency exceeds fIN2 then error voltage Vg will fall to zero and the VCO will operate at the free running frequency fr, as illustrated in figure. If the input signal frequency is now slowly swept back and it attains the value of fd1 then the loop (VCO frequency) locks with the input signal frequency, causing a positive jump of the error voltage Ve. So the VCO output frequency increases from fr continuously till fOUT becomes equal to fIN. The VCO frequency fOUT locks with the input signal frequency fIN upto fd2 (the lower edge of the lock range) as shown in figure by dotted lines. Now if the frequency of the input signal falls below fd2, then the error voltage Ve will fall to zero and the VCO will operate at the free running frequency.

PLL Applications
1. Frequency Multiplication or Frequency Synthesis

NE 565 Frequency Multiplier The block diagram of a frequency muliplier (or synthesizer) is shown in figure. In this circuit, a frequency divider is inserted between the output of the VCO and the phase comparator (PC) so that the loop signal to the PC is at frequency fOUT while the output of VCO is N fOUT. This output is a multiple of the input frequency as long as the loop is in lock. The desired amount of multiplication can be obtained by selecting a proper divide- by N network where N is an integer. Figure shows this function performed by a 7490 configured as a divide-by-4 circuit.

In this case the input Vin at frequency /in is compared with the output frequency fOUT at pin 5. An output at N fOUT (4 fOUT in this case) is connected through an inverter circuit to give an input at pin 14 of the 7490, which varies between 0 and + 5 V. Using the output at pin 9, which is onefourth of that at the input to the 7490, the signal at pin 4 of the PLL is four times the input frequency as long as the loop remains in lock. Since the VCO can be adjusted over a limited range from its centre frequency, it may become necessary to change the VCO frequency whenever the divider value is changed. For verification of the circuit operation, one must determine the input frequency range and then adjust the free running fOUT of the VCO by means of R1 and C1 so that the output frequency of the 7490 divider is midway within the predetermined input frequency range. The output of VCO should now be equal to 4 fin.

PLL Application Frequency Demodulation


Using NE-SE 565 IC

fm detector Frequency demodulation or detection can be obtained directly by using the PLL circuit. When the centre frequency of the PLL is selected or designed at the FM carrier frequency, the filtered or output voltage in the circuit shown in figure, is obviously the desired demodulated voltage, that varies in magnitude in proportion to the signal frequency. The PLL circuit thus can be operated as complete IF strip, limiter, and detector as employed in FM receivers. The 565, very popular PLL unit, containing a phase comparator PC, amplifier, and VCO, is shown in figure. PC, amplifier and VCO are only partially connected internally. An external resistor R1 and capacitor C1 are for setting free-running or centre frequency of VCO and another external capacitor C2 is for setting low-pass filter pass
band. VCO output is connected back as the input to the PC so as to close the PLL loop. Power supplies used are two (V+ and V-).

PLL Application FSK (Frequency Shift Keying) Demodulator


FSK demodulator using NE-SE 565 IC

fsk demodulator A very useful application of the 565 PLL is as a FSK demodulator. In the 565 PLL the frequency shift is usually accomplished by driving a VCO with the binary data signal so that the two resulting frequencies correspond to the logic 0 and logic 1 states of the binary data signal. The frequencies corresponding to logic 1 and logic 0 states are commonly called the mark and space frequencies. Several standards are used to set the mark and space frequencies. An FSK signal demodulator can be built as illustrated in figure. The demodulator receives a signal at one of the two distinct carrier frequencies, 1,270 Hz or 1,070 Hz representing the RS232 C logic levels of mark (- 5 V) or space (+ 14 V), respectively. Capacitance coupling is used at the input to remove a dc level. As the signal appears at the input of 565 PLL, the PLL locks to the input frequency and tracks it between the two possible frequencies with a corresponding dc shift at the output. Resistor R1 and capacitor C1 determine the free-running frequency of the VCO. Capacitor C2 is a loop filter capacitor that establishes the dynamic characteristics of the demodulator. Capacitor C2 is chosen smaller than usual one to eliminate overshoot on the output pulse. A three-stage RC ladder filter is employed for removing the sum frequency component from the output. The VCO frequency is adjusted with R1 so that the dc voltage level at the output (pin 7) is the same as that at pin 6. An input at frequency 1,070 Hz drives the demodulator output voltage to a more positive voltage level, driving the digital output to the high level (space or + 14 V). An input at 1,270 Hz correspondingly drives the 565 dc output less positive with the digital output, which then drops to the low level (mark or 5 V).