E&C-ENGR 227 Logic Design Laboratory Manual

By

Prof. Ghulam M. Chaudhry

Department of Computer Science Electrical Engineering School of Computing and Engineering University of Missouri-Kansas City
Revised 19-8-2013

Logic Design Lab Grading Policy

INSTRUCTOR: TEXT: REFERENCES: Dr. G. M. Chaudhry Lab Manual Digital Design, 3rd Edition, by M. Morris Mano, Prentice Hall, 2002. Digital Logic Design Principles by N. Balabanian and B. Carlson, John Wiley & Sons, Inc. 2001. TTL Data Book, by Texas Instrument, 1988. = = = = 30 % 30 % 20 % Midterm 20 % Final

1) 2) 3)

GRADING:

Lab Reports: Demonstration: Examinations: i)

ii)

UMKC Academic Dishonesty Policy:

Student Conduct: Penalties for academic dishonesty will be severed. Academic dishonesty includes cheating, plagiarism or sabotage. Cheating includes, but is not limited to: (i) unauthorized assistance in taking quizzes, tests or examinations; (ii) dependence upon the aid of sources beyond those authorized by the instructor in solving problems or carrying out other assignments; (iii) acquisition or possession without permission of tests or other academic material belonging to a member of the faculty or staff; (iv) knowingly providing any unauthorized assistance to another student on quizzes, tests or examinations. Plagiarism includes, but is not limited to: (i) use by paraphrase or direct quotation of the published or unpublished work of another person without fully and properly crediting the author with references; (ii) unacknowledged use of materials prepared by another person or agency engaged in the selling of term papers or other academic materials; or (iii) unacknowledged use of original work/material that has been produced through collaboration with others without release in writing from collaborators. Sabotage includes but is not limited to, the unauthorized interference with, modification of, or destruction of the work or intellectual property of another member of the University community. Other conduct that is subject to disciplinary action includes the actual or attempted theft or other abuse of computer time, including but not limited to: (i) unauthorized entry into a file to use, read or change the contents, or for any other purpose; (ii) unauthorized transfer of a file; (iii) unauthorized use of another individual's identification and password; (iv) use of computing facilities to interfere with the work of another student, faculty member or University official; (v) use of computing facilities to interfere with normal operation of the University computing system; (vi) knowingly causing a computer virus to become installed in a computer system or file. For this class, work turned in must be original and represent an individual effort unless otherwise indicated. IF DUPLICATE COPIES OF PROJECTS OR HOMEWORKS ARE RECEIVED, AN AUTOMATIC GRADE OF ZERO WILL BE GIVEN TO ALL PARTIES INVOLVED. Code which is not your own must be referenced (e.g. when using code libraries). Persons observed cheating on tests will forfeit the test and receive a zero for that test. Names of persons involved in any of these incidents will be forwarded to the campus Primary Administrative Officer. Those students will be subject to sanctions as outlined in the general catalog. Sanctions may result in dismissal from the University. I have read and I understand the Class Policies regarding Student Conduct. I agree to abide by these policies.

Signed: ____________________________________ Date: ________________

GENERAL LABORATORY POLICY:

All of us who share the laboratory must cooperate to maintain the facility in its best possible form. We all need to encourage and enforce professional standards to insure that the laboratory remains productive environment. All equipments and systems must be used in a careful and thoughtful manner to insure their integrity. Any equipment in needed of repair should be reported immediately, so that it can be expeditiously brought back to useable condition. Eating, drinking, and smoking are not permitted in the laboratory. All disks brought into the laboratory must be checked for computer viruses before execution any of the programs stored in the disks. Each laboratory session is intended to provide a discovery and learning experience. It is essential that student come prepared to make best use of the limited laboratory time. Every student must be thoroughly and independently prepared for each laboratory project to insure that the laboratory session will be productive, efficient, and professional. The laboratory instructor may ask questions about the laboratory assignment to insure that each student adequately prepared for the laboratory. Laboratory attendance at the assigned laboratory is required. Each student must submit his or her laboratory report on the due date at the beginning of the laboratory period. If a student misses a laboratory, his laboratory report will not be accepted.

LABORATORY SAFETY:
Whenever electricity is used in an experiment, some danger exists. This should always be kept in your mind. Most of the experiments in this course will be use only low voltages, which are inherently dangerous. However, it is possible to incorrectly wire almost any experiment, which may lead to dangerous. However, it is possible to incorrectly wire almost any experiment, which may lead to dangerous voltage levels. The careless use of electricity can have two results: it can hurt you and it can hurt the equipment. Obviously, you want to avoid hurting any thing. Try to understand what you are being asked to do. Consult your instructor if necessary. Never turn the power on until you are confident that everything is safe. To protect yourself, always treat electricity with respect. Dont handle hot lead wires. Dont leave wires dangling around the space. An old rule of thumb is to keep one hand in your pocket at all the times. This hopefully prevents the flow of electricity from one hand to another through your body, which potentially causes the heart to stop. Keeping one hand in your pocket also causes cramps, and decrease efficiency, so on one does it. But keep in mind that when you touch a wire that is electrified, the electricity always try to flow and it is at your advantage to keep it from flowing from flowing through your body. Dont hold electrified wires, and make sure that no part of your body inadvertently comes into contact with a wire.

5 To protect equipment, make sure that all of the hookups between power supplies, oscilloscopes, multimeters, light emitting diodes (LEDs), breadboards, integrated circuits (ICs) etc. Double check all wiring prior to prior to turning on the power. On way to destroy an IC is to reverse power leads. An abused IC may start smoking, or may become so hot that you cannot touch it. While probing a circuit with a test lead, please ensure that you are making contact with the exact points you wish to test, and only those points. When using a particular piece of test equipment, understand the limitations of the equipment. Dont try to use it to test something it wasnt designed to test. Read the equipment manual whenever necessary. In the event that there is an emergency situation, call campus security 1515.

LABORATORY REPORT FORMAT:

Each student will be required to write a formal report after successfully demonstrating a working laboratory project to the instructor. All laboratory reports must be type written on one side of white 8.5 x 11 papers. The lab report must include the following section: Title Page: The title page must include the course number, the experiment number, the title of the experiment, the date of performing the experiment, the due date, student number, and the name of your partners (if applicable). Objective: This section briefly explains the purpose of the experiment. Equipment and Software Packages: This section includes the list of equipments, components, and software packages used for the experiment. Theory: This section includes a brief discussion of the theoretical background of the experiment being performed. Procedure: Described briefly the procedure used to implement your laboratory project. For laboratory assignment involving hardware design, all necessary circuit diagrams including an operational description of the circuit must be included in this section. Your circuit diagram must include a gate level diagram including the IC types and the pin numbers. A block diagram for each circuit diagram is required. For laboratory assignment involving software design, describe concisely the operational description of your program. A printed copy of your program listing is required for all programs written for a laboratory assignment. A program must include a header statement, which contains the course name and the number, the name of the student, the purpose of the program, and special instruction (if any), to the user for executing the program. Your program must include proper and clear documentation (not just commenting) so that a third person can understand the purpose of your program without difficulty. Include the printout your program in an appendix.

Sample Calculation: This section includes a sample of any calculation that you may perform while doing the experiments. Table / Graphs: This section includes the results obtained from the experiment in tabular form. Draw appropriate graphs from the tabular results if necessary. The table / graph must be appropriately labeled with a title. The data sheet(s) used during the laboratory period must be included in an appendix. For more detailed information, please refer to appendix II on graphs. Discussion of Results: This section includes an analysis of your results obtained from the experiment. Also, include a printout of your result such as the outputs obtained from a program and the waveform obtained from the oscilloscope. Answers to Questions: This section includes answer to questions (if any) Conclusions: Describe briefly what you have learned from the experiment.

GENERAL GRADING POLICY:

Because the laboratory work is an essential ingredient of this course, a student must successfully complete all the laboratory assignments with a minimum of 70% credit assigned for all laboratories in order to pass this course. A laboratory assignment is complete when it functions according to the given specifications and a report is submitted for the corresponding laboratory assignment. No credit will be given for an incomplete laboratory assignment. Overall neatness and clarity of work will essential to receiving full credit. A maximum of 20% may be deducted from your laboratory reports due to sloppy work. For programming assignments, grading will be based on the proper and clear documentation, efficient programming, and workability. For late laboratory reports, 20% credit will deducted for each day after the due date. Partial credit is a matter of professional judgment and is not subject to negotiation.

List of Equipment Note: All equipment and parts are supplied by UMKC
Package List for one Student: Item Solderless Breadboard Jump Wires Push Button Tactile Switch 12 Pos 24 Pin Dipswitch Resister Resister Resister Resister Resister Capacitor (> 6 Volts) Capacitor (> 6 Volts) Capacitor (> 6 Volts) Capacitor (> 6 Volts) Timers LEDs LED Displays 8 x 1 MUX Dual D Flip Flop Stk. No. Type WB-204-3R WJW-60B-R KRS-3550-BK-R D5-12-G-01-BL-R 1KW 100 W 10 K W 27 K W 100 K W 2200 F 0.01 F 10.0 F 47 F 555 Timer XC556R MAN72 74LS151 74LS74 Qty. 1 1 1 1 10 6 2 1 1 1 1 1 1 2 8 1 1 2 Jameco

155249 206481 690865 690620 691104 691201 691304 767121 26884 545641 1946244 27422 697602 24740 301348 48004

Dual JK Flip Flop Dual 4 x 1 MUX Hex Inverter Hex Inverter buffer/driver Quad 2-input AND Quad 2-input NAND Dual 4-input NAND Quad 2-input NOR Quad 2-input OR Binary Counter 4-bit Full Adder XOR Gates 3-to-8 line decoder/demux BCD to 7 segment driver

74LS76 74LS153 74LS04 74LS06 74LS08 74LS00 74LS20 74LS02 74LS32 74LS193 74LS83 74LS86 74LS138 74LS47

2 2 1 1 1 1 1 2 1 1 1 1 1 2

48039 46720 46316 295304 46375 46252 47095 46287 47466 47036 48063 48098 46607 47790

NOTE: In addition to these components the Lab should be equipped with Oscilloscope (29 MHz), Function Generator, Power Supply, Computer and Printer.

Logic 74xxxx Series

74LS00 74LS01 74LS02 74LS03 74LS04 74LS05 74LS06 74LS08 74LS09 74LS10 74LS11 74LS12 74LS13 74LS14 74LS16 74LS15 74LS20 74LS21 74LS22 7425 74LS22 7425 74LS27 74LS30 74LS32 74LS38 74LS42 7445 74LS47 74LS48 74LS51 74LS54 74F64 Quad 2 input NAND gate Quad 2 input NAND gate (OC) Quad 2 input NOR gate Quad 2 input NAND gate Hex Inverter Hex Inverter (OC) Hex Inverter buffer/driver Quad 2 input AND Quad 2 input AND gate (OC) Triple 3 input NAND gate Triple 3 input AND gate Triple 3 input NAND gate (OC) 74LS76 clear 74LS83 74LS85 74LS86 74LS90 74LS91 74LS92 74LS93 74LS95 74LS107 74LS109 74LS112 Dual JK flip-flops with preset and 4 bit full adder 4 bit magnitude comparator Quad 2 input XOR gate Decade counter 8-bit shift register Divide by 12 counter Binary counter 4 bit shift register Dual JK flip-flops with clear Dual JK pos edge trig flip flop Dual JK neg edge trig flip flop Monostable multivibrator Monostable multivibrator Monostable multivibrator Monostable multivibrator Quad 2 input NAND gate Schmitt 13 input NAND Quad 2 input XOR (O.C) 3-to-8 line decoder/demux Dual 1-of-4 decoder/demux 74LS174 74LS175 74176 74177 74LS191 74LS192 74LS193 74LS195 74LS196 74LS197 74199 74LS221 74S225 74LS240 74LS241 74LS244 74LS245 74LS251 74LS257 74LS259 74LS266 Hex D type flip flop with clear Quad D type flip flop with clear Decade Counter Binary Counter 4 bit binary up / down counter BCD up / down counter 4 bit binary up / down counter 4 bit shift register Presettable decade counter Presettable binary counter 8-bit shift register Dual monostable multivibrator 16x5 FIFO memory Octal buffer/line driver Octal 3-state buffer Octal buffer/line driver Octal bus tranciever Data selector / MUX Quad 2 input mux 3-state 8 bit addresable latch Quad 2 input XNOR (O.C) Octal D type flip flop with clear 9 bit odd / even parity generator Quad 2 input MUX with storage 8 bit universal shift register 8-Bit Shift register Hex bus driver Hex bus driver with inverters Octal transparent latch Octal D type flip flop 3-state Dual 4 bit decade counter Dual 4 bit binary counter 4 bit shift register

Dual 4-input NAND gate Schmitt trigger 74121 Hex Inverter Schmitt trigger Hex Inverter (OC) Triple 3 input AND gate (OC) Dual 4 input NAND gate Dual 4 input AND gate Dual 4 input NAND gate (OC) Dual 4 input NOR gate with strobe Dual 4 input NAND gate (OC) Dual 4 input NOR gate with strobe Triple 3 input NOR gate 8 input NAND gate Quad 2 input OR gate Quad 2 input NAND gate Buffer BCD to DEC decoder BCD to DEC decoder BCD to 7 seg decoder/driver BCD to 7 seg decoder/driver AND/OR/INVERT gate AND/OR/INVERT gate AND/OR/INVERT gate 74LS122 74LS123 74LS125 74LS132 trigger 74S133 74LS136 74LS138 74LS139 74LS147 74LS148 74150 74LS151 74LS153 74LS154

10 line - 4 line octal priority encoder 74LS273 8 line - 3 line octal priority encoder 74LS280 Data selector/mux 8 input MUX Dual 4-to-1 Multiplexer 4-to16 decoder/demux 74LS298 74LS299 74LS323 74LS367 74LS368 74LS373 74LS374 74LS390 74LS393 74LS395

74LS155 Dual 2 line to 4 line decoder / demux 74LS156 Dual 2 line to 4 line decoder / demux (O.C) 74LS157 74LS158 outputs 74LS160 74LS161 Quad 2 input MUX Quad 2 input MUX with inverted BCD decade counter Synchronous 4 bit binary counter

9
7470 7472 74LS73 74LS74 clear 74LS75 JK flip flop JK M/S flip flop Dual JK flip flop with clear Dual D-Type flip-flops with preset and 4 bit bistable latch 74LS162 74LS163 74LS164 74LS165 74LS166 BCD decade counter 74LS540 Octal buffer 3-state Octal buffer 3-state outputs

Asynchronous 4 bit binary counter 74LS541 8 bit SIPO shift register 8 bit PISO shift register 8 bit PISO shift register

10

List of Potential Suppliers

Note: All equipment and parts are supplied by UMKC.
1: Electronic School Supply, Inc. (Recommended)
3070 Skyway Dr. #303 Santa Maria CA 93455 Ph. : (805) 922-6383 TOLL-FREE (800) 726-0084 FAX (805) 928-0253 www.esssales.com Email: essinc@lightspeed.net 2: Mouser Electronics www.mouser.com 3: B&B Electronics Mfg. Co. www.bb-elec.com Ph : (815) 433-5100 Email: info@bb-elec.com FAX: (815) 433-5109 TOLL-FREE: (800) 346 6873

4: MCM Electronics www.mcmelectronics.com TOLL-FREE : (800) 543-4330 FAX: (800) 765-6960 5: Digi-Key www.digi-key.com 6: Jameco Ph. : (415)-592-8097 7: Electronics Supply Co. Inc. 4100 Main Street Kansas City MO-64111 Ph. : (816) 931-0250 TOLL-FREE: (800) 669- 3752 TOLL-FREE: (800)-DIGI-KEY

11

List of Experiments
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 Auxiliary Circuits for ECE-227 Lab TTL Logic Gates Applications of NAND and NOR Gates Code-Converter Circuits 2-Bit Binary Ripple Carry Adder 4-Bit 2s Complement Adder/Subtractor Multiplexers Flip-Flops Design with flip-flops Register Configurations Multifunction Register Synchronous and Asynchronous Counters Appendix A Appendix B Appendix C

12

Experiment 0: Auxiliary Circuits for ECE-227 Lab The circuits in this experiment are only needed to perform experiments outside the lab. Most students may skip this experiment. Objectives: To introduce some useful circuits either signal generators or testing indicators for the following ECE-227 experiments.

Materials Needed: 1..Dipswitch. 2..555 Timers. 1..74LS06 TTL IC. 6..XC556R LEDs.

Introduction: I. 0 1 Switch 0 1 switch is used here to supply the `0` or `1` digital signal to the experimented digital circuit as its data inputs or control signals. The circuit diagram is shown in Figure 1. Figure 2 shows the circuit diagram for eight 0 1 switches.

Fig 1: 0 1 switch

Fig 2: Eight 0 -1 switches (using dipswitches)

13

II. Square-wave Generator (Oscillator) Square-wave generator is used here to supply the continuous 0 1 pulses to the experimented digital circuit (to trigger the flip-flops). The following circuit (see Figure 3) is using a 555 timer to make a square-wave generator. The period could be calculated by the formula: T = 0.7 * (R1 + 2 * R2) * C

Fig 3: Square-wave generator III. Monostable Circuit Monostable circuit is used here to supply a signal 0 1 pulse to trigger the flip-flops in the experimented circuit. One typical monostable circuit using 555 timer is shown in Figure 4. The Tpo is approximated equal to: Tpo = 1.1 * R * C.

Fig 4: A typical monostable circuit

14

IV. 0 1 Indicator 0 1 indicator is used here to measure the output level (high 1, low 0) of the experimented digital circuit. Atypical 0 1 indicator (six indicates actually) is shown in Figure 5 by using open-collector driver 7406 TTL IC.

1 LED ON 0 LED OFF

Fig 5: Six 0 1 indicators Procedure: Connect all above circuits in your bottom slice breadboard and do NOT disconnect them for you will use them in your later experiments.

15 Experiment 1: TTL Logic Gates Objectives: To demonstrate the operation and characteristics of a TTL logic gate and to show how it can be used to perform any of the three basic logic functions. Materials Needed: 1--74LS00 quad 2-input NAND TTL IC 1--74LS02 quad 2-input NOR TTL IC 1--DC Voltmeter 1-- +5V Power supply Procedure: 1. Mount the 74LS00 TTL IC on the breadboard. Be sure that it is seated firmly straddling the notch in the socket and that none of the pins are bent. Connect pin 14 to +5 volts and pin 7 to GND (ground). 2. Connect one of the four gates in the IC as shown in figure 1. The input will come from data switch SW1. 3. Set SW1 to the down position then the up position. Measure the DC input (pins 1 and 2) and the output (pin 3) voltage for each position. Record your data in Table 1 4. Assuming positive logic, determine the logic function being performed.
Sw1 1

Sw1 I

1 2
Fig 1

3 L

B Sw2 2
Fig 2

Input I

Output L

Table I A(SW1) 0V 0V +5 V +5 V B (SW2) 0V +5 V 0V +5 V Table II Table III F A B F

16 5. Wire the circuit shown in Figure 2. You will measure the output voltage F at pin 3 of the 74LS00 IC. 6. With SW1 and SW2, apply the input voltages given in Table II. Measure and record the output voltage for each set of inputs. 7. Using positive logic convert your electric truth table in Table II into 1s and 0s in Table III. Study Table III. Determine the logic function being performed. 8. Remove the wires connecting pins 1 and 2 of the IC to SW1 and SW2. Let the gate inputs hang free. Note the output state. With open inputs, the TTL gate output is _______ volts or binary _______ for positive logic. This means that an open input acts like a binary _________. 9. Wire the circuit shown in Figure 3. With SW1 (A) and SW2 (B), apply the states shown in Table IV 10. Study the circuit in Figure 3 and the data in Table IV. Determine the logic function being performed. 11. Replace 74LS00 with 74LS02, repeat steps 110. Record your data in Table V Table VIII. Note the difference of pin-out between 74LS00 and 74LS02. Table IV
A Sw1 1 3 4 5
Fig 3

Table V F Input I Output L

A
F

B 0 1 0 1

B Sw2 2

0 0 1 1

A 0V 0V +5 V +5 V

B 0V +5 V 0V +5 V Table VI

A 0 0 1 1

B 0 1 0 1 Table VII

A 0 0 1 1 TableVIII

B 0 1 0 1

17

Experiment 2: Applications of NAND and NOR Gates Objectives: (a) To verify one of the Demorgans laws by experiment. (b) To show how TTL NAND and NOR gates are used to implement any logic functions and to demonstrate the value of Boolean algebra in reducing logic circuits to their minimum configuration. Materials Needed: 1 74LS20 TTL IC 1--74LS00 TTL IC 1--74LS02 TTL IC 1--DC Voltmeter 1-- +5V Power supply (a) Procedure: 1. Choose one of Demorgans laws (A + B)= AB or (AB) = A+ B. Design two circuits separately to perform the function of each side of the chosen Demorgans law respectively. Students are required to do this as a pre-lab work. 2. Construct the circuits according to your design. Using the data switches as inputs, measure the outputs. Record your results in the truth table I and II respectively. 3. Compare the two truth tables and get the conclusion.

Table I A 0 0 1 1 B 0 1 0 1 A 0 0 1 1

Table II B 0 1 0 1

18 (b) Procedure: 1. Write the output expression of the circuit shown in the figure 1. F =_____________________________________________ 2. Figure 2 shows the NAND gate implementation of the circuit in Figure 1. Wire the circuit shown in figure 2. Be sure to connect pin 14 to +5 volts and pin 7 to GND on each IC. 3. Apply the inputs A, B, C and D in Table I to the circuit with data switches SW1 through SW4. Measure the output on L1 and record the state for each set of inputs on the left hand F columns in table I.

A C B A D B C B D
Figure 1

SW 1 SW 3

A C

SW 1 A

SW 4 SW 2 SW 3 SW 2

D B C B

F
L1

SW 4 D Figure 2

4. Using Boolean algebra, reduce the output equation obtained in step 1. The minimized expression is: (Product of sums form) F = _________________________________ 5. Write the output equation of the circuit in figure 3. Compare it to the expression you derived in step 4. F = ______________________________ 6. Construct the circuit shown in figure 3. 7. Apply the inputs shown in table 1 and record the output state in the righthand column. 8. Compare the two F output columns in table I and get the conclusion.

19

A B F C D

Fig 3

Inputs A 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 B 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 C 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 D 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 F (fig2)

Outputs F (fig3)

20 Experiment 3: Code Converter Circuits Objectives: To study the operation and usefulness of several MSI code converter and adder circuit devices. Material Needed: 1 74LS138 (Decoder) TTL IC 1 74LS47 (Driver) TTL IC 1 MAN72 LED Displays 1 DC Voltmeter 1 +5V Power Supply Procedure: Part A 1. Mount a 74LS138 binary to octal converter (3 to 8 decoder) on the breadboard socket. Connect pin 16 to +5 volts and pin 8 to GND 2. Set up the connections depicted in Figure 1. Verify binary to octal conversion by completing the truth table I. 3. Grounding the enable input G1, monitor the outputs Y0 Y7 and write your comments.

Inputs:
SW1 SW2 SW3 A B C

Outputs: A B C
Yo Y1

Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7

74LS138

Y2 Y3 Y4 Y5 Y6 Y7

Enable (Open)

G1 G2A G2B

Figure 1 Part B

Table 1

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4. Mount a 74LS47 TTL IC and a 7 segment LED display device on the bread boarding socket. Connect pin 16 of 74LS47 to +5 volts and pin 8 to GND 5. Set up the circuit depicted in figure 2. Verify BCD to seven-segment code conversion by completing the truth table II
LED Display BCD Inputs
Sw1 Sw2 Sw3 Sw4 D C B a b c f g b

+5V

74LS47

d e f g h e e d

LT OPEN FBO FB1

Figure II

SYMBOL

0 0 0 0 0 0 0 0 1 1

0 0 0 0 1 1 1 1 0 0

0 0 1 1 0 0 1 1 0 0

0 1 0 1 0 1 0 1 0 1 Table II

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Experiment 4: 2-Bit Binary Ripple Carry Adder

Objective: To design a 2-bit binary ripple carry adder. Materials Needed: 1 74LS86 1 74LS08 1 74LS02 Introduction: A full-adder is a combinational circuit that forms the arithmetic sum of three bits. It consists of three inputs and two outputs. Two of the input variables represent the two significant bits to be added. The third input variable represents the carry from the previous lower significant position. Two outputs are necessary because the arithmetic sum of the three binary digits ranges in value from 0 to 3 and binary 2 or 3 needs two digits. The two outputs are designated by the symbols S for sum and C for carry. The binary variable S gives the value of the least significant bit of the sum. The binary variable C gives the output carry.

A binary adder is a digital circuit that produces the arithmetic sum of two binary numbers. It can be constructed with full adders connected in cascade, with the output carry from each full adder connected to the input carry of the next full adder in the chain. The figure below shows the interconnection of four full adder (FA) circuits to provide a 4-bit binary ripple carry adder. The augend bits of A and the addend bits of B are designated by subscript numbers from right to left, with subscript 0 denoting the least significant bit. The carries are connected in a chain through the full adders. The input carry to the adder is C0 and it ripples through full adders to the output carry C4. The S outputs generate the required sum bits. An n-bit adder requires n full adders with each output carry connected to the input carry of the next higher order full adder.

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Prelab Design a 2-bit binary ripple carry adder using the configuration described above. Derive its truth table, equations and draw the logic diagram. Procedure Implement your designed circuit and test it using the following data: Inputs (Decimal) B 2 0 1 3 1 2 Outputs Carry_out

A 1 1 0 2 3 3

Carry_in 1 1 0 0 1 1

Sum

24 Experiment 5: 4 Bit 2s Complement Adder/Subtractor Objectives: To study the operation of 2s complement Adder/Subtractor by using full adder and XOR gates IC chips. Materials Needed: 1--74LS83 (4-bit full adder) TTL integrated circuits 1--74LS86 (XOR gates) TTL integrated circuits 1--DC Voltmeter 1-- +5V Power supply Procedure: 1. Mount the 74LS83 and 74LS86 TTL ICs on the breadboard socket. Connect pin 5 of 74LS83 and pin 14 74LS86 to +5 volts, pin 12 of 74LS83 and pin 7 of 74LS86 to GND. 2. Construct the circuit as shown in figure 1. 3. Apply the inputs and verify correct operation by testing the following sets of numbers.

Decimal 1 -2 ------------

Binary 0001 - 0010 ------------

Carry

7 - 5 -----------8 + 9 ------------

------------

------------

25 Decimal Binary Carry

-1 +8 ------------

------------

-5 +6 ------------

-----------Sum

Carry

C4 A4 B4 A3 B3

74LS83
A2 B2 A1 B1

C0

74LS86
Adder/Subtracter 0/1

DA4 DB4

DA3

DB3

DA2

DB2

DA1

DB1

Input Data

Figure 1

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Experiment 6: Multiplexers

Objectives: To demonstrate the operation and applications of digital multiplexers. Materials Needed: 1--74LS00 TTL IC 1--74LS151 TTL IC 1--74LS193 TTL IC 1--74LS06 TTL IC Procedure: 1. Construct the circuit shown in Figure 1. Study the circuit and answer the questions below. a. What type of circuit is this? b. The two signal sources are _____________ and _______________. c. The control input is ______________. 2. Apply the power to the circuit. Set SW1 to the binary 1 position and note the circuit output on 0-1 indicator at L1. Note the effect of switching A off and on. The output is _______________, when A is set to binary position 1. Set SW1 to binary 1 position. Note the effect of switching B off and on. The output is _________________, regardless of B value. 74LS00
A

SW1 L1

Figure 1 3. Construct your circuit to conform the Figure 2. Wire the inputs of the multiplexer as shown in Figure 2. Connected in this way, the multiplexer becomes a serial data word generator or a Boolean function generator.

27

+5V

D0 D1

16

3 D2 2 +5V 1 15 14 13 12 7 11 10 9 L2

74LS151

D3 D4 D5 D6 D7

L1

L3

L4 3 A 2 B 6
4 4

C 16 +5V 1K

CLK

74LS193 Figure 2.
CLR 14

4 8

Figure 2 4. Apply power to the circuit. Step the counter with the monostable circuit at A until it is in the 000 state as indicated by 0-1 indicators at L2 through L4. At this time observe the multiplexer output at L1. This is the first bit (LSB) of an eight bit word to be generated by the 74LS151 multiplexer. Next, step the counter with monostable circuit at A. At each counter state, note the multiplexer output by observing L1. Increment the counter until the last bit of the word (counter state 111) is obtained. Record the binary word developed and its equivalent decimal value in the spaces provided below. Serial output binary word = ______________________. Decimal equivalent = _____________________.

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5. Without changing the experimental circuit, assume that it is being used as a Boolean function generator. Use the data from step 4 to complete the following truth table. 6. Write the Boolean equation (Sum-of-products) from the truth table. Record your Boolean equation below. L1 = ________________________________________.

INPUTS CBA 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1

OUTPUT L1

29 Experiment 7: Flip-Flops Objectives: To become familiar with the input/output characteristics of several types of standard flipflop devices and the conversion among them. Materials Needed: 1..74LS00 TTL IC. 1..74LS74 TTL IC. 1..74LS76 TTL IC. Introduction: Logic circuits whose outputs depend upon circuit inputs as well as previous values of circuit outputs described as their present states are known as sequential logic circuits. A sequential system can be defined in terms of its inputs and present state. That is, the next state of the sequential system can be determined from these two quantities. The (clocked) RS, D, JK and T flip-flops are characterized by the following state tables.

R 0 0 0 0 1 1 1 1

S 0 0 1 1 0 0 1 1

Qt 0 1 0 1 0 1 0 1

Qt+1 0 1 1 1 0 0 ? ?

J 0 0 0 0 1 1 1 1

K 0 0 1 1 0 0 1 1

Qt 0 1 0 1 0 1 0 1

Qt+1 0 1 0 0 1 1 1 0

Table 1: RS flip-flop

Table 2: JK flip-flop

D 0 0 1 1

Qt 0 1 0 1

Qt+1 0 0 1 1

T 0 0 1 1

Qt 0 1 0 1

Qt+1 0 1 1 0

Table 3: D flip-flop

Table 4: T flip-flop

30 The `?` in the RS flip-flop state table means that when R = 1 and S = 1 then the next state is not determined explicitly.

Procedure: 1. Construct the cross-coupled NAND gate basic RS flip-flop depicted in Figure 1 and verify its sequential operation by completing the timing diagram shown in Figure 2.

Fig 1: Basic RS flip-flop

Fig 2: Timing Diagram

2. Construct the clocked RS flip-flop of Figure 3. Determine its state table. Use monostable circuit as your clock source.

Fig 3: Clocked RS flip-flop

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3. Simultaneous application of ones to S and R of the clocked RS flip-flop, observe the outputs. 4. Since the constructed clocked RS flip-flop is symmetric, we can change the position of R & S, and Q` & Q. It is still a clocked RS flip-flop. Repeat step 3, see what has happened. Give your conclusion.

5. Using the 74LS74 dual D flip-flop, investigate the operation of the D flip-flop (See Figure 4) There is no Fig. 4. Compare your result with the state table given above. Pay attention to the change in state of the device as the clock signal is rising or falling. Complete the following timing diagram.

Fig 4: D flip-flop Fig 5: Timing Diagram

6. Let input CLR open, ground the input PR, watch the output and then let PR open, ground CLR, watch the output. Determine the usage of these two inputs on 74LS74.

32 7. Using the 74LS76 dual JK master-slave flip-flop, determine its logical operation. The circuit diagram is shown in figure 6. As described in step 5, pay attention to the state changes as the clock signal is rising or falling. Complete the following timing diagram.

Fig 6: JK flip-flop

Fig 7: Timing Diagram 8. The flip-flops can simulate each other. Construct the circuit shown in Figure 8. Verify its sequential operation as a D flip-flop. Complete the following timing diagram. Compare it with the timing diagram of figure 5.

Fig 8: D flip-flop (Constructed by JK flip-flop)

Fig 9: Timing Diagram

33 9. Wiring the circuit shown in Figure 10, verify that it is a T flip-flop.

Fig 10: T flip-flop (Constructed by JK flip-flop)

Fig 11: Timing Diagram

Experiment 8: Design with Flip-Flops Objective: To explore basic design concepts of sequential logic. Materials Needed: 1 74LS74 1 74LS76 Other ICs based on student design

34 Prelab: 1) A sequential circuit with two D flip-flops, A and B and two inputs, x and y is specified by the following next state and output equations: A(t+1) = xy + xA B(t+1) = xB + xA a) List the state table for the sequential circuit. b) Draw the logic diagram of the circuit. 2) A sequential circuit has two JK flip-flops A and B and one input x. The circuit is described by the following flip-flop input equations: JA = x KA = B JB = x KB = A a) Derive the state equations A(t+1) and B(t+1) by substituting the input equations for the J and K variables. b) Draw the logic diagram of the circuit. Procedure 1) Construct the circuit designed in question 1. 2) Observe the output of your circuit and from the output draw the corresponding state diagram. 3) Construct the circuit designed in question 2. 4) Observe the output of your circuit and from the output draw the corresponding state diagram.

35 Experiment 9: Basic Configurations of Shift Registers Objective: To explore basic concepts of shift register configurations. Materials Needed: 2 74LS74 ICs Introduction: A register is a group of flip-flops. Each flip-flop is capable of storing one bit of information. An n-bit register consists of a group of n flip-flops capable of storing n bits of binary information. A register capable of shifting information in one or both directions is called a shift register. The logical configuration of a shift register consists of a chain of flip-flops in cascade, with the output of one flip-flop connected to the input of the next flip-flop. All flip-flops receive common clock pulses, which activate the shift from one stage to the next. 4-bit Parallel in/Parallel out Register Construct the circuit given below in figure 1.

Figure 1

36 Load the inputs with the following values and with each CLK cycle record your outputs in the table below. CLK PA 1 0 1 0 PB 0 1 1 0 PC 1 1 0 0 PD 1 0 0 1 QA QB QC QD

4-bit Serial in/Parallel out Register Make modifications to your circuit so as it is configured according to Figure 2.

Figure 2 Load Serial Data input with the following values and with each CLK cycle record your outputs in the table below. CLK Serial Data In 1 0 1 1 QA QB QC QD

37 4-bit Serial in/Serial out Register Make modifications to your circuit so as it is configured according to Figure 3.

Figure 3 Load Serial Data input with the following values and with each CLK cycle record your output in the table below.

CLK

Serial Data In 0 1 1 0 1 0 0 1 1

Serial Data Out

Experiment 10: Multifunction Register Objectives: To apply the methods for sequential circuit design developed in ECE 226 class to the design of a complicated register and to become familiar with the multiplexer. Materials Needed: 2--74LS74 TTL IC 2--74LS153 TTL IC 174LS04 TTL IC

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Introduction: Registers are an important building component in every computer. Most registers found in computers are multifunction, that is they are capable of implementing a number of functions as shift-left, shift-right, clear, complement, parallel load, etc. Furthermore, the shift functions can be further classified as logical shifts, arithmetic shifts and circular shifts. Prelab: Referring to your textbook and using the material presented in ECE 226 class, design a four bit multifunction register. It works in four modes as listed below: 1. No change ------- The state (outputs) of the register will not change even though clock pulses are continuously applied.

2. Shift right -------- It acts as shift right register.

3. Shift left --------- It acts as a shift left register.

4. Parallel load -------- The register could be loaded in parallel. It acts as four 1-bit data registers.

There are two S1, S0 for selecting The following table mode control by S0

Mode Control S1 S0 0 0 0 1 1 1 0 1

Register operation No change Shift right Shift left Parallel load

selection lines the proper mode. gives a list of and S1.

The register should have a clear control to clear the register to 0, two serial inputs one for shift-right and one for shift-left, a CP input for clock pulses to synchronize all operations and four parallel inputs for parallel loading.

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2 S0 S1 LSI D1 14 2 4 3 5 6 10 12 11 D2 13 9 8 1 15 11

4 PRE D

74LS74

D F/F
16 7 VCC 3 CLK CLR 1 4 PRE D

Q1

74LS153

12

D F/F
CLK CLR 13

Q2

4 PRE 2 14 16 2 D3 3 5 4 6 12 10 D4 RSI 13 11 9 8 1 15 11 CLK CLR 13 7 VCC 3 CLK CLR 1 4 PRE 12 D D

74LS74
5 Q3

D F/F

74LS153

D F/F

Q4

CLK CLR

40 Procedure: 1. Construct your designed register as shown in figure 1. Clear the register to 0. As the experiments become more sophisticated, the number of integrated circuits to be interconnected increases. This also increases the chance of your making a wiring mistake. If the circuit does not perform properly, the first thing to check is your circuit wiring. Be sure that you connected +5 volts and ground to each of the integrated circuits in the experimental circuit. 2. Let S0 = S1 = 1, put 1010 to the parallel inputs, input clock pulse by using monostable circuit. Observe the output of the register. 3. Let S0 = S1 = 0, input clock pulse. Observe the output. 4. Let S0 = 0, S1 = 1, set LSI = 0, Serial input for shift left. Input two clock pulses by using monostable circuit. Observe the change of output. 5. Set 1 to the RSI, Serial input for shift right. Repeat step 4, but let S0 =1, S1=0 instead of S0 = 0, S1 = 1. Observe the change of output.

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Experiment 11: Synchronous and Asynchronous Counters

Objectives: To apply the theoretical methods developed in ECE 226 class for designing the synchronous and asynchronous counters.

Materials Needed: 2--74LS76 TTL IC 2--74LS74 TTL IC. And some other TTL ICs depending on your design.

Prelab: Using the material for counter design in your ECE-226 class, design a synchronous decade counter by using the 74LS74 dual D flip-flops for implementation and an asynchronous decade counter by using the 74LS76 dual JK flip-flops.

Procedure: 1. Construct your designed synchronous decade counter. 2. Using the square wave generator as your clock source, observe the output of the counter. 3. Construct your designed asynchronous decade counter. Then repeat step 2.

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Appendix A Pin-Out Diagram

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Appendix B 555 - Timer

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Appendix C 7400 ICs Data Sheet

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69 74LS74 Dual D-Flip Flops

74LS76 Dual JK Flip Flops