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ID (mA/mm)
600
gm = 200 mS/mm
d Open channel
400 200 0 0 2 4 6 8 10 12 14 16
Lg Source Wg Gate
Drain
VDS (V)
Active Region S. I. Buffer
Lg
Pinch off
Similar to normally-on MOSFETs but no substrate doping. For accurate formula, refer to Sze: Physics of Semiconductor Devices
I max
BIAS POINT
IDS
Q
VSWING ISWING 8
Minimize Vknee
V knee
VDS
Vbreakdown
VSWING
1 20 0.6 1.4
If the dc input power is also given then the Power-Added Efficiency (PAE) can be calculated as (Pout Pin)/Pdc
Slide # 3
Slide # 5
time
Slide # 6
AlN
InN
High Al (x=0.5 ~ 1) is currently under intense research (UV LEDs and detectors etc.)
GaN
Slide # 7
_ _ _ __ _ __ _ __ _ _ _ _ _ __ _ _
Gate
Source
AlxGa1-xN
Drain
+ + + Donors
Surface states
+++++-
UID AlGaN
Polarization charge
+ + + + + + +
2DEG
AlGaAs/GaAs HEMT
AlGaN/GaN HEMT
Slide # 8
AlGaN
GaN
Ec
Ec d +ve EF
GaN buffer(1-2 m)
comp
B
2 DEG
+ B 0 ns = 2 [ B + E F (ns ) Ec ] e de The 2DEG is an explicit function of the surface barrier, AlGaN thickness, and the bound positive charge at the interface
Slide # 9
surf
AlGaN
GaN
Ec d
+ve
comp
B
2 DEG
GaAs buffer
surf
AlGaAs spacer
No doping is required for the 2DEG to be present at the interface. Higher sheet charge and higher conduction band discontinuity for AlGaN/GaN heterostructure
Slide # 10
2DEG (density and mobility) Determined by - xAl - interface roughness - alloy scattering - dislocation, etc. Slide # 11
Al2O3/SiC
For AlGaAs/GaAs heterostructures, the spacer layer thickness is important for 2DEG mobility and density The 2DEG does not freeze out at very low temperature unlike the 3D doping The 2DEG mobility does not decrease with decrease in temperature unlike the 3D case The 2DEG mobility can increase with increase in 2DEG density due to increased screening unlike the 3D doping Slide # 12
300K
~ 1/xAl
1500 1400 1300 1200 1100 1000 1.8 1.6 1.4 1.2 1.0 0.8 0.6 0.2 0.4 0.6
-2 13 [10 cm ]
xAl :
- interface problems - strain induced defects - higher impurity incorporation - alloy ordering/clustering ns ~ xAl
300
- charge increases due to spontaneous polarization and piezoelectric effects xAl<0.2: 300K ~ xAl
0.0
ns
xAl
- better confinement of the 2DEG at higher xAl - low xAl = low ns: less efficient screening of defects
relaxed Slide # 13
GaN
2
GaAs
2
Usually the regions are separated into regions of constant and zero mobility A velocity overshoot is expected for GaN similar to GaAs case, but usually not seen, possibly due to high background doping At higher temperature, the degradation of v-F curve for GaN is much smaller than GaAs
Slide # 14
Slide # 15
Electron transport
Phonon scattering:
---most important at room temperature
where i refers to the mobility corresponding to different sources Alloy disorder scattering is the limiting factor at low temperature. Alloy disorder scattering also plays an important role at room temperature when carrier concentration is high. It is due to the ternary nature of AlGaN.
Debdeep Jena Ph.D dissertation
net
=
i
Slide # 16
30 25 cm )
-2
2.5 Mobility (10 , cm /Vs) AlGaN/GaN AlGaN/AlN/GaN 2 1.5 1 0.5 AlGaN/GaN AlGaN/AlN/GaN
(10
12
sapphire
T = 17 K
0 0 0.1 0.2 0.3 0.4 Alloy composition x 0.5
dAlN = 1 nm
no alloy scattering
Slide # 18
Al0.22Ga0.78N/GaN AlN/GaN
-2
0.06
5 4 3 2 1 0 0 5 10 15 20 25 30
Probability
AlGaN/GaN interface
13
Distance (nm)
However, after gate metal deposition, it was found to be almost ohmic due to tunneling!
Slide # 19
AlGaN/AlN/GaN Heterostructure
Incorporation of a thin AlN (<1nm) into a standard AlGaN/GaN HEMT The thickness of AlN interfacial layer is below critical thickness for formation of 2DEG. The main purpose is to improve mobility. Thin AlN layer forms a larger effective Ec, which affects both mobility and carrier concentration.
SiC Substrate
Slide # 20
1000
optimum thickness
0.0 0.5 1.0 1.5 2.0 2.5 3.0
800 600
Theory predicts that ns increases with AlN thickness In real growth, thick AlN suffers by the relaxation. Above 0.5nm, charge saturates and mobility drops
Slide # 21
1200
Mobility (cm V s )
13
-1
-1
1400
Band Diagram
25 nm Al0.33Ga0.67N/ 1 nm AlN/GaN HEMT
3
25 nm Al0.33Ga0.67N/GaN HEMT
Thin AlN
Energy (eV)
Effective EC
Energy (eV)
- + - + - + +
2
AlGaN GaN
EC
-1 0 10 20 30 40 50
10
20
30
40
50
Thickness (nm)
Thickness (nm)
2
AlGaN t AlGaN
ns =
E
' c , eff
t AlGaN
q q + t AlN + d 0
q2
B +
Ec' ,eff
ns =
AlGaN t AlGaN
0
q
B +
0
q
2
EC, AlGaN
t AlGaN + d0
= EC , AlGaN +
AlN t AlN
Slide # 22
ID (mA/mm)
600
gm = 200 mS/mm
400 200 0 0 2 4 6 8 10 12 14 16
VDS (V)
Mobility was improved with a slight increase of 2DEG Si doping increased 2DEG density while retaining high mobility
Slide # 23
Power Performance
Undoped AlGaN
35 40
Si-doped AlGaN
35 40
Pout Gain PAE 8.47 W/mm
25 20 15 10 5 0 0
30
30
8.1 W/mm
35
30 25 20 15 10 5 0 0
35 30
PAE (%)
20 15 10 5 5 10 15 20 25 0 30
20 15 10 5 5 10 15 20 25 0 30
Pin (dBm)
Pin (dBm)
On SiC substrate. SiN passivated. 8.1W/mm with a peak PAE of 23% was obtained at 8GHz at VD=50V, ID=130mA/mm from an undoped AlGaN barrier HEMT. 8.47W/mm with a PAE of 41% was obtained at 10GHz at 8GHz at VD=45V, ID=160mA/mm from a Si-doped barrier HEMT.
Slide # 24
PAE (%)
25
25
Nd/Polarization=1.2
Nd/Polarization=0.8
Nd/Polarization=0.5
6
Energy (eV)
2 0
Thickness (nm)
Thickness (nm)
Thickness (nm)
Too much Si doping results in free electrons in graded layer, leading to parallel conduction Too little Si doping is not enough to remove holes ~80% compensation puts fermi level in the middle of bandgap
Slide # 25
18
-3
Air-bridge to connect 4 isolated source pads Cl2 based ECR 1 mesa isolation
Slide # 27
D S G S S
D S G
The gate footprint and the cross-sectional area and width controls the frequency response
Lg lower means fT goes up Cross-section and gate width control gate resistance (this is why mushroom gates are used)
The gate drain spacing as well as gate footprint determines the breakdown voltage
Lg lower means VBR down Gate-drain spacing up means VBR up
Air bridges Larger periphery devices used for higher actual output power NOT power density (usually more than 1 mm gate finger width) The fabrication processes are complicated as this involves airbridging the source or the drain. Large periphery design issues: electrical and thermal
Slide # 29
Thermal issues:
Device heating is a problem at higher output power, since power wasted is also larger The maximum possible output power depends on the conductivity of the substrates. SiC substrates are commonly used. Thinned sapphire substrates have also been used. The number of gate fingers as well as the gate finger pitch determine the maximum temperature rise in a device.
Slide # 30
The negative slope in the dc characteristics of sapphire is either due to heating or trapping The dc characteristics are better for HEMTs fabricated on SiC than on sapphire possibly because of reduced dislocation density and increased thermal conductivity The difference becomes more severe with scaling
Slide # 31
RF performance
Small signal
30
Large signal
60
Pout Gain PAE
30
h21 UPG
3.4W/mm 50
25 20 15 10 5
20
30 20 10 0 5 10 15 20 0 25
10
10
100
f (GHz)
Pin (dBm)
ft of 22GHz and fmax of 40GHz were obtained from a 0.7um-gate-length HEMT at drain bias of 10V and drain current of 240mA/mm.
On sapphire substrate. No SiN passivation. 3.4W/mm with peak PAE 32% was obtained at 10GHz when VD=15V and ID=230mA/mm.
Slide # 32
PAE (%)
40
RF performance
Small signal
35
40 h21 UPG
Large signal
Pout (dBm), Gain (dB)
Pout Gain PAE 12W/mm
50 40
30 25 20
44%
30 20
20 10 0
15 10 10 0 0 5 10 15 20
10
100
Frequency (GHz)
Pin (dBm)
ft of 21GHz and fmax of 39GHz were obtained from a 0.7um-gate-length HEMT at drain bias of 15V and drain current of 280mA/mm.
On SiC substrate 12W/mm with a peak PAE of 44% was obtained at 4GHz at VD=50V, ID=270mA/mm
Slide # 33
PAE (%)
30