1) Half Adder Simulation By Data Flow Modelling

2) Full Adder Simulation By Data Flow Modelling

3) (a) Half Subractor Simulation By Data Flow Modelling

3) (b) Full Subtractor Simulation By Data Flow Modelling

4) B D to Decimal Decoder Simulation By Data Flow Modelling

!) Binary to "ray ode on#erter Simulation By Data Flow Modelling

$) "ray to Binary ode on#erter Simulation By Data Flow Modelling

%) B D to &'ce((3 ode on#erter Simulation By Data Flow Modelling

)) 4'1 Multi*le'er Simulation u(ing +f,el(e- a(e (tatement(

.) 2'4 Decoder Simulation By Data Flow Modelling

1/)

2 Bit Multi*lier Simulation By Data Flow Modelling

11) 2 Bit om*arator Simulation By Data Flow Modelling

12)

Half Adder Simulation by Structural Modelling

1!) 4'1 Multi*le'er Simulation By Data Flow Modelling

1$) 2'4 Decoder By Be0a#ioral Modelling

1. VHDL Code For Half Adder By Data Flow Modelling

library ieee1 u(e ieee2(td3logic311$42all1 entity 0alf3adder i( *ort(a4b5 in bit1(4c5 out bit)1 end 0alf3adder1 arc0itecture 0alf3adder of 0alf3adder i( begin (67(a 'or b)1 c67(a and b)1 end 0alf3adder1

2. VHDL Code For Full Adder By Data Flow Modelling

library ieee1 u(e ieee2(td3logic311$42all1 entity full3adder i( *ort(a4b4c5 in bit1(um4carry5 out bit)1 end full3adder1 arc0itecture full3adder of full3adder i( begin (um67((a 'or b) 'or c)1 carry67((a and b) or (b and c) or (c and a))1 end full3adder1

3. (a) VHDL Code For Half Su tra!tor By Data Flow Modelling

library ieee1 u(e ieee2(td3logic311$42all1 entity 0alf3(ubtractor i( *ort(a4b5 in bit1 difference4borrow5 out bit)1 end 0alf3(ubtrator1 arc0itecture 0alf3(ubtractor3dfm of (ubtractor i( begin difference67(a 'or b)1 borrow67((not a) and b)1 end 0alf3(ubtractor3dfm1

3. ( ) VHDL Code For Full Su tra!tor By Data Flow Modelling

library ieee1 u(e ieee2(td3logic311$42all1 entity full3(ubtractor i( *ort(a4b4*re#iou(3borrow5 in bit1 difference4ne't3borrow5 out bit)1 end full3(ubtractor1 arc0itecture full3(ubtractor3dfm of full3(ubtractor i( begin difference67((a 'or b) or (b 'or *re#iou(3borrow) or (a 'or *re#iou(3borrow))1 ne't3borrow67(((not a) and (b or *re#iou(3borrow)) or (b and *re#iou(3borrow))1 end full3(ubtractor3dfm1

". VHDL Code For BCD #o De!i$al De!oder By Data Flow Modelling
library ieee1 u(e ieee2(td3logic311$42all1 entity bcd3to3decimal i( *ort(a4b4c4d5 in bit1 e5 out bit3#ector(/ to .))1 end bcd3to3decimal1 arc0itecture bcd3to3decimal3dfm of bcd3to3decimal i( begin e(/)67((((not a) and (not b)) and (not c)) and (not d))1 e(1)67((((not a) and (not b)) and (not c)) and d)1 e(2)67(((not b) and c) and (not d))1 e(3)67(((not b) and c) and d)1 e(4)67((b and (not c)) and (not d))1 e(!)67((b and (not c)) and d)1 e($)67((b and c) and (not d))1 e(%)67((b and c) and d)1 e())67(a and (not d))1 e(.)67(a and d)1 end bcd3to3decimal3dfm1

%. VHDL Code For Binary to &ray Code Con'erter By Data Flow Modelling
library ieee1 u(e ieee2(td3logic311$42all1 entity binary3to3gray i( *ort(b/4b14b24b35 in bit1g/4g14g24g35 out bit)1 end binary3to3gray1 arc0itecture b3t3g of binary3to3gray i( begin g367b31 g267b3 'or b21 g167b2 'or b11 g/67b1 'or b/1 end b3t3g1

(. VHDL Code For &ray to Binary Code Con'erter By Data Flow Modelling
library ieee1 u(e ieee2(td3logic311$42all1 entity gray3to3binary i( *ort(g/4g14g24g35 in bit1b/4b14b24b35 out bit)1 end gray3to3binary1 arc0itecture g3t3b of gray3to3binary i( begin b367g31 b267g3 'or g21 b167(g3 'or (g2 'or g1))1 b/67(g3 'or (g2 'or (g1 'or g/)))1 end1

). VHDL Code For BCD #o *+!e,,3 Code Con'erter By Data Flow Modelling
library ieee1 u(e ieee2(td3logic311$42all1 entity bcd3to3e'ce((33 i( *ort(b/4b14b24b35 in bit1 e/4e14e24e35 out bit)1 end bcd3to3e'ce((331 arc0itecture bcd3to3e'ce((333dfm of bcd3to3e'ce((33 i( begin e367((b3 or (b2 and b/)) or (b2 and b1))1 e267(((not b2) and b/) or ((not b/) and (b1 'or b2)))1 e167(b1 'nor b/)1 e/67(not b/)1 end bcd3to3e'ce((333dfm1

-. (a) VHDL Code For ".1 Multi/le+er 0,ing 1F2*LS* State$ent,

library ieee1 u(e ieee2(td3logic311$42all1 entity mu'3431 i( *ort((5 in bit3#ector(/ to 1)1 d5 in bit3#ector(/ to 3)1 y5 out bit)1 end mu'34311 arc0itecture mu'34313be0a#ioural3if3el(e of mu'3431 i( begin *roce((((4d) begin if (78//8 t0en y67d(/)1 el(if (78/18 t0en y67d(1)1 el(if (781/8 t0en y67d(2)1 el(e y67d(3)1 end if1 end *roce((1 end mu'34313be0a#ioural3if3el(e1

-. ( ) VHDL Code For ".1 Multi/le+er 0,ing CAS* State$ent,

library ieee1 u(e ieee2(td3logic311$42all1 entity mu'3431 i( *ort((5 in bit3#ector(/ to 1)1 d5 in bit3#ector(/ to 3)1 y5 out bit)1 end mu'34311 arc0itecture mu'34313be0a#ioural3ca(e of mu'3431 i( begin *roce((((4d) begin ca(e ( i( w0en 8//8 79 y67d(/)1 w0en 8/18 79 y67d(1)1 w0en 81/8 79 y67d(2)1 w0en ot0er( 79 y67d(3)1 end ca(e1 end *roce((1 end mu'34313be0a#ioural3ca(e1

3. VHDL Code For 2." De!oder By Data Flow Modelling

library ieee1 u(e ieee2(td3logic311$42all1 entity decoder3234 i( *ort(a4b4e5 in bit1 d/4d14d24d35 out bit)1 end decoder32341 arc0itecture decoder32343dfm of decoder3234 i( begin d/67 (((not a) and (not b)) and e)1 d167 (((not a) and b) and e)1 d267 ((a and (not b)) and e)1 d367 ((a and b) and e)1 end decoder32343dfm1

14.

VHDL Code For 2 Bit Multi/lier By Data Flow Modelling

library ieee1 u(e ieee2(td3logic311$42all1 entity multi*lier323bit i( *ort(a5 in bit3#ector(1 downto /)1b5 in bit3#ector(1 downto /)1 d5 out bit3#ector(3 downto /))1 end multi*lier323bit1 arc0itecture multi*lier323bit3dfm of multi*lier323bit i( (ignal c5 bit1 begin d(/)67(a(/) and b(/))1 d(1)67((a(1) and b(/)) 'or (a(/) and b(1)))1 c67((a(1) and b(/)) and (a(/) and b(1)))1 d(2)67((a(1) and b(1)) 'or c)1 d(3)67((a(1) and b(1)) and c)1 end multi*lier323bit3dfm1

11.

VHDL Code For 2 Bit Co$/arator By Data Flow Modelling

library ieee1 u(e ieee2(td3logic311$42all1 entity com*arator323bit i( *ort(a4b5 in bit3#ector(1 downto /)1 y5 out bit3#ector(2 downto /))1 end com*arator323bit1 arc0itecture com*arator323bit3dfm of com*arator323bit i( begin y(/)67 (((a(1) and (not b(1))) or (a(1) and a(/) and (not b(/)))) or ((not b(1)) and a(/) and (not b(/))))1 y(1)67 ((((not a(1)) and b(1)) or ((not a(1)) and (not a(/)) and b(/))) or (b(1) and (not a(/)) and a(/)))1 y(2)67 ((a(1) 'nor b(1)) and (a(/) 'nor b(/)))1 end com*arator323bit3dfm1

12.

VHDL Code For Half Adder

y Stru!tural Modelling

library ieee1 u(e ieee2(td3logic311$42all1 entity 0alf3adder i( *ort(a4b5 in bit1 (um4carry5 out bit)1 end 0alf3adder1 arc0itecture 0alf3adder3(truct of 0alf3adder i( com*onent 'or1 i( *ort(*4:5 in bit1 r5 out bit)1 end com*onent1 com*onent and1 i( *ort(u4#5 in bit1 w5 out bit)1 end com*onent1 begin '15'or1 *ort ma*(a4b4(um)1 '25and1 *ort ma*(a4b4carry)1 end 0alf3adder3(truct1 entity 'or1 i( *ort(*4:5 in bit1 r5 out bit)1 end 'or11 arc0itecture 'or313dfm of 'or1 i( begin r67* 'or :1 end 'or311 entity and1 i( *ort(u4#5 in bit1 w5 out bit)1 end and11 arc0itecture and313dfm of and1 i( begin w67u and #1 end and311