Micro Controler 8051

A Course on REAL-TIME EMBEDDED SYSTEMS . . .
by Krest Technologies
MICRO CONTROLLER 8051
EMBEDDED SYSTEMS
What Is an Embedded System?
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A Course on REAL-TIME EMBEDDED SYSTEMS . . . by Krest Technologies

An em edded system is a unit 'a*ing $om ination o+ so+t)are and 'ard)are along )it' me$'ani$al parts. A general#purpose de+inition o+ em edded systems is t'at t'ey are de*i$es used to $ontrol, monitor or assist t'e operation o+ e,uipment, ma$'inery or plant.
An embedded system &s des&'ned to (er)orm a ded&cated )*nct&on+ Most em edded de*i$es are primarily designed +or one spe$i+i$ +un$tion. de*i$es su$' as personal data assistant -P.A/0$ell p'one 'y rids, )'i$' are em edded systems designed to e a le to do a *ariety o+ primary +un$tions. digital 12s in$lude intera$ti*e appli$ations t'at per+orm a )ide *ariety o+ general +un$tions unrelated to t'e 3123 +un$tion ut 4ust as important, su$' as e#mail, )e ro)sing, and games.
Character&st&cs o) Embedded Systems:

Reliability: pro a ility o+ system )or&ing $orre$tly Maintainability: pro a ility o+ system )or&ing $orre$tly time units a+ter error o$$urred. Availability: pro a ility o+ system )or&ing at time t Safety: no 'arm to e $aused Security: $on+idential and aut'enti$ $ommuni$ation Energy e++i$ient C !e"#i$e e++i$ient -espe$ially +or systems on a $'ip/ Run"ti%e e++i$ient &eig't e++i$ient C #t e++i$ient (e!icate! to)ards a $ertain a))licati n! 5no)ledge a out e used to minimize resour$es and to ma6imize ro ustness. (e!icate! user interface -no mouse, &ey oard and s$reen/. e'a*ior at design time $an
MICR,-R,CESS,R

A Mi$ropro$essor is +undamentally a $olle$tion o+ on0o++ s)it$'es laid out o*er sili$on in order to per+orm Computations.
C'aracteri#tic# f a Micr )r ce## r: Hig' $ost, Hig' speed, on t'e order o+ 188 MHz 9 :Hz Hig' Po)er $onsumption, lots o+ 'eat ;arge ar$'ite$ture, <7# it, and 69# it ar$'ite$ture ;arge memory size, on oard +las' and $a$'e, )it' an e6ternal us inter+a$e +or greater memory usage. ;ots o+ I0= and perip'erals, t'oug' Mi$ropro$essors tend to e s'ort on :eneral purpose I0=.
MICR,C,.TR,LLER
A mi$ro$ontroller is an entire $omputer manu+a$tured on a single $'ip. 1'ey 'a*e a 'ig' $on$entration o+ on#$'ip +a$ilities su$' as serial ports, parallel input0output ports, timers, $ounters, interrupt $ontrol, analog#to#digital $on*erters, random a$$ess memory, read only memory, et$.
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C'aracteri#tic# f a Micr c ntr ller: ;o) $ost ;o) speed, on t'e order o+ 18 5Hz 78 MHz Small ar$'ite$ture, usually an ># it ar$'ite$ture Small memory size, ut usually enoug' +or t'e type o+ appli$ation it is intended +or =n oard Flas'. ;imited I0=, ut again, enoug' +or t'e type o+ appli$ation. ;o) Po)er, e6tremely lo) po)er in sleep mode.
Choos&n' a m&crocontro//er
1'ere are +our ma4or ># it mi$ro$ontrollers. 1'ey are! Frees$ale?s 6>11, Intel?s >8@1, Ailog?s A>, and PIC 16B +rom Mi$ro$'ip 1e$'nology. "a$' o+ t'ese mi$ro$ontrollers 'as a uni,ue instru$tion set and register setC t'ere+ore, t'ey are not $ompati le )it' ea$' ot'er. Programs )ritten +or one )ill not run on t'e ot'ers. 1'ere are also 16# it and <7# it mi$ro$ontrollers made y *arious $'ip ma&ers. (it' all t'ese di++erent mi$ro$ontrollers, )'at $riteria do designers $onsider in $'oosing oneD 1'ree $riteria in $'oosing mi$ro$ontrollers are as +ollo)s! -1/ meeting t'e $omputing needs o+ t'e tas& at 'and e++i$iently and $ost e++e$ti*ely, -7/ a*aila ility o+ so+t)are de*elopment tools su$' as $ompilers, assem lers, and de uggers, and -</ )ide a*aila ility and relia le sour$es o+ t'e mi$ro$ontr ller. Ee6t )e ela orate +urt'er on ea$' o+ t'e a o*e $riteria. Cr&ter&a )or choos&n' a m&crocontro//er

1'e +irst and +oremost $riterion in $'oosing a mi$ro$ontroller is t'at it must meet t'e tas& at 'and e++i$iently and $ost e++e$ti*ely. In analyzing t'e needs o+ a mi$ro$ontroller# ased pro4e$t, )e must +irst see )'et'er an ># it, 16# it, or <7# it mi$ro$ontroller $an est 'andle t'e $omputing needs o+ t'e tas& most e++e$ti*ely. Among ot'er $onsiderations in t'is $ategory are! 1/ S(eed+ ('at is t'e 'ig'est speed t'at t'e mi$ro$ontroller supportsD i. Pa$&aging. .oes it $ome in a 98#pin .IP -dual inline pa$&age/ or a FFP -,uad +lat pa$&age/, or some ot'er pa$&aging +ormatD 1'is is important in terms o+ spa$e, assem ling, and prototyping t'e end produ$t. Po)er $onsumption. 1'is is espe$ially $riti$al +or attery#po)ered produ$ts.
ii.
7/ 1'e amount o+ GAM and G=M on $'ip. </ 1'e num er o+ I0= pins and t'e timer on t'e $'ip. i. ii. Ho) easy it is to upgrade to 'ig'er#per+orman$e or lo)er po)er $onsumption *ersions. Cost per unit. 1'is is important in terms o+ t'e +inal $ost o+ t'e produ$t in )'i$' a mi$ro$ontroller is used.
,0ER0IEW ,1 T2E "3%! 1AMILY A br&e) h&story o) the "3%!! In 1H>1, Intel Corporation introdu$ed an ># it mi$ro$ontroller $alled t'e >8@1. 1'is mi$ro$ontroller 'ad 17> ytes o+ GAM, 95 ytes o+ on#$'ip G=M, t)o timers, one serial port, and +our ports -ea$' ># its )ide/ all on a single $'ip. At t'e time it )as also re+erred to as a 3system on a $'ip.3 1'e >8@1 is an ># it pro$essor, meaning t'at t'e CPI $an )or& on only > its o+ data at a time. .ata larger t'an > its 'as to e ro&en into ># it pie$es to e pro$essed y t'e CPI. 1'e >8@1 'as a total o+ +our I0= ports, ea$' > its )ide. Alt'oug' t'e >8@1 $an 'a*e a ma6imum o+ 695 ytes o+ on#$'ip G=M, many manu+a$turers 'a*e put only 95 ytes on t'e $'ip.
,ther members o) the "3%! )am&/y! 1'ere are t)o ot'er mem ers in t'e >8@1 +amily o+ mi$ro$ontrollers. 1'ey are t'e >8@7 and t'e >8<1. "3%4 m&crocontro//er! 1'e >8@7 is anot'er mem er o+ t'e >8@1 +amily. 1'e >8@7 'as all t'e standard +eatures o+ t'e >8@1 as )ell as an e6tra 17> ytes o+ GAM and an e6tra timer. In ot'er )ords, t'e >8@7 'as 7@6 ytes o+ GAM and < timers. It also 'as >5 ytes o+ on#$'ip program G=M instead o+ 95 ytes.
1'e >8@1 is a su set o+ t'e >8@7C t'ere+ore, all programs )ritten +or t'e >8@1 )ill run on t'e >8@7, ut t'e re*erse is not true. >8@1 +amily mem ers -e.g, >J@1,>HC@1, >HC@7, .S>HC968/

Ha*e 98 pins dedi$ated +or *arious+un$tions su$' as I0=, #G., #(G, address, data, and interrupts Come in di++erent pa$&ages, su$' as .IP-dual in#line pa$&age/, FFP-,uad +lat pa$&age/, and ;;C-leadless $'ip $arrier/ Some $ompanies pro*ide a 78#pin *ersion o+ t'e >8@1 )it' a redu$ed num er o+ I0= ports +or less demanding appli$ations 1'e >8@1 is t'e original mem er o+ t'e >8@1 +amily. Intel re+ers to it as MCS#@1. 2o5 to 5or6 on embedded system? (e $an di*ide our re,uirements on t)o di++erent sets. !7 2ARDWARE: 1/ Cir$uit .esigning 7/ Cpu sele$tion </ PCB manu+a$turing 9/ Assem ly @/ .e*i$e Programmer 47 S,1TWARE: 1/ Programming language sele$tion 7/ Programming tool ! .epending on $pu sele$ted .e ugger or Simulator.
Some W&de/y 8sed Data Ty(es )or "3%! C!
INTRO(*CTION O+ AT8,C51
A Mi$ro $ontroller $onsists o+ a po)er+ul CPI tig'tly $oupled )it' memory, *arious I0= inter+a$es su$' as serial port, parallel port timer or $ounter, interrupt $ontroller, data a$,uisition inter+a$es#Analog to .igital $on*erter, .igital to Analog $on*erter, integrated on to a single sili$on $'ip. I+ a system is de*eloped )it' a mi$ropro$essor, t'e designer 'as to go +or e6ternal memory su$' as GAM, G=M, "PG=M and perip'erals. But $ontroller is pro*ided all t'ese +a$ilities on a single $'ip. .e*elopment o+ a Mi$ro $ontroller redu$es PCB size and $ost o+ design. =ne o+ t'e ma4or di++eren$es et)een a Mi$ropro$essor and a Mi$ro $ontroller is t'at a $ontroller o+ten deals )it' its not ytes as in t'e real )orld appli$ation. Intel 'as introdu$ed a +amily o+ Mi$ro $ontrollers $alled t'e MCS#@1. The Ma9or 1eat*res: Compati le )it' MCS#@1 produ$ts 9& Bytes o+ in#system Geprogramma le +las' memory Fully stati$ operation! 8HA to 79MHA 1'ree le*el programma le $lo$& 17> K > it timer0$ounters Si6 interrupt sour$es Programma le serial $'annel ;o) po)er idle po)er#do)n modes.
Why AT " C%! 1'e system re,uirements and $ontrol spe$i+i$ations $learly rule out t'e use o+ 16, <7 or 69 it mi$ro $ontrollers or mi$ropro$essors. Systems using t'ese may e earlier to implement due
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to large num er o+ internal +eatures. 1'ey are also +aster and more relia le ut, ># it mi$ro $ontroller satis+a$torily ser*es t'e a o*e appli$ation. Ising an ine6pensi*e ># it Mi$ro$ontroller )ill doom t'e <7# it produ$t +ailure in any $ompetiti*e mar&et pla$e. Coming to t'e ,uestion o+ )'y to use A1>HC@1 o+ all t'e ># it mi$ro$ontroller a*aila le in t'e mar&et t'e main ans)er )ould e e$ause it 'as 9 5 on $'ip +las' memory )'i$' is 4ust su++i$ient +or our appli$ation. 1'e on#$'ip Flas' G=M allo)s t'e program memory to e reprogrammed in system or y $on*entional non#*olatile memory Programmer. Moreo*er A1M"; is t'e leader in +las' te$'nology in todayLs mar&et pla$e and 'en$e using A1 >HC@1 is t'e optimal solution. AT" C%! MICR,C,.TR,LLER ARC2ITECT8RE 1'e >HC@1 ar$'ite$ture $onsists o+ t'ese spe$i+i$ +eatures! "ig't it CPI )it' registers A -t'e a$$umulator/ and B Si6teen# it program $ounter -PC/ and data pointer -.P1G/ "ig't# it sta$& pointer -PS(/ "ig't# it sta$& pointer -Sp/ Internal G=M or "PG=M ->J@1/ o+ 8->8<1/ to 95 ->HC@1/ Internal GAM o+ 17> ytes! !+ Four register an&s, ea$' $ontaining eig't registers 4+ Si6teen ytes, )'i$' may e addressed at t'e it le*el :+ "ig'ty ytes o+ general# purpose data memory 1'irty t)o input0output pins arranged as +our ># it ports!p8#p< 1)o 16# it timer0$ounters! 18 and 11 Full duple6 serial data re$ei*er0transmitter! SBIF Control registers! 1C=E, 1M=., SC=E, PC=E, IP, and I" 1)o e6ternal and t'ree internal interrupts sour$es. =s$illator and $lo$& $ir$uits.
1*nct&ona/ b/oc6 d&a'ram o) m&cro contro//er The " C%! osc&//ator and c/oc6: 1'e 'eart o+ t'e >HC@1 $ir$uitry t'at generates t'e $lo$& pulses y )'i$' all t'e internal all internal operations are syn$'ronized. Pins B1A;1 and B1A;7 is pro*ided +or $onne$ting a resonant net)or& to +orm an os$illator. 1ypi$ally a ,uartz $rystal and $apa$itors are employed. 1'e $rystal +re,uen$y is t'e asi$ internal $lo$& +re,uen$y o+ t'e mi$ro$ontroller. 1'e manu+a$turers ma&e >HC@1 designs t'at run at spe$i+i$ minimum and ma6imum +re,uen$ies typi$ally 1 to 16 MHz.
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,sc&//ator and t&m&n' c&rc*&t Ty(es o) memory: 1'e >HC@1 'a*e t'ree general types o+ memory. 1'ey are on#$'ip memory, e6ternal Code memory and e6ternal Gam. =n#C'ip memory re+ers to p'ysi$ally e6isting memory on t'e mi$ro $ontroller itsel+. "6ternal $ode memory is t'e $ode memory t'at resides o++ $'ip. 1'is is o+ten in t'e +orm o+ an e6ternal "PG=M. "6ternal GAM is t'e Gam t'at resides o++ $'ip. 1'is o+ten is in t'e +orm o+ standard stati$ GAM or +las' GAM. a7 Code memory Code memory is t'e memory t'at 'olds t'e a$tual >HC@1 programs t'at is to e run. 1'is memory is limited to 695. Code memory may e +ound on#$'ip or o++#$'ip. It is possi le to 'a*e 95 o+ $ode memory on#$'ip and 685 o++ $'ip memory simultaneously. I+ only o++#$'ip memory is a*aila le t'en t'ere $an e 695 o+ o++ $'ip G=M. 1'is is $ontrolled y pin pro*ided as "A. b7 Interna/ RAM 1'e >HC@1 'a*e a an& o+ 17> o+ internal GAM. 1'e internal GAM is +ound on#$'ip. So it is t'e +astest Gam a*aila le. And also it is most +le6i le in terms o+ reading and )riting.
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Internal Gam is *olatile, so )'en >HC@1 is reset, t'is memory is $leared. 17> ytes o+ internal memory are su di*ided. 1'e +irst <7 ytes are di*ided into 9 register an&s. "a$' an& $ontains > registers. Internal GAM also $ontains 17> its, )'i$' are addressed +rom 78' to 7F'. 1'ese its are it addressed i.e. ea$' indi*idual it o+ a yte $an e addressed y t'e user. 1'ey are num ered 88' to JF'. 1'e user may ma&e use o+ t'ese *aria les )it' $ommands su$' as S"1B and C;G. 1LAS2 MEM,RY: Flas' memory -sometimes $alled 3+las' GAM3/ is a type o+ $onstantly#po)ered non *olatile t'at $an e erased and reprogrammed in units o+ memory $alled blocks. It is a *ariation o+ ele$tri$ally erasa le programma le read#only memory -""PG=M/ )'i$', unli&e +las' memory, is erased and re)ritten at t'e yte le*el, )'i$' is slo)er t'an +las' memory updating. Flas' memory is o+ten used to 'old $ontrol $ode su$' as t'e asi$ input0output system -BI=S/ in a personal $omputer. ('en BI=S needs to e $'anged -re)ritten/, t'e +las' memory $an e )ritten to in lo$& -rat'er t'an yte/ sizes, ma&ing it easy to update. =n t'e ot'er 'and, +las' memory is not use+ul as random a$$ess memory -GAM/ e$ause GAM needs to e addressa le at t'e yte -not t'e lo$&/ le*el. Flas' memory gets its name e$ause t'e mi$ro$'ip is organized so t'at a se$tion o+ memory $ells are erased in a single a$tion or 3+las'.3 1'e erasure is $aused y Fo)ler#Eord'eim tunneling in )'i$' ele$trons pier$e t'roug' a t'in diele$tri$ material to remo*e an ele$troni$ $'arge +rom a fl ating gate asso$iated )it' ea$' memory $ell. Intel o++ers a +orm o+ +las' memory t'at 'olds t)o its -rat'er t'an one/ in ea$' memory $ell, t'us dou ling t'e $apa$ity o+ memory )it'out a $orresponding in$rease in pri$e. Flas' memory is used in digital $ellular p'ones, digital $ameras, ;AE s)it$'es, PC Cards +or note oo& $omputers, digital set#up o6es, em edded $ontrollers, and ot'er de*i$es. 1eat*res Memory Ty(e 1LAS2 ;o)#$ost, 'ig'#density, 'ig'#speed ar$'ite$tureC lo) po)erC 'ig' relia ility Mature, 'ig'#density, relia le, lo) $ostC time# $onsuming mas& re,uired, suita le +or 'ig' produ$tion )it' sta le $ode
R,M Gead#=nly Memory
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SRAM Stati$ Gandom#A$$ess Memory E-R,M "le$tri$ally Memory Hig'est speed, 'ig'#po)er, lo)#density memoryC limited density dri*es up $ost Hig'#density memoryC must Gead#=nly ultra*iolet lig't +or erasure e e6posed to
Programma le
EE-R,MorE4-R,M "le$tri$ally yte#erasa leC lo)er relia ility, "le$tri$ally "rasa le Programma le Gead# 'ig'er $ost, lo)est density =nly Memory
DRAM .ynami$ Gandom A$$ess Memory
Hig'#density, lo)#$ost, 'ig'#speed, 'ig'# po)er
Techn&ca/ ,;er;&e5 o) 1/ash Memory Flas' memory is a non*olatile memory using E=G te$'nology, )'i$' allo)s t'e user to ele$tri$ally program and erase in+ormation. IntelM Flas' memory uses memory $ells similar to an "PG=M, ut )it' a mu$' t'inner, pre$isely gro)n o6ide et)een t'e +loating gate and t'e sour$e -see Figure 7/. Flas' programming o$$urs )'en ele$trons are pla$ed on t'e +loating gate. 1'e $'arge is stored on t'e +loating gate, )it' t'e o6ide layer allo)ing t'e $ell to e ele$tri$ally erased t'roug' t'e sour$e. Intel Flas' memory is e6tremely relia le non*olatile memory ar$'ite$ture.
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-&n d&a'ram o) AT" C%!
-I. DESCRI-TI,.
0CC: Supply *oltage. <.D: :round.
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-ort 3: Port 8 is an ># it open#drain i#dire$tional I0= port. As an output port, ea$' pin $an sin& eig't 11; inputs. ('en oneLs are )ritten to port 8 pins, t'e pins $an e used as 'ig' impedan$e inputs. Port 8 may also e $on+igured to e t'e multiple6ed lo) order address0data us during a$$esses to e6ternal program and data memory. In t'is mode P8 'as internal pull#ups. Port 8 also re$ei*es t'e $ode ytes during Flas' programming, and outputs t'e $ode ytes during program *eri+i$ation. "6ternal pull#ups are re,uired during program *eri+i$ation. -ort !: Port 1 is an ># it i#dire$tional I0= port )it' internal pull#ups. 1'e Port 1 output u++ers $an sin&0sour$e +our 11; inputs. ('en 1s are )ritten to Port 1 pins t'ey are pulled 'ig' y t'e internal pull#ups and $an e used as inputs. As inputs, Port 1 pins t'at are e6ternally eing pulled lo) )ill sour$e $urrent -II;/ e$ause o+ t'e internal pull#ups. Port 1 also re$ei*es t'e lo)#order address ytes during Flas' programming and *eri+i$ation. -ort 4: Port 7 is an ># it i#dire$tional I0= port )it' internal pull#ups. 1'e Port 7 output u++ers $an sin&0sour$e +our 11; inputs. ('en 1s are )ritten to Port 7 pins t'ey are pulled 'ig' y t'e internal pull#ups and $an e used as inputs. As inputs, Port 7 pins t'at are e6ternally eing pulled lo) )ill sour$e $urrent -II;/ e$ause o+ t'e internal pull#ups. Port 7 emits t'e 'ig'#order address yte during +et$'es +rom e6ternal program memory and during a$$esses to e6ternal data memories t'at use 16# it addresses -M=2B %.P1G/. In t'is appli$ation, it uses strong internal pull#ups )'en emitting 1s. .uring a$$esses to e6ternal data memories t'at use ># it addresses -M=2B % GI/, Port 7 emits t'e $ontents o+ t'e P7 Spe$ial Fun$tion Gegister. Port 7 also re$ei*es t'e 'ig'#order address its and some $ontrol signals during Flas' programming and *eri+i$ation. -ort :: Port < is an ># it i#dire$tional I0= port )it' internal pull#ups. 1'e Port < output u++ers $an sin&0sour$e +our 11; inputs. ('en 1s are )ritten to Port < pins t'ey are pulled 'ig' y t'e internal pull#ups and $an e used as inputs. As inputs, Port < pins t'at are e6ternally eing pulled lo) )ill sour$e $urrent -II;/ e$ause o+ t'e pull#ups. Port < also ser*es t'e +un$tions o+ *arious spe$ial +eatures o+ t'e A1>HC@1 as listed elo)! Port < also re$ei*es some $ontrol signals +or Flas' programming and *eri+i$ation
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-ort (&ns and the&r a/ternate )*nct&ons RST: Geset input. A 'ig' on t'is pin +or t)o ma$'ine $y$les )'ile t'e os$illator is running resets t'e de*i$e.
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ALE=-R,<: Address ;at$' "na le output pulse +or lat$'ing t'e lo) yte o+ t'e address during a$$esses to e6ternal memory. 1'is pin is also t'e program pulse input -PG=:/ during Flas' programming. In normal operation A;" is emitted at a $onstant rate o+ 106t'e os$illator +re,uen$y, and may e used +or e6ternal timing or $lo$&ing purposes. Eote, 'o)e*er, t'at one A;" pulse is s&ipped during ea$' a$$ess to e6ternal .ata Memory. I+ desired, A;" operation $an e disa led y setting it 8 o+ SFG lo$ation >"H. (it' t'e it set, A;" is a$ti*e only during a M=2B or M=2C instru$tion. =t'er)ise, t'e pin is pulled 'ig'. Setting t'e A;"#disa le it 'as no e++e$t i+ t'e mi$ro$ontroller is in e6ternal e6e$ution mode. -SE.: Program Store "na le is t'e read stro e to e6ternal program memory. ('en t'e A1>HC@1 is e6e$uting $ode +rom e6ternal program memory, PS"E is a$ti*ated t)i$e ea$' ma$'ine $y$le, e6$ept t'at t)o PS"E a$ti*ations are s&ipped during ea$' a$$ess to e6ternal data memory. EA=0--: "6ternal A$$ess "na le "A must e strapped to :E. in order to ena le t'e de*i$e to +et$' $ode +rom e6ternal program memory lo$ations starting at 8888H up to FFFFH. Eote, 'o)e*er, t'at i+ lo$& it 1 is programmed, "A )ill e internally lat$'ed on reset. "A s'ould e strapped to 2CC +or internal program e6e$utions. 1'is pin also re$ei*es t'e 17#*olt programming ena le *oltage -2PP/ during Flas' programming, +or parts t'at re,uire 17#*olt 2PP. >TAL!: Input to t'e in*erting os$illator ampli+ier and input to t'e internal $lo$& operating $ir$uit. >TAL4: It is t'e =utput +rom t'e in*erting os$illator ampli+ier. ,sc&//ator Character&st&cs: B1A;1 and B1A;7 are t'e input and output, respe$ti*ely, o+ an in*erting ampli+ier )'i$' $an e $on+igured +or use as an on#$'ip os$illatorC "it'er a ,uartz $rystal or $erami$ resonator may e used. 1o dri*e t'e de*i$e +rom an e6ternal $lo$& sour$e, B1A;7 s'ould e le+t un$onne$ted )'ile B1A;1 is dri*en. 1'ere are no re,uirements on t'e duty $y$le o+ t'e e6ternal $lo$& signal, sin$e t'e input to t'e internal $lo$&ing $ir$uitry is t'roug' a di*ide# y#t)o +lip#+lop, ut minimum and ma6imum *oltage 'ig' and lo) time spe$i+i$ations must e o ser*ed.
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Inder steady state -non#transient/ $onditions, I=; must e e6ternally limited as +ollo)s! Ma6imum I=; per port pin! 18 mA Ma6imum I=; per ># it port! Port 8! 76 mA Ports 1, 7, <! 1@ mA Ma6imum total I=; +or all output pins! J1 mA I+ I=; e6$eeds t'e test $ondition, 2=; may e6$eed t'e related spe$i+i$ation. Pins are not guaranteed to sin& $urrent greater t'an t'e listed test $onditions. Minimum 2CC +or Po)er#do)n is 72.
4.
E>AM-LE -R,<RAM
!+ Wr&te an "3%! C (ro'ram to send ;a/*es 33 ? 11 to (ort -!+ Nin$lude Oreg@1.'P *oid main-*oid/ Q unsigned $'ar zC +or -zR8CzOR7@@CzSS/ P1RzC T
1>

4+ Wr&te an "3%! C (ro'ram to to''/e b&t D3 o) the (ort -!@-!+37 %3A333 t&mes+ Nin$lude Oreg@1.'P s it MUBI1RP1V8C *oid main-*oid/ Q unsigned int zC +or -zR8CzOR@8888CzSS/ Q MUBI1R8C MUBI1R1C T T :+ Wr&te a -ro'ram to s5&tch ,11 and ,. the LEDBs 6ee( &t *(to % *s *s&n' by de/ay )*nct&on? Nin$ludeOreg@1.'P *oid .elay-*oid/C *oid main -/ Q P7 R86FFC .elay -/C 00Ma&ing P7 port to get 'ig' logi$ 00&eeping P7 to @ us as a 'ig' logi$ y generating delay 00using y delay +un$tion P7 R 8688C .elay -/C 00Ma&ing P7 port to get lo) logi$ 00&eeping P7 to @ us as a lo) logi$ y generating delay 00 using y delay +un$tion
00adding >8@1 ar$'ite$ture support +ile to sour$e program 00delay +un$tion de$laration at start o+ program
1H

T *oid .elay-*oid/ Q unsigned int iC +or -iR8C iO@C iSS/C T
RE<ISTERS
In t'e CPI, registers are used to store in+ormation temporarily. 1'at in+ormation $ould e a yte o+ data to e pro$essed, or an address pointing to t'e data to e +et$'ed. 1'e *ast ma4ority o+ >8@1 registers are > it registers. In t'e >8@1 t'ere is only one data type! > its. 1'e > its o+ a register are s'o)n in t'e diagram +rom t'e MSB -most signi+i$ant it/ .J to t'e ;SB -least signi+i$ant it/ .8. (it' an ># it data type, any data larger t'an > its must e ro&en into ># it $'un&s e+ore it is pro$essed. Sin$e t'ere are a large num er o+ registers in t'e >8@1, )e )ill $on$entrate on some o+ t'e )idely used general#purpose registers and $o*er spe$ial registers in +uture $'apters. DC D# D% D$ D: D4 D! D3
1'e most )idely used registers o+ t'e >8@1 are A -a$$umulator/, B, G8, G1, G7, G<, G9, G@, G6, GJ, .P1G -data pointer/, and PC -program $ounter/. All o+ t'e a o*e registers are ># its, e6$ept .P1G and t'e program $ounter. 1'e a$$umulator, register A, is used +or all arit'meti$ and logi$ instru$tions.
S1Rs @S(ec&a/ 1*nct&on Re'&sters7 Among t'e registers G8#GJ is part o+ t'e 17> ytes o+ GAM memory. ('at a out registers A, B, PS(, and .P1GD .o t'ey also 'a*e addressesD 1'e ans)er is yes. In t'e >8@1, registers A, B, PS( and .P1G are part o+ t'e group o+ registers $ommonly re+erred to as SFG -spe$ial +un$tion registers/. 1'ere are many spe$ial +un$tion registers and t'ey are )idely used. 1'e SFG $an e a$$essed y t'e names -)'i$' is mu$' easier/ or y t'eir addresses. For e6ample, register A 'as address "8', and register B 'as een ignited t'e address F8H. 1'e +ollo)ing t)o points s'ould noted a out t'e SFG addresses.
78

!7 1'e Spe$ial +un$tion registers 'a*e addresses et)een >8H and FFH. 1'ese addresses are a o*e >8H, sin$e t'e addresses 88 to JFH are addresses o+ GAM memory inside t'e >8@1. 47 Eot all t'e address spa$e o+ >8H to FFH is used y t'e SFG. 1'e unused lo$ations >8H to FFH are reser*ed and must not e used y t'e >8@1 programmer. Gegarding dire$t addressing mode, noti$e t'e +ollo)ing t)o points! @a7 1'e address *alue is limited to one yte, 88#FFH, )'i$' means t'is addressing mode is limited to a$$essing GAM lo$ations and registers lo$ated inside t'e >8@1. @b7 I+ you e6amine t'e l st +ile +or an assem ly language program, you )ill see t'at t'e SFG registers names are repla$ed )it' t'eir addresses as listed in ta le. Symbo/ ACC B PS( SP .P1G .P; .PH P8 P1 P7 P< IP I" 1M=. 1C=E 17C=E 17M=. 1H8 1;8 1H1 1;1 1H7 1;7 GCAP7H GCAP7; SC=E SBIF PC=E .ame A$$umulator B register Program status )ord Sta$& pointer .ata pointer 7 ytes ;o) yte Hig' yte Port8 Port1 Port7 Port< Interrupt priority $ontrol Interrupt ena le $ontrol 1imer0$ounter mode $ontrol 1imer0$ounter $ontrol 1imer0$ounter 7 $ontrol 1imer0$ounter mode7 $ontrol 1imer0$ounter 8'ig' yte 1imer0$ounter 8 lo) yte 1imer0$ounter 1 'ig' yte 1imer0$ounter 1 lo) yte 1imer0$ounter 7 'ig' yte 1imer0$ounter 7 lo) yte 10C 7 $apture register 'ig' yte 10C 7 $apture register lo) yte Serial $ontrol Serial data u++er Po)er $ontrol Address 8"8H 8F8H 8.8H >1H >7H ><H >8H H8H 8A8H 8B8H 8B>H 8A>H >HH >>H 8C>H 8CHH >CH >AH >.H >BH 8C.H 8CCH 8CBH 8CAH H>H HHH >JH
71

"3%! S(ec&a/ )*nct&on re'&ster Address
A @Acc*m*/ator7 Re'&ster:
1'is is a general#purpose register )'i$' ser*es +or storing intermediate results during operating. A num er -an operand/ s'ould e added to t'e a$$umulator prior to e6e$ute an instru$tion upon it. =n$e an arit'meti$al operation is per+ormed y t'e A;I, t'e result is pla$ed into t'e a$$umulator. I+ a data s'ould e trans+erred +rom one register to anot'er, it must go t'roug' a$$umulator. For su$' uni*ersal purpose, t'is is t'e most $ommonly used register t'at none mi$ro$ontroller $an e imagined )it'out -more t'an a 'al+ >8@1 mi$ro$ontroller?s instru$tions used use t'e a$$umulator in some )ay/. B Re'&ster: B register is used during multiply and di*ide operations )'i$' $an e per+ormed only upon num ers stored in t'e A and B registers. All ot'er instru$tions in t'e program $an use t'is register as a spare a$$umulator -A/.
.uring programming, ea$' o+ registers is $alled y name so t'at t'eir e6a$t address is not so important +or t'e user. .uring $ompiling into ma$'ine $ode -series o+ 'e6ade$imal num ers re$ognized as instru$tions y t'e mi$ro$ontroller/, PC )ill automati$ally, instead o+ registersL name, )rite ne$essary addresses into t'e mi$ro$ontroller. R Re'&sters @R3-RC7:
77
1'is is a $ommon name +or t'e total > general purpose registers -G8, G1, and G7 ...GJ/. "*en t'ey are not true SFGs, t'ey deser*e to e dis$ussed 'ere e$ause o+ t'eir purpose. 1'e an& is a$ti*e )'en t'e G registers it in$ludes are in use. Similar to t'e a$$umulator, t'ey are used +or temporary storing *aria les and intermediate results. ('i$' o+ t'e an&s )ill e a$ti*e depends on t)o its in$luded in t'e PS( Gegister. 1'ese registers are stored in +our an&s in t'e s$ope o+ GAM. 1'e +ollo)ing e6ample est illustrates t'e use+ul purpose o+ t'ese registers. Suppose t'at mat'emati$al operations on num ers pre*iously stored in t'e G registers s'ould e per+ormed! -G1SG7/ # -G<SG9/. = *iously, a register +or temporary storing results o+ addition is needed. "*eryt'ing is ,uite simple and t'e program is as +ollo)s! M,0 AA R:D Means! mo*e num er +rom G< into a$$umulator ADD AA R$D Means! add num er +rom G9 to a$$umulator -result remains in a$$umulator/ M,0 R%A AD Means! temporarily mo*es t'e result +rom a$$umulator into G@ M,0 AA R!D Means! mo*e num er +rom G1 into a$$umulator
7<

ADD AA R4D Means! add num er +rom G7 to a$$umulator S8BB AA R%D Means! su tra$t num er +rom G@ -t'ere are G<SG9/ "3%! Re'&ster Ban6s and Stac6: RAM memory s(ace a//ocat&on &n the "3%! 1'ere are 17> ytes o+ GAM in t'e >8@1. 1'e 17> ytes o+ GAM inside t'e >8@1 are assigned addresses 88 toJFH. 1'ese 17> ytes are di*ided into t'ree di++erent groups as +ollo)s! !+ A total o+ <7 ytes +rom lo$ations 88 to 1FH 'e6 are set aside +or register an&s and t'e sta$&. 4+ A total o+ 16 ytes +rom lo$ations 78 to 7FH 'e6 are set aside +or it#addressa le read0)rite memory. :+ A total o+ >8 ytes +rom lo$ations <8H to JFH are used +or read and )rite storage, or )'at is normally $alled S$rat$' pad. 1'ese >8 lo$ations o+ GAM are )idely used +or t'e purpose o+ storing data and parameters use >8@1 programmers. Re'&ster ban6s &n the "3%!: A total o+ <7 ytes o+ GAM are set aside +or t'e register an&s and sta$&. 1'ese <7 ytes are di*ided into 9 an&s o+ registers in )'i$' ea$' an& 'as registers, G8#GJ. GAM lo$ations 8 to J are set aside +or an& 8 o+ G8#GJ )'ere G8 is GAM lo$ation 8, G1 is GAM lo$ation 1, and G7 is lo$ation 7, and so on, until memory lo$ationJ, )'i$' elongs to GJ o+ an&8. 1'e se$ond an& o+ registers G8#GJ starts at GAM lo$ation 8> and goes to lo$ation 8FH. 1'e t'ird an& o+ G8#GJ starts at memory lo$ation 18H and goes to lo$ation 1JH. Finally, GAM lo$ations 1>H to 1FH are set aside +or t'e +ourt' an& o+ G8#GJ. Fig s'o)s 'o) t'e <7 ytes are allo$ated into 9 an&s. 1'e an& 1 uses t'e same GAM spa$e as t'e sta$&. 1'is is a ma4or pro lem in programming t'e >8@1. (e must eit'er not use register an&1, or allo$ate anot'er area o+ GAM +or t'e sta$&. De)a*/t re'&ster ban6: I+ GAM lo$ations 88#1F are set aside +or t'e +our register an&s, )'i$' register an& o+ G8#GJ do )e 'a*e a$$ess to )'en t'e >8@1 is po)ered upD 1'e ans)er is register an& 8C t'at is , GAM lo$ations 8, 1,7,<,9,@,6, and J are a$$essed )it' t'e names G8, G1, G7, G<, G9, G@, G6, and GJ )'en programming t'e >8@1. It is mu$' easier to re+er to t'ese GAM lo$ations )it' names su$' as G8, G1 and so on, t'an y t'eir memory lo$ations. 1'e register an&s are s)it$'ed y using t'e .< W .9 its o+ register PS(.
79
RAM A//ocat&on &n the "3%!
7@

-SW Re'&ster @-ro'ram Stat*s Word7
1'is is one o+ t'e most important SFGs. 1'e Program Status (ord -PS(/ $ontains se*eral status its t'at re+le$t t'e $urrent state o+ t'e CPI. 1'is register $ontains! Carry it, Au6iliary Carry, t)o register an& sele$t its, =*er+lo) +lag, parity it, and user#de+ina le status +lag. 1'e A;I automati$ally $'anges some o+ registerLs its, )'i$' is usually used in regulation o+ t'e program per+orming. - - -ar&ty b&t+ I+ a num er in a$$umulator is e*en t'en t'is it )ill e automati$ally set -1/, ot'er)ise it )ill e $leared -8/. It is mainly used during data transmission and re$ei*ing *ia serial $ommuni$ation. - B&t !: 1'is it is intended +or t'e +uture *ersions o+ t'e mi$ro$ontrollers, so it is not supposed to e 'ere. ,0 ,;er)/o5! =$$urs )'en t'e result o+ arit'meti$al operation is greater t'an 7@@ -de$imal/, so t'at it $annot e stored in one register. In t'at $ase, t'is it )ill e set -1/. I+ t'ere is no o*er+lo), t'is it )ill e $leared -8/. RS3A RS! - Re'&ster ban6 se/ects b&ts+ 1'ese t)o its are used to sele$t one o+ t'e +our register an&s in GAM. By )riting zeroes and ones to t'ese its, a group o+ registers G8#GJ is stored in one o+ +our an&s in GAM.
RS! 8 8 1
RS4 8 1 8
S(ace &n RAM Ban&8 88'#8J' Ban&1 8>'#8F' Ban&7 18'#1J'
76

1 1 Ban&< 1>'#1F'
13 - 1/a' 3+ 1'is is a general#purpose it a*aila le to t'e user. AC - A*E&/&ary Carry 1/a' is used +or BC. operations only. CY - Carry 1/a' is t'e -nint'/ au6iliary it used +or all arit'meti$al operations and s'i+t instru$tions. D-TR Re'&ster @Data -o&nter7: 1'ese registers are not true ones e$ause t'ey do not p'ysi$ally e6ist. 1'ey $onsist o+ t)o separate registers! .PH -.ata Pointer Hig'/ and -.ata Pointer ;o)/. 1'eir 16 its are used +or e6ternal memory addressing. 1'ey may e 'andled as a 16# it register or as t)o independent ># it registers. Besides, t'e .P1G Gegister is usually used +or storing data and intermediate results )'i$' 'a*e not'ing to do )it' memory lo$ations.
S- Re'&ster @Stac6 -o&nter7:
7J

1'e sta$& is a se$tion o+ GAM used y t'e CPI to store in+ormation temporarily. 1'is in+ormation $ould e data or an address. 1'e CPI needs t'is storage area sin$e t'ere are only a limited num er o+ registers. 2o5 stac6s are accessed &n the "3%! I+ t'e sta$& is a se$tion o+ GAM, t'ere must e registers inside t'e CPI to point to it. 1'e register used to a$$ess t'e sta$& is $alled t'e SP -Sta$& point/ Gegister. 1'e sta$& pointer in t'e >8@1 is only > its )ideC )'i$' means t'at it $an ta&e *alues o+ 88 to FFH. ('en t'e >8@1 is po)ered up, t'e SP register $ontains *alue 8J. 1'is means t'at GAM lo$ation 8> is t'e +irst lo$ation used +or t'e sta$& y t'e >8@1. 1'e storing o+ a CPI register in t'e sta$& is $alled a PISH, and pulling t'e $ontents o++ t'e sta$& a$& into a CPI register is $alled a P=P. In ot'er )ords, a register is pus'ed onto t'e sta$& to sa*e it and popped o++ t'e sta$& to retrie*e it. 1'e 4o o+ t'e SP is *ery $riti$al )'en pus' and pop a$tions are per+ormed. -*sh&n' onto the stac6 In t'e >8@1 t'e sta$& pointer -SP/ points to t'e last used lo$ation o+ t'e sta$&. As )e pus' data onto t'e sta$&, t'e sta$& pointer is in$remented y one. Eoti$e t'at t'is di++erent +rom many mi$ropro$essors, nota ly 6>6 pro$essors in )'i$' t'e SP is de$remented )'en data is pus'ed onto t'e sta$&. As ea$' PISH is e6e$uted, t'e $ontents o+ t'e register are sa*ed on t'e sta$& and SP is in$remented y 1. Eoti$e t'at +or e*ery yte o+ data sa*ed on t'e sta$& and t'en SP is in$remented only on$e. Eoti$e also t'at to pus' t'e registers onto t'e sta$& )e must use t'eir GAM addresses. For e6ample, t'e instru$tion XPISHY pus'es register G1 onto t'e sta$&.
-o((&n' )rom the stac6 Popping t'e $ontents o+ t'e sta$& a$& into a gi*en register is t'e opposite pro$ess o+ pus'ing. (it' e*ery pop, t'e top yte o+ t'e sta$& is $opied to t'e register spe$i+ied y t'e instru$tion and t'e sta$& pointer is de$remented on$e. The *((er /&m&t o) the stac6 As, mentioned earlier, lo$ations 8> to 1FH in t'e >8@1 GAM $an e used +or t'e sta$&. 1'is is e$ause lo$ations 78#7FH o+ GAM are reser*ed +or it#addressa le memory and must not e used y t'e sta$&. I+ in a program )e need more t'an 79 ytes -8> to 1FHR79 ytes/ o+ sta$&, )e $an $'ange t'e SP to point to GAM lo$ations <8#JFH. 1'is is done )it' t'e instru$tion XM=2 SP, NBBY. -3A -!A -4A -: - In(*t=,*t(*t Re'&sters
7>
In $ase t'at e6ternal memory and serial $ommuni$ation system are not in use t'en, 9 ports )it' in total o+ <7 input#output lines are a*aila le to t'e user +or $onne$tion to perip'eral en*ironment. "a$' it inside t'ese ports $orresponds to t'e appropriate pin on t'e mi$ro$ontroller. 1'is means t'at logi$ state )ritten to t'ese ports appears as a *oltage on t'e pin -8 or @ 2/. Eaturally, )'ile reading, t'e opposite o$$urs *oltage on some input pins is re+le$ted in t'e appropriate port it. 1'e state o+ a port it, esides eing re+le$ted in t'e pin, determines at t'e same time )'et'er it )ill e $on+igured as input or output. I+ a it is $leared -8/, t'e pin )ill e $on+igured as output. In t'e same manner, i+ a it is set to 1 t'e pin )ill e $on+igured as input. A+ter reset, as )ell as )'en turning t'e mi$ro$ontroller =E, all its on t'ese ports are set to one @!7. 1'is means t'at t'e appropriate pins )ill e $on+igured as &n(*ts.
-C @-ro'ram co*nter7: 1'e important register in t'e >8@1 is t'e PC -Program $ounter/. 1'e program $ounter points to t'e address o+ t'e ne6t instru$tion to e e6e$uted. As t'e CPI +et$'es t'e =PC=." +rom t'e program G=M, t'e program $ounter is in$remented to point to t'e ne6t instru$tion. 1'e program $ounter in t'e >8@1 is 16 its )ide. 1'is means t'at t'e >8@1 $an a$$ess program addresses 8888 to FFFFH, a total o+ 69& ytes o+ $ode. Ty(es o) &nstr*ct&ons .epending on operation t'ey per+orm, all instru$tions are di*ided in se*eral groups!

Arit'meti$ Instru$tions Bran$' Instru$tions .ata 1rans+er Instru$tions ;ogi$al Instru$tions ;ogi$al Instru$tions )it' its
7H

1'e +irst part o+ ea$' instru$tion, $alled ME"M=EIC re+ers to t'e operation an instru$tion per+orms -$opying, addition, logi$al operation et$./. Mnemoni$s $ommonly are s'ortened +orm o+ name o+ operation eing e6e$uted. For e6ample! I.CR1: In$rement G1 -in$rement register G1/ LJMP LAB5: ;ong Zump ;AB@ -long 4ump to address spe$i+ied as ;AB@/ JNZ LOOP: Zump i+ Eot Aero ;==P -i+ t'e num er in t'e a$$umulator is not 8, 4ump to address spe$i+ied as ;==P/ Anot'er part o+ instru$tion, $alled =P"GAE. is separated +rom mnemoni$ at least y one empty spa$e and de+ines data eing pro$essed y instru$tions. Some instru$tions 'a*e no operandC some 'a*e one, t)o or t'ree. I+ t'ere is more t'an one operand in instru$tion, t'ey are separated y $omma. RET -return +rom su #routine/ JZ TEMP - -i+ t'e Eo. in t'e a$$umulator is not 8, 4ump to address spe$i+ied as 1"MP/ ADD A,R3 -add G< and a$$umulator/ CJNE A,#20,LOOP - -$ompare a$$umulator )it' 78. I+ t'ey are not e,ual, 4ump to address spe$i+ied as ;==P/ Ar&thmet&c &nstr*ct&ons: 1'ese instru$tions per+orm se*eral asi$ operations -addition, su tra$tion, di*ision, multipli$ation et$./ A+ter e6e$ution, t'e result is stored in t'e +irst operand. ADD A, R1 - 1'e result o+ addition -ASG1/ )ill e stored in t'e a$$umulator. Ar&thmet&ca/ Instr*ct&ons Byte .*mber 1 ,sc&//ator -er&od 1
Mnemon&c
Descr&(t&on
A.. A,Gn
Add G Gegister to a$$umulator Add dire$tly addressed G6 Gegister to a$$umulator Add indire$tly addressed Gegister to a$$umulator
A.. A,G6
A.. A,%Gi
<8

A.. A,NB A..C A,Gn Add num er B to a$$umulator Add G Gegister )it' Carry it to a$$umulator 7 1 7 1
Branch Instr*ct&ons: 1'ere are t)o &inds o+ t'ese instru$tions! 8ncond&t&ona/ 9*m( &nstr*ct&ons: A+ter t'eir e6e$ution a 4ump to a ne) lo$ation +rom )'ere t'e program $ontinues e6e$ution is e6e$uted. Cond&t&ona/ 9*m( &nstr*ct&ons: I+ some $ondition is met # a 4ump is e6e$uted. =t'er)ise, t'e program normally pro$eeds )it' t'e ne6t instru$tion. Branch Instr*ct&on Mnemon&c Descr&(t&on Byte .*mber ,sc&//ator -er&od
ACA;; adr11
Call su routine lo$ated at address )it'in 7 5 yte Program Memory spa$e Call su routine lo$ated at any address )it'in 69 5 yte Program Memory spa$e Geturn +rom su routine Geturn +rom interrupt routine Zump to address lo$ated )it'in 7 5 yte Program Memory spa$e Zump to any address lo$ated )it'in 69 5 yte Program Memory spa$e
<
;CA;; adr16 G"1 G"1I AZMP adr11
< 1 1 7
9 9 9 <
;ZMP adr16
<
Data Trans)er Instr*ct&ons
<1

1'ese instru$tions mo*e t'e $ontent o+ one register to anot'er one. 1'e register )'i$' $ontent is mo*ed remains un$'anged. I+ t'ey 'a*e t'e su++i6 XBY -M=2B/, t'e data is e6$'anged )it' e6ternal memory. Data Trans)er Instr*ct&on Mnemon&c Descr&(t&on Byte .*mber 1 Cyc/e .*mber 1
M=2 A,Gn
Mo*e G register to a$$umulator
M=2 A,G6
Mo*e dire$tly addressed G6 register to a$$umulator
M=2 A,%Gi
Mo*e indire$tly addressed register to a$$umulator
M=2 A,NB
Mo*e num er B to a$$umulator
Lo'&ca/ Instr*ct&ons 1'ese instru$tions per+orm logi$al operations et)een $orresponding its o+ t)o registers. A+ter e6e$ution, t'e result is stored in t'e +irst operand. Lo'&ca/ Instr*ct&ons Mnemon&c Descr&(t&on Byte .*mber Cyc/e .*mber 1
AE; A,Gn
;ogi$al AE. et)een a$$umulator and G register
AE; A,G6
;ogi$al AE. et)een a$$umulator and dire$tly addressed register G6
<7
AE; A,%Gi
;ogi$al AE. et)een a$$umulator and indire$tly addressed register
AE; A,NB
;ogi$al AE. et)een a$$umulator and num er B
Lo'&ca/ ,(erat&ons on B&ts Similar to logi$al instru$tions, t'ese instru$tions per+orm logi$al operations. 1'e di++eren$e is t'at t'ese operations are per+ormed on single its. Lo'&ca/ o(erat&ons on b&ts Cyc/e .*mber 1 7 1 7
Mnemon&c
Descr&(t&on
Byte .*mber
C;G C C;G it S"1B C S"1B it
Clear Carry it Clear dire$tly addressed it Set Carry it Set dire$tly addressed it
1 7 1 7
CP; C
Complement Carry it
CP; it
Complement dire$tly addressed it
<<
TIMERS
=n#$'ip timing0$ounting +a$ility 'as pro*ed t'e $apa ilities o+ t'e mi$ro$ontroller +or implementing t'e real time appli$ation. 1'ese in$ludes pulse $ounting, +re,uen$y measurement, pulse )idt' measurement, aud rate generation,et$., Ha*ing su++i$ient num er o+ timer0$ounters may e a need in a $ertain design appli$ation. 1'e >8@1 'as t)o timers0$ounters. 1'ey $an e used eit'er as timers to generate a time delay or as $ounters to $ount e*ents 'appening outside t'e mi$ro$ontroller. -R,<RAMMI.< "3%! TIMERS The "3%! has t5o t&mers=co*ntersA they can be *sed e&ther as 1imers to generate a time delay or as "*ent $ounters to $ount e*ents 'appening outside t'e mi$ro$ontroller
BASIC RI<ISTERS ,1 T2E TIMER: Bot' 1imer 8 and 1imer 1 are 16 its )ide. Sin$e >8@1 'as an ># it ar$'ite$ture, ea$' 16# its timer is a$$essed as t)o registers o+ lo) yte and 'ig' yte. Accessed as /o5 byte and h&'h byte 1'e lo) yte register is $alled 1;8 0 1;1 and 1'e 'ig' yte register is $alled 1H8 0 1H1. separate
<9
TIMER 3 RE<ISTERS 1'e 16# it register o+ 1imer 8 is a$$essed as lo) yte and 'ig' yte. t'e lo) yte register is $alled 1;8 -1imer 8 lo) yte/and t'e 'ig' yte register is re+erred to as 1H8 -1imer 8 'ig' yte/.1'ese register $an e a$$essed li&e any ot'er register, su$' as A, B, G8, G1, G7,et$. For "6ample, t'e instru$tion YM=2 1;8, N9FYmo*es t'e *alue 9FH into 1;8,t'e lo) yte o+ 1imer 8.1'ese registers $an also e read li&e any ot'er register.
TIMER ! RE<ISTERS 1imer 1 is also 16# it register is split into t)o ytes, re+erred to as 1;1 -1imer 1 lo) yte/ and 1H1 -1imer 1 'ig' yte/.t'ese registers are a$$essi le n t'e same )ay as t'e register o+ 1imer 8. TM,D @T&mer Mode7 RE<ISTER Bot' timers 1IM"G 8 and 1IM"G 1 use t'e same register, $alled 1M=., to set t'e *arious timer operation modes. 1M=. is an ># it register in )'i$' t'e lo)er 9 its are set aside +or 1imer 8 and t'e upper 9 its +or 1imer 1.in ea$' $aseC t'e lo)er 7 its are used to set t'e timer mode and t'e upper 7 its to spe$i+y t'e operation.
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M,DES @ M! A M37 : M8 and M1 are used to sele$t t'e timer mode. 1'ere are t'ree modes! 8, 1, 7. Mode 8 is a 1<# it timer, mode 1 is a 16# it timer, and mode 7 is an ># it timer. (e )ill $on$entrate on modes 1 and 7 sin$e t'ey are t'e ones used most )idely. (e )ill soon des$ri e t'e $'ara$teristi$s o+ t'ese modes, a+ter des$ri ing t'e reset o+ t'e 1M=. register. <ATE :ate $ontrol )'en set. 1'e timer0$ounter is ena led only )'ile t'e IE16 pin is 'ig' and t'e 1G6 $ontrol pin is Set. ('en $leared, t'e timer is ena led. 1imer or $ounter sele$ted $leared +or timer operation -Input +rom internal system $lo$&/.set +or $ounter =peration -input 1B input pin/. Mode it 1 Mode it 8
C=T
M! M3
M! 8
M3 8
M,DE 8
,(erat&n' Mode 1<# it timer mode ># it timer0$ounter 1H6 )it' 1;6 as @ # Bit pre#s$aler 16# it timer mode 16# it timer0$ounters 1H6 )it' 1;6 are Cas$adedC t'ere is no pres$aler ># it auto reload ># it auto reload timer0$ounterC 1H6 Holds a *alue t'at is to e reloaded into 1;6 ea$' time it o*er+lo)s.
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1 1 < Split timer mode
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<ATE:
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T&mers o) "3%! do start&n' and sto((&n' by e&ther so)t5are or hard5are contro/ In using so+t)are to start and stop t'e timer )'ere :A1"R8 1'e start and stop o+ t'e timer are $ontrolled y )ay o+ so+t)are y t'e 1G -timer start/ its 1G8 and 1G1 1'e S"1B instru$tion starts it, and it is stopped y t'e C;G instru$tion 1'ese instru$tions start and stop t'e timers as long as :A1"R8 in t'e 1M=. register 1'e 'ard)are )ay o+ starting and stopping t'e timer y an e6ternal sour$e is a$'ie*ed y ma&ing :A1"R1 in t'e 1M=. register I+ :A1" R 1, t'e start and stop o+ t'e timer are done e6ternally t'roug' pins P<.7 W P<.< +or timers 8 and 1, respe$ti*ely. 1'is 'ard)are )ay allo)s to start or stop t'e timer e6ternally at any time *ia a simple s)it$'
C=T @c/oc6=t&mer7 1'is it in t'e 1M=. register is used to de$ide )'et'er t'e timer is used as a delay generator or an e*ent $ounter. I+ C01R8, it is used as a timer +or time delay generation. 1'e $lo$& sour$e +or t'e time delay is t'e $rystal +re,uen$y o+ t'e >8@1. As yo* 6no5A e;ery t&mer needs a c/oc6 (*/se to t&c6+ What &s the so*rce o) the c/oc6 (*/se )or the "3%! t&mers? I+ C01R8, t'e $rystal +re,uen$y atta$'ed to t'e >8@1 is t'e sour$e o+ t'e $lo$& +or t'e timer. 1'is means t'at t'e size o+ t'e $rystal +re,uen$y atta$'ed to t'e >8@1 also de$ides t'e speed at )'i$' t'e >8@1 timer ti$&s. 1'e +re,uen$y +or t'e timer is al)ays 1017t' t'e +re,uen$y o+ t'e $rystal atta$'ed to t'e >8@1.
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Alt'oug' *arious >8@1# ased systems 'a*e an B1A; +re,uen$y o+ 18MHz,)e )ill $on$entrate on t'e B1A; +re,uen$y o+ 11.8@H7MHz. 1'e reason e'ind su$' an odd num er 'as to do )it' t'e aud rate +or serial $ommuni$ation o+ t'e >8@1. B1A; R11.8@H7MHz allo)s t'e >8@1 system to $ommuni$ate )it' t'e PC )it' no errors. 1imers $an also e used as $ounters $ounting e*ents 'appening outside t'e >8@1 ('en it is used as a $ounter, it is a pulse outside o+ t'e >8@1 t'at in$rements t'e 1H, 1; registers. 1M=. and 1H, 1; registers are t'e same as +or t'e timer
1'e C01 it in t'e 1M=. registers de$ides t'e sour$e o+ t'e $lo$& +or t'e timer. ('en C01 R 1, t'e timer is used as a $ounter and gets its pulses +rom outside t'e >8@1. 1'e $ounter $ounts up as pulses are +ed +rom pins 19 and 1@, t'ese pins are $alled 18 -timer 8 input/ and 11 -timer 1 input/.
E>AM-LE -R,<RAMS
!+ Wr&te an "3%! C (ro'ram to to''/e a// the b&ts o) (ort -! cont&n*o*s/y 5&th some de/ay &n bet5een+ 8se T&mer3A !#-b&t mode to 'enerate the de/ay+
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Nin$lude Oreg@1.'P *oid 18.elay-*oid/C *oid main -*oid/ Q )'ile -1/ Q P1R86@@C 18.elay-/C P1R86AAC 18.elay-/C T T *oid 18.elay- / Q 1M=.R8681C 1;8R8688C 1H8R86<@C 1G8R1C )'ile -1F8RR8/C 1G8R8C 1F8R8C T 4+ Wr&te an "3%! C (ro'ram to create a )reF*ency o) 4%33 2G on (&n -4+C+ 8se T&mer !A mode 4 to create de/ay+
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Nin$lude Oreg@1.'P *oid 11M7.elay-*oid/C s it my itRP7VJC *oid main-*oid/ Q unsigned $'ar 6C )'ile -1/ Q my itR[my itC 11M7.elay-/C T T *oid 11M7.elay-*oid/ Q 1M=.R8678C 1H1R#1>9C 1G1R1C )'ile -1F1RR8/C 1G1R8C 1F1R8C T
EEerc&ses
1/ Find t'e *alue +or 1M=. i+ )e )ant to program 1imer 8 in mode 7, use >8@1 B1A; +or t'e $lo$& sour$e, and use instru$tions to start and stop t'e timer.
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7/ Assume t'at B1A; R 11.8@H7 MHz. ('at *alue do )e need to load into t'e timer?s registers i+ )e )ant to 'a*e a time delay o+ @ ms -millise$onds/D S'o) t'e program +or 1imer 8 to $reate a pulse )idt' o+ @ ms on P7.<. </ Assuming t'at B1A; R 11.8@H7 MHz, )rite a program to generate a s,uare )a*e o+ 7 &Hz +re,uen$y on pin PI .@. 9/ Assuming B1A; R 11.8@H7 MHz, )rite a program to generate a s,uare )a*e o+ @8 Hz +re,uen$y on pin P7.<. @/ (rite an >8@1 C program to toggle only it PI.@ $ontinuously e*ery @8 ms. Ise 1imer 8, mode 1 -16# it/ to $reate t'e delay. 6/ (rite an >8@1 C program to toggle all its o+ P2 $ontinuously e*ery @88 ms. Ise 1imer 1. mode 1 to $reate t'e delay. J/ (rite an >8@1 C program to toggle only pin PI.@ $ontinuously e*ery 7@8 ms. Ise 1imer 8, mode 7 -># it auto#reload/ to $reate t'e delay. >/ (rite an >8@1 C program to $reate a +re,uen$y o+ 7@88 Hz on pin P7.J. Ise 1imer 1. mode 7 to $reate t'e delay. H/ A s)it$' is $onne$ted to pin PI.7. (rite an >8@1 C program to monitor S( and $reate t'e +ollo)ing +re,uen$ies on pin PI.J! S(R8! @88 Hz S(R1! J@8 Hz Ise 1imer 8, mode 1 +or ot' o+ t'em. 18/ Assuming t'at $lo$& pulses are +ed into pin 1l, )rite a program +or $ounter 1 in mode 7 to $ount t'e pulses and display t'e state o+ t'e 1;1 $ount on -4+
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11/ Assume t'at a 1#Hz e6ternal $lo$& is eing +ed into pin 1l -P<.@/. (rite a C program +or $ounter 1 in mode 7 -># it auto reload/ to $ount up and display t'e state o+ t'e 1;1 $ount on PI. Start t'e $ount at =H. 17/ Assume t'at a 1#Hz e6ternal $lo$& is eing +ed into pin 1= -P<.9/. (rite a C program +or $ounter 8 in mode #1 -16# it/ to $ount t'e pulses and display t'e 1H= and 1;= registers on P7 and PI, respe$ti*ely. 1</ Assume t'at a 7#Hz e6ternal $lo$& is eing +ed into pin 1l -P<.@/. (rite a C program +or $ounter 8 in mode 7 -># it auto reload/ to display t'e $ount in ASCII. 1'e ># it inary $ount must e $on*erted to ASCII. .isplay t'e ASCII digits -in inary/ on P=, PI, and P7 )'ere P= 'as t'e least signi+i$ant digit. Set t'e initial *alue o+ 1H= to 8. 19/ Assume t'at a 68#Hz e6ternal $lo$& is eing +ed into pin 1= -P<.9/. (rite a C program +or $ounter 8 in mode 7 -># it auto#reload/ to display t'e se$onds and minutes on PI and P7, respe$ti*ely.
SERIAL C,MM8.ICATI,.
Computers $an trans+er data in t)o )ays! parallel and serial. In parallel data trans+ers, o+ten > or more lines -)ire $ondu$tors/ are used to trans+er data to a de*i$e t'at is only a +e) +eet a)ay. "6amples o+ parallel data trans+er are printers and 'ard dis&sC ea$' uses $a les )it' many )ire strips. Alt'oug' in su$' $ases a lot o+ data $an e trans+erred in a s'ort amount o+ time y using many )ires in parallel, t'e distan$e $annot e great. 1o trans+er to a de*i$e lo$ated many meters a)ay, t'e serial met'od is used. In serial $ommuni$ation, t'e data is sent one it at a time, in $ontrast to parallel $ommuni$ation, in )'i$' t'e data is sent a yte or more at a time. Serial $ommuni$ation o+ t'e >8@1 is t'e topi$ o+ t'is $'apter. 1'e >8@1 'as serial $ommuni$ation $apa ility uilt into it, t'ere y ma&ing possi le +ast data trans+er using only a +e) )ires.
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Ser&a/ ;ers*s -ara//e/ Data Trans)er I+ data is to e trans+erred on t'e telep'one line, it must e $on*erted +rom 8s and 1s to audio tones, )'i$' are sinusoidal#s'aped signals. A perip'eral de*i$e $alled a modem, )'i$' stands +or Xmodulator0demodulatorY, per+orms t'is $on*ersion. Serial data $ommuni$ation uses t)o met'ods, asyn$'ronous and syn$'ronous. 1'e syn$'ronous met'od trans+ers a lo$& o+ data at a time, )'ile t'e asyn$'ronous met'od trans+ers a single yte at a time. In data transmission i+ t'e data $an e transmitted and re$ei*ed, it is a duple6 transmission. 1'is is in $ontrast to simple6 transmissions su$' as )it' printers, in )'i$' t'e $omputer only sends data. .uple6 transmissions $an e 'al+ or +ull duple6, depending on )'et'er or not t'e data trans+er $an e simultaneous. I+ data is transmitted one )ay at a time, it is re+erred to as 'al+ duple6. I+ t'e data $an go ot' )ays at t'e same time, it is +ull duple6. =+ $ourse, +ull duple6 re,uires t)o )ire $ondu$tors +or t'e data lines, one +or transmission and one +or re$eption, in order to trans+er and re$ei*e data simultaneously.
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S&m(/eEA 2a/)-A and 1*//-D*(/eE Trans)ers Asynchrono*s ser&a/ comm*n&cat&on and data )ram&n' 1'e data $oming in at t'e re$ei*ing end o+ t'e data line in a serial data trans+er is all 8s and 1sC it is di++i$ult to ma&e sense o+ t'e data unless t'e sender and re$ei*er agree on a set o+ rules, a proto$ol, on 'o) t'e data is pa$&ed, 'o) many its $onstitute a $'ara$ter, and )'en t'e data egins and ends. Start and sto( b&ts Asyn$'ronous serial data $ommuni$ation is )idely used +or $'ara$ter#oriented transmissions, )'ile lo$&#oriented data trans+ers use t'e syn$'ronous met'od. In t'e asyn$'ronous met'od, ea$' $'ara$ter is pla$ed et)een start and stop its. 1'is is $alled framing. In t'e data +raming +or asyn$'ronous $ommuni$ations, t'e data, su$' as ASCII $'ara$ters, are pa$&ed et)een a start it and a stop it. 1'e start it is al)ays one it, ut t'e stop it $an e one or t)o its. 1'e start it is al)ays a 8 -lo)/ and t'e stop it -s/ is 1 -'ig'/.
Data trans)er rate 1'e rate o+ data trans+er in serial data $ommuni$ation is stated in ps - its per se$ond/. Anot'er )idely used terminology +or ps is aud rate. Ho)e*er, t'e aud and ps rates are not ne$essarily e,ual. 1'is is due to t'e +a$t t'at aud rate is t'e modem terminology and is de+ined as t'e num er o+ signal $'anges per se$ond. In modems a single $'ange o+ signal, sometimes trans+ers se*eral its o+ data. As +ar as t'e $ondu$tor )ire is $on$erned, t'e aud rate and ps are t'e same, and +or t'is reason )e use t'e ps and aud inter$'angea ly. 1'e data trans+er rate o+ gi*en $omputer system depends on $ommuni$ation ports in$orporated into t'at system. For e6ample, t'e early IBMPC0B1 $ould trans+er data at t'e rate o+ 188 to H688 ps. In re$ent years, 'o)e*er, Pentium ased PCS trans+er data at rates as 'ig' as @65 ps. It must e noted t'at in asyn$'ronous serial data $ommuni$ation, t'e aud rate is generally limited to 188,888 ps. RS4:4 Standards 1o allo) $ompati ility among data $ommuni$ation e,uipment made y *arious manu+a$turers, an inter+a$ing standard $alled GS7<7 )as set y t'e "le$troni$s Industries Asso$iation -"IA/ in 1H68. In 1H6< it )as modi+ied and $alled GS7<7A. GS7<7B AE. GS7<7C )ere issued in 1H6@ and 1H6H, respe$ti*ely. 1oday, GS7<7 is t'e most )idely used serial I0= inter+a$ing standard. 1'is standard is used in PCs and numerous types o+ e,uipment. Ho)e*er,
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sin$e t'e standard )as set long e+ore t'e ad*ert o+ t'e 11; logi$ +amily, its input and output *oltage le*els are not 11; $ompati le. In GS7<7, a 1 is represented y #< to #7@2, )'ile a 8 it is S< to S7@2, ma&ing #< to S< unde+ined. For t'is reason, to $onne$t any GS7<7 to a mi$ro$ontroller system )e must use *oltage $on*erters su$' as MAB7<7 to $on*ert t'e 11; logi$ le*els to t'e GS7<7 *oltage le*els, and *i$e *ersa. MAB7<7 IC $'ips are $ommonly re+erred to as line dri*ers. RS4:4 (&ns GS7<7 $a le is $ommonly re+erred to as t'e .B#7@ $onne$tor. In la eling, .B#7@P re+ers to t'e plug $onne$tor -male/ and .B#7@S is +or t'e so$&et $onne$tor -+emale/. Sin$e not all t'e pins are used in PC $a les, IBM introdu$ed t'e .B#H 2ersion o+ t'e serial I0= standard, )'i$' uses H pins only.
RS4:4 Connector DB-4%
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9>
DB- (&n connector
-&n 1*nct&ons: Pin 1 7 < 9 @ 6 J > H .es$ription .ata $arrier dete$t -.C./ Ge$ei*ed data -GB./ 1ransmitted data -1B./ .ata terminal ready-.1G/ Signal ground -:E./ .ata set ready -.SG/ Ge,uest to send -G1S/ Clear to send -C1S/ Ging indi$ator -GI/
.ote: .C., .SG, G1S and C1S are a$ti*e lo) pins. 1'e met'od used y GS#7<7 +or $ommuni$ation allo)s +or a simple $onne$tion o+ t'ree lines! 16, G6, and :round. 1'e t'ree essential signals +or 7#)ay GS#7<7. Communi$ations are t'ese! T>D! $arries data +rom .1" to t'e .C".
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R>D! $arries data +rom .C" to t'e .1" S<! signal ground
"3%! connect&on to RS4:4: 1'e GS7<7 standard is not 11; $ompati leC t'ere+ore, it re,uires a line dri*er su$' as t'e MAB7<7 $'ip to $on*ert GS7<7 *oltage le*els to 11; le*els, and *i$e *ersa. 1'e inter+a$ing o+ >8@1 )it' GS7<7 $onne$tors *ia t'e MAB7<7 $'ip is t'e main topi$. 1'e >8@1 'as t)o pins t'at are used spe$i+i$ally +or trans+erring and re$ei*ing data serially. 1'ese t)o pins are $alled 1B. and GB. and a part o+ t'e port < group -P<.8 and P<.1/. Pin 11 o+ t'e >8@1 is assigned to 1B. and pin 18 is designated as GB.. 1'ese pins are 11; $ompati leC t'ere+ore, t'ey re,uire a line dri*er to ma&e t'em GS7<7 $ompati le. =ne su$' line dri*er is t'e MAB7<7 $'ip.
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-a/ Inside MAB7<7 - / its Conne$tion to t'e >8@1 -Eull Modem/
MAB7<7 $on*erts +rom GS7<7 *oltage le*els to 11; *oltage le*els, and *i$e *ersa. =ne ad*antage o+ t'e MAB7<7 $'ip is t'at it uses a S@2 po)er sour$e )'i$', is t'e same as t'e sour$e *oltage +or t'e >8@1. In t'e ot'er )ords, )it' a single S@2 po)er supply )e $an po)er ot' t'e >8@1 and MAB7<7, )it' no need +or t'e po)er supplies t'at are $ommon in many older systems. 1'e MAB7<7 'as t)o sets o+ line dri*ers +or trans+erring and re$ei*ing data. 1'e line dri*ers used +or 1B. are $alled 11 and 17, )'ile t'e line dri*ers +or GB. are designated as G1 and G7. In many appli$ations only one o+ ea$' is used.
@1
1B.
GB. 1B.
7 < @
"m edded Controller
GB. :E.
MAB 7<7
C,..ECTI.< HC to -C *s&n' MA> 4:4 Ba*d rate &n the "3%! aud rate in t'e >8@1 is programma le done )it' t'e 'elp o+ 1imer 1 relations'ip et)een t'e $rystal +re,uen$y and t'e aud rate in t'e >8@1 >8@1 di*ides t'e $rystal +re,uen$y y 17 to get t'e ma$'ine $y$le +re,uen$y B1A; R 11.8@H7 MHz, t'e ma$'ine $y$le +re,uen$y is H71.6 &Hz >8@1?s IAG1 di*ides t'e ma$'ine $y$le +re,uen$y o+ H71.6 &Hz y <7 on$e more e+ore it is used y 1imer 1 to set t'e aud rate H71.6 &Hz di*ided y <7 gi*es 7>,>88 Hz 1imer 1 must e programmed in mode 7, t'at is ># it, auto#reload.
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SB81 @ser&a/ b*))er7 re'&ster a yte o+ data to e trans+erred *ia t'e 16. line must e pla$ed in t'e SBIF register SBIF 'olds t'e yte o+ data )'en it is re$ei*ed y t'e G6. line $an e a$$essed li&e any ot'er register M=2 SBIF,N?.? Cload SBIFR99H, ASCII +or ?.\ M=2 SBIF,A C$opy a$$umulator into SBIF M=2 A,SBIF C$opy SBIF into a$$umulator )'en a yte is )ritten, it is +ramed )it' t'e start and stop its and trans+erred serially *ia t'e 16. pin
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)'en t'e its are re$ei*ed serially *ia G6., it is de+rame y eliminating t'e stop and start its, ma&ing a yte out o+ t'e data re$ei*ed, and t'en pla$ing it in t'e SBIF
SC,. @ser&a/ contro/7 re'&ster! 1o program t'e start it, stop it, and data it
EEam(/e (ro'rams
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@6
EEerc&ses
!+ (rite an >8@1 C program to send t)o di++erent strings to t'e serial port. Assuming t'at S( is $onne$ted to pin P7.8, monitor its status and ma&e a de$ision as +ollo)s! S( R 8! send your +irst name S( R 1! send your last name Assume B1A; R 11.8@H7 MHz, aud rate o+ H688, ># it data, 1 stop it. 4+ Program t'e >8@1 to re$ei*e ytes o+ data serially, and put t'em in PI. Set t'e aud rate at 9>88, ># it data, and 1 stop it. :+ (rite a program to send t'e te6t string 3Hello3 to Serial N1. Set t'e aud rate at H688, ># it data, and 1 stop it. $+ Assume t'at a s)it$' is $onne$ted to pin P7.8.(rite a program to monitor t'e s)it$' and per+orm t'e +ollo)ing! I+ S( R 8 send t'e message 3Hello3 to t'e Serial N8 port.
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I+ S( R 1 send t'e message 3:ood ye3 to t'e Serial N1 port. %+ Assume t'at t'e >8@1 serial port is $onne$ted to t'e C=M port o+ t'e IBM PC, and on t'e PC )e are using t'e Hyper1erminal program to send and re$ei*e data serially. PI and P7 o+ t'e >8@1 are $onne$ted to ;".s and s)it$'es, respe$ti*ely. (rite an >8@1 program to -a/ send to t'e PC t'e message 3(e Are Geady3, - / re$ei*e any data sent y t'e PC and put it on ;".s $onne$ted to PI, and -$/ get data on s)it$'es $onne$ted to P7 and send it to t'e PC serially. 1'e program s'ould per+orm part -a/ on$e, ut parts - / and -$/ $ontinuously. Ise t'e 9>88 aud rate. #+ Assume a s)it$' is $onne$ted to pin P;J. (rite a program to monitor its status and send t)o messages to serial port $ontinuously as +ollo)s! S(R8 send 3E=3 S(R1 send 3U"S3 Assume B1A; R 11.8@H7 MHz, H688 aud, ># it data, and 1 stop it.
I.TERR8-TS
A single mi$ro$ontroller $an ser*e se*eral de*i$es. 1'ere are t)o )ays to do t'at! IE1"GGIP1S or P=;;IE:. -,LLI.<: In polling t'e mi$ro$ontroller $ontinuously monitors t'e status o+ a gi*en de*i$eC )'en t'e status $ondition is met, it per+orms t'e ser*i$e .A+ter t'at, it mo*es on to monitor t'e ne6t de*i$e until ea$' one is ser*i$ed. Alt'oug' polling $an monitor t'e status o+ se*eral de*i$es and ser*e ea$' o+ t'em as $ertain $ondition are met. I.TERR8-TS:
@>

In t'e interrupts met'od, )'ene*er any de*i$e needs its ser*i$e, t'e de*i$e noti+ies t'e mi$ro$ontroller y sending it an interrupts signal. Ipon re$ei*ing an interrupt signal, t'e mi$ro$ontroller interrupts )'ate*er it is doing and ser*es t'e de*i$e. 1'e program asso$iated )it' t'e interrupts is $alled t'e interrupt ser*i$e routine -ISG/.or interrupt 'andler. I.TERR8-TS 0s -,LLI.<: 1'e ad*antage o+ interrupts is t'at t'e mi$ro$ontroller $an ser*e many de*i$es -not all t'e same time, o+ $ourse/C ea$' de*i$e $an get t'e attention o+ t'e mi$ro$ontroller ased on t'e priority assigned to it. 1'e polling met'od $annot assign priority sin$e it $'e$&s all de*i$es in round#ro in +as'ion. More importantly, in t'e interrupt met'od t'e mi$ro$ontroller $an also ignore -mas&/ a de*i$e re,uest +or ser*i$e. 1'is is again not possi le )it' t'e polling met'od. 1'e most important reason t'at t'e interrupt met'od is pre+era le is t'at t'e polling met'od )astes mu$' o+ t'e mi$ro$ontrollerLs time y polling de*i$es t'at do not need ser*i$e. So, in order to a*oid tying do)n t'e mi$ro$ontroller, interrupts are used.
I.TERR8-T SER0ICE R,8TI.E For e*ery interrupt, t'ere must e an interrupt ser*i$e routine -ISG/, or interrupt 'andler. ('en an interrupt is in*o&ed, t'e mi$ro$ontroller runs t'e interrupts ser*i$e routine. For e*ery interrupt, t'ere is a +i6ed lo$ation in memory t'at 'olds t'e address o+ its ISG. 1'e group o+ memory lo$ation set aside to 'old t'e addresses o+ ISG and is $alled t'e Interrupt 2e$tor 1a le. S'o)n elo)! Interr*(t 0ector Tab/e )or the "3%!: S+.o+ I.TERR8-T R,M L,CATI,. @2E>7 -I. 1LA< CLEARI.<
1.
Geset
8888
Auto
@H

7. "6ternal 'ard)are Interrupt 8 888< P<.7 -17/ Auto
<.
1imers 8 interrupt -1F8/
888B
Auto
9.
"6ternal 'ard)are Interrupt 1-IE11/
881<
P<.< -1</
Auto
@.
1imers 1 interrupt -1F1/
881B
Auto
6.
Serial C=M -GI and 1I/
887<
Programmer $lears it
S&E Interr*(ts &n the "3%!: In reality, only +i*e interrupts are a*aila le to t'e user in t'e >8@1, ut many manu+a$turersL data s'eets state t'at t'ere are si6 interrupts sin$e t'ey in$lude reset .t'e si6 interrupts in t'e >8@1 are allo$ated as a o*e. 1. Geset. ('en t'e reset pin is a$ti*ated, t'e >8@1 4umps to address lo$ation 8888.t'is is t'e po)er#up reset. 7. 1)o interrupts are set aside +or t'e timers! one +or 1imer 8 and one +or 1imer 1.Memory lo$ation 888BH and 881BH in t'e interrupt *e$tor ta le elong to 1imer 8 and 1imer 1, respe$ti*ely. <. 1)o interrupts are set aside +or 'ard)are e6ternal 'arder interrupts. Pin num er 17-P<.7/ and 1<-P<.</ in port < are +or t'e e6ternal 'ard)are interrupts IE18 and IE11,respe$ti*ely.1'ese e6ternal interrupts are also re+erred to as "B1 and "B7.Memory lo$ation 888<H and 881<H in t'e interrupt *e$tor ta le are assigned to IE18 and IE11, respe$ti*ely. 9. Serial $ommuni$ation 'as a single interrupt t'at elongs to ot' re$ei*e and transmit. 1'e interrupt *e$tor ta le lo$ation 887<H elongs to t'is interrupt.
68

Eoti$e t'at a limited num er o+ ytes are set aside +or ea$' interrupt. For e6ample, a total o+ > ytes +rom lo$ation 888< to 888A is set aside +or IE18, e6ternal 'ard)are interrupt 8.similarly,a total o+ > ytes +rom lo$ation 88BH to 8817H is reser*ed +or 1F8, 1imer 8 interrupt. I+ t'e ser*i$e routine +or a gi*en interrupt is s'ort enoug' to +it in t'e memory spa$e allo$ated to it, it is pla$ed in t'e *e$tor ta leC ot'er)ise, and an ;ZMP instru$tion is pla$ed in t'e *e$tor ta le to point to t'e address o+ t'e ISG. In t'at rest o+ t'e ytes allo$ated to t'at interrupt are unused. From t'e a o*e ta le also noti$e t'at only t'ree ytes o+ G=M spa$e are assigned to t'e reset pin. t'ey are G=M address lo$ation 8,1 and7.address lo$ation < elongs to e6ternal 'ard)are interrupt 8.+or t'is reason, in our program )e put t'e ;ZMP as t'e +irst instru$tion and redire$t t'e pro$essor a)ay +rom t'e interrupt *e$tor ta le, as s'o)n elo)
Ste(s &n eEec*t&n' an &nterr*(t Ipon a$ti*ation o+ an interrupt, t'e mi$ro$ontroller goes t'roug' t'e +ollo)ing steps. 1. It +inis'es t'e instru$tion it is e6e$uting and sa*es t'e address o+ t'e ne6t instru$tion -PC/ on t'e sta$&. 7. It also sa*es t'e $urrent status o+ all t'e interrupts internally -i.e., not on t'e sta$&/. <. It 4umps to a +i6ed lo$ation in memory $alled t'e interrupt *e$tor ta le t'at 'olds t'e address o+ t'e interrupts ser*i$e routine. 9. 1'e mi$ro$ontroller gets t'e address o+ t'e ISG +rom t'e interrupt *e$tor ta le and 4umps to it. It starts to e6e$ute t'e interrupt ser*i$e su routine until it rea$'es t'e last instru$tion o+ t'e su routine, )'i$' is G"1I -return +rom interrupt/. @. Ipon e6e$uting t'e G"1I instru$tion, t'e mi$ro$ontroller returns to t'e pla$e )'ere it )as interrupted. First, it gets t'e program $ounter -PC/ address +rom t'e sta$& y popping t'e top t)o ytes o+ t'e sta$& into t'e PC. 1'en it starts to e6e$ute +rom t'at address. Eoti$e +rom step @ t'e $riti$al role o+ t'e sta$&. For t'is reason, )e must e $are+ul in manipulating t'e sta$& $ontents in t'e ISG. Spe$i+i$ally, in t'e ISG, 4ust as in any CA;; su routine, t'e num er o+ pus'es and pops must e e,ual. Enab/&n' and d&sab/&n' an &nterr*(t: Ipon reset, all interrupt are disa led -mas&ed/, meaning t'at none )ill e responded to y t'e mi$ro$ontroller i+ t'ey are a$ti*ated. 1'e interrupt must e ena led y so+t)are in order +or t'e mi$ro$ontroller to respond to t'em. 1'ere is a register $alled I" -interrupt ena le/ t'at is responsi le +or ena ling -unmas&ing/ and disa ling -mas&ing/ t'e interrupts. Eoti$e t'at I" is a it#addressa le register.
61
Ste(s &n enab/&n' an &nterr*(t: 1o ena le an interrupt, 1. Bit .J o+ t'e I" register -"A/ must e set to 'ig' to allo) t'e reset to ta&e e++e$t. I+ "AR1, interrupts are ena led and )ill e responded to i+ t'eir $orresponding it in I" are 'ig'. I+ "AR8, no interrupt )ill e responded to, e*en i+ t'e asso$iated it in t'e I" register is 'ig'. Interr*(t Enab/e Re'&ster
"A
I".J
## "17 "S "11 "B1 "18 "B8
I".6 I".@ I".9 I".< I".7 I".1 I".8
disa les all interrupts. I+ "AR8, no interrupts is a$&no)ledged. I+ "AR1, ea$' interrupt sour$e is indi*idually ena led disa led By setting or $learing its ena le it. Eot implemented, reser*ed +or +uture use.K "na les or disa les 1imer 7 o*er+lo) or $apture interrupt ->8@7 =nly/ "na les or disa les t'e serial port interrupts. "na les or disa les 1imers 1 o*er+lo) interrupt "na les or disa les e6ternal interrupt 1. "na les or disa les 1imer 8 o*er+lo) interrupt. "na les or disa les e6ternal interrupt.
Interr*(t -r&or&ty Re'&ster
Wr&te a C (ro'ram that cont&n*o*s/y 'ets a s&n'/e b&t o) data )rom -I+ C and sends &t to -/+3A 5h&/e s&m*/taneo*s/y creat&n' a sF*are 5a;e o) 433 @as (er&od on (&n -4+%+ 8se t&mer 3 to create the sF*are 5a;e+
67

Ass*me that >TAL I !!+3% 4 M2G.
Wr&te a C (ro'ram that cont&n*o*s/y 'ets a s&n'/e b&t o) data )rom -I+ C and sends &t to -/+, &n the ma&nA 5h&/e s&m*/taneo*s/y @a7 creat&n' a sF*are 5a;e o) 433 *s (er&od on (&n -4+%A
6<

and @b7 send&n' /etter JAJ to the ser&a/ (ort+ 8se T&mer 3 to create the sF*are 5a;e+ Ass*me that >TAL I !!+3% 4 M2G+ 8se the #33 ba*d rate+
E>AM-LE -R,<RAMS
69

!+ (rite a C program using interrupts to do t'e +ollo)ing! 1. Ge$ei*e data serially and send it to P=, 7. Gead port PI, transmit data serially, and gi*e a $opy to P7, <. Ma&e timer 8 generate a s,uare )a*e o+ @ &Hz +re,uen$y on P=.l. Assume t'at B1A; R 11.8@H7 MHz. Set t'e aud rate at 9>88. 4+ (rite a C program using interrupts to do t'e +ollo)ing! 1. :enerate a 18888 Hz +re,uen$y on P7.1 using 1= ># it auto#reload, 7. Ise timer 1 as an e*ent $ounter to $ount up a 1#Hz pulse and display it on P=. 1'e pulse is $onne$ted to "B1. Assume t'at B1A; R 11.8@H7 MHz. Set t'e aud rate at H688. :+ Assume t'at t'e IE11 pin is $onne$ted to a s)it$' t'at is normally 'ig'. ('ene*er it goes lo), it s'ould turn on an ;".. 1'e ;". is $onne$ted to PI .< and is normally o++. ('en it is turned on it s'ould stay on +or a +ra$tion o+ a se$ond. As long as t'e s)it$' is pressed lo), t'e ;". s'ould stay on. $+ (rite a program in )'i$' t'e >8@1 reads data +rom PI and )rites it to P7 $ontinuously )'ile gi*ing a $opy o+ it to t'e serial C=M port to e trans+erred serially. Assume t'at B1A; R 11.8@H7 MHz. Set t'e aud rate at H688. %+ (rite a program using interrupts to do t'e +ollo)ing! 1. Ge$ei*e data serially and send it to P=, 7. Ha*e port PI read and transmitted serially, and a $opy gi*en to P7, <. Ma&e 1imer 8 generate a s,uare )a*e o+ @ &Hz +re,uen$y on P=.l. Assume t'at B1A; R 11.8@H7 MHz. Set t'e aud rate at 9>88. #+ (rite a C program using interrupts to do t'e +ollo)ing! 1. :enerate a 18888 Hz +re,uen$y on P7.1 using 1= ># it auto#reload, 7. Ise timer 1 as an e*ent $ounter to $ount up a 1#Hz pulse and display it on P=. 1'e pulse is $onne$ted to "B1. Assume t'at B1A; R 11.8@H7 MHz. Set t'e aud rate at H688.
LCD @L&F*&d Crysta/ D&s(/ay7

;i,uid $rystal displays -;C. s/ 'a*e materials )'i$' $om ine t'e properties o+ ot' li,uids and $rystals. Gat'er t'an 'a*ing a melting point, t'ey 'a*e a temperature range )it'in
6@

)'i$' t'e mole$ules are almost as mo ile as t'ey )ould e in a li,uid, ut are grouped toget'er in an ordered +orm similar to a $rystal. An ;C. $onsists o+ t)o glass panels, )it' t'e li,uid $rystal material sand )it$'ed in et)een t'em. 1'e inner sur+a$e o+ t'e glass plates are $oated )it' transparent ele$trodes )'i$' de+ine t'e $'ara$ter, sym ols or patterns to e displayed polymeri$ layers are present in et)een t'e ele$trodes and t'e li,uid $rystal, )'i$' ma&es t'e li,uid $rystal mole$ules to maintain a de+ined orientation angle. =ne ea$' polarisers are pasted outside t'e t)o glass panels. 1'ese polarisers )ould rotate t'e lig't rays passing t'roug' t'em to a de+inite angle, in a parti$ular dire$tion ('en t'e ;C. is in t'e o++ state, lig't rays are rotated y t'e t)o polarisers and t'e li,uid $rystal, su$' t'at t'e lig't rays $ome out o+ t'e ;C. )it'out any orientation, and 'en$e t'e ;C. appears transparent. ('en su++i$ient *oltage is applied to t'e ele$trodes, t'e li,uid $rystal mole$ules )ould e aligned in a spe$i+i$ dire$tion. 1'e lig't rays passing t'roug' t'e ;C. )ould e rotated y t'e polarisers, )'i$' )ould result in a$ti*ating 0 'ig'lig'ting t'e desired $'ara$ters. 1'e ;C.Ls are lig't)eig't )it' only a +e) millimeters t'i$&ness. Sin$e t'e ;C.Ls $onsume less po)er, t'ey are $ompati le )it' lo) po)er ele$troni$ $ir$uits, and $an e po)ered +or long durations. 1'e ;C. s )onLt generate lig't and so lig't is needed to read t'e display. By using a$&lig'ting, reading is possi le in t'e dar&. 1'e ;C.Ls 'a*e long li+e and a )ide operating temperature range. C'anging t'e display size or t'e layout size is relati*ely simple )'i$' ma&es t'e ;C.Ls more $ustomer +riendly. 1'e ;C. s used e6$lusi*ely in )at$'es, $al$ulators and measuring instruments is t'e simple se*en#segment displays, 'a*ing a limited amount o+ numeri$ data. 1'e re$ent ad*an$es in te$'nology 'a*e resulted in etter legi ility, more in+ormation displaying $apa ility and a )ider temperature range. 1'ese 'a*e resulted in t'e ;C. s eing e6tensi*ely used in tele$ommuni$ations and entertainment ele$troni$s. 1'e ;C. s 'as e*en started repla$ing t'e $at'ode ray tu es -CG1s/ used +or t'e display o+ te6t and grap'i$s, and also in small 12 appli$ations.
66
LCD o(erat&on
In re$ent years t'e ;C. is +inding )idespread use repla$ing ;". s -se*en#segment ;". or ot'er multi segment ;". s/. 1'is is due to t'e +ollo)ing reasons! 1. 1'e de$lining pri$es o+ ;C. s. 7. 1'e a ility to display num ers, $'ara$ters and grap'i$s. 1'is is in $ontra$t to ;". s, )'i$' are limited to num ers and a +e) $'ara$ters. <. In$orporation o+ a re+res'ing $ontroller into t'e ;C., t'ere y y t'e CPI to &eep displaying t'e data. 9. "ase o+ programming +or $'ara$ters and grap'i$s. relie*ing t'e CPI o+ t'e tas& o+ re+res'ing t'e ;C.. In t'e $ontrast, t'e ;". must e re+res'ed
LCD (&n descr&(t&on
6J
-&n descr&(t&on )or LCD:
6>
6H
LCD Command Codes Code @heE7

1 7 9 6 @ J > A C " F 18 19 1> 1C >8 C8 <>
Command to LCD Instr*ct&on Re'&ster

Clear display s$reen Geturn 'ome .e$rement $ursor In$rement $ursor S'i+t display rig't S'i+t display le+t .isplay o++, $ursor o++ .isplay o++, $ursor on .isplay on, $ursor o++ .isplay on, $ursor on .isplay on, $ursor lin&ing S'i+t $ursor position to le+t S'i+t $ursor position to rig't S'i+t t'e entire display to t'e le+t S'i+t t'e entire display to t'e rig't For$e $ursor to eginning o+ 1st line For$e $ursor to eginning o+ 7nd line 7 lines and @6J matri6
8ses:
1'e ;C.s used e6$lusi*ely in )at$'es, $al$ulators and measuring instruments are t'e simple se*en#segment displays, 'a*ing a limited amount o+ numeri$ data. 1'e re$ent
J8
A Course on REAL-TIME EMBEDDED SYSTEMS . . . by Krest Technologies ad*an$es in te$'nology 'a*e resulted in etter legi ility, more in+ormation displaying $apa ility and a )ider temperature range. 1'ese 'a*e resulted in t'e ;C.s eing e6tensi*ely used in tele$ommuni$ations and entertainment ele$troni$s. 1'e ;C.s 'a*e e*en started repla$ing t'e $at'ode ray tu es -CG1s/ used +or t'e display o+ te6t and grap'i$s, and also in small 12 appli$ations.
LCD I.TER1ACI.<
Send&n' commands and data to LCDs 5&th a t&me de/ay:
1o send any $ommand +rom ta le 7 to t'e ;C., ma&e pin GSR8. For data, ma&e GSR1.1'en pla$e a 'ig' to lo) pulse on t'e " pin to ena le t'e internal lat$' o+ t'e ;C..
J1

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