Metastable state (metastable) chain reaction Almost all digital design textbooks are mentioned metastable, meta-stable this

term is widely known in the chip designer, no wonder. For digital design engineers need to understand is the meta-stable impact on the circuit and causes, how to avoid it. nly a deep understanding o! the negative conse"uences o! metastability, will have Audition experience. First, talk about the chain reaction caused by metastability, like the atomic bomb, as very serious. As shown below# async$sig right clk is asynchronous, asynchronous, meaning re!ers async$sig this point in time and the signal change rising edge o! clk no correlation, !or example, by the addition o! a di!!erent generation o! clk clock domains, the di!!erent clock domains and this clock clk domain does not have a speci!ic relationship. %hat aync$sig signal clk changes likely to occur in any one period o! time. As async$sig asynchronous relationship, it is sampled clk resulting action will occur in the data terminal & &FFA changing time, the sampled data may be metastable, A point in an intermediate level. 'peaking o! books, the metastable state will not last long, over a short period o! time, A point level will still go (igh or )ow (speci!ically (igh or )ow is uncertain). 'ince the point A will eventually move towards homeostasis, and why it will bring conse"uences* )et+s assume that the duration o! metastability is ,.-ns, the !igure o! the circuit cycle is .,ns, !or clarity, timing analysis made abstract and simpli!ied. %hese circuits are synthetically generated synthesis tool, a!ter A/0, the !inal analysis was carried out by the '%A timing guarantees. &FF. to &FF1,, &FF. to &FF1. and &FF1, to &FF2 .,ns timing are able to meet the re"uirements. %he '%A static timing analysis, a !undamental guarantees that synchroni3ation circuit does not appear metastability. (4! '%A analysis report %iming violation, then there may also appear synchronous circuit metastability). 1ad when point A metastable lasted a certain time (,.-ns), originally &FFA to &FF1, timing is to meet the re"uirements, i! the timing margin is only ,..ns, then remove the metastable brought ,.-ns , it does not meet the timing re"uirements. 4n other words, it had no metastable, &FFA to &FF1,5&FF1. timing is to meet the re"uirements, now have metastable, their time is not enough. 4! you have a lot o! point A load path, as long as the path timing margins enough ,.-ns, then they are the result o! lack o! time will occur. 6ot enough time to bring the e!!ect is likely to be &FF1,5&FF1. sampling time, they do not calculate the & terminal to complete, is in the period o! change, which also occurred &FF1,5&FF1. metastability. 4! a lot o! the load point A, then part o! the timing margin is not enough, the next level may thus continue to produce enough time metastable7 course, in part because o! the timing margin is large, it does not occur metastable state. And so on, start !rom point A, a level back, like a chain, like metastable, step by step hair should be, more and more, 8ust like the atomic bomb. %he entire chip will be in disarray. 2an only be reset in order to recover.

%his is why you want to add two &FF synchroni3er causes. %wo &FF synchroni3ation between them is not logical, it is great timing margins, metastability will not hurt to the back o! the circuit. &escribed earlier, it is considered metastable time ,.-ns actually a special case, the actual rate is a generous !actor, but not very long (personal years o! practical experience products that will not up to the level above 9ns (.:, 5 .;,nm process)). Another problem, i! time is metastable ,.-ns, &FF circuit synchroni3ation cycle is ,.-ns, then how to do* %his time, the lack o! time synchroni3er will occur, what to do* ! course, there is a way to understand the above principle, should be able to design their own out (increase cycles, or cascade lower probability).