A4-R3: COMPUTER ORGANIZATION NOTE: 1. There are TWO PARTS in this Module/Paper.

PART ONE contains FOUR questions and PART TWO contains FIVE questions. 2. PART ONE is to be answered in the TEAR-OFF ANSWER SHEET only, attached to the question paper, as per the instructions contained therein. PART ONE is NOT to be answered in the answer book.

Maximum time allotted or PART ONE is ONE HOUR. !nswer book or PART TWO will be supplied at the table when the answer sheet or PART ONE is returned. "owe#er, candidates, who complete PART ONE earlier than one hour, can collect the answer book or PART TWO immediately a ter handin$ o#er the answer sheet or PART ONE. TOTAL TIME: 3 HOURS TOTAL MARKS: 100 (PART ONE 40; PART TWO 60) PART ONE (Answ ! "## $% &' s$()ns* 1+ E",% &' s$()n - #)w .(/ s " 0'#$(1# ,%)(, )2 "nsw !s+ C%))s $% 0)s$ "11!)1!("$ )n "n3 n$ ! (n $% 4$ "!-)225 "nsw ! s% $ "$$",% 3 $) $% &' s$()n 1"1 !6 2)##)w(n. (ns$!',$()ns $% ! (n+ (1 7 10* The minimum time delay between the initiations o two independent memory operations is called &ycle time !ccess time (atency time *one o the abo#e +rom a $i#en tautolo$y, another tautolo$y can be deri#ed by interchan$in$ , and 1 !*) and -. 'oth !% and '% /mpossible to deri#e &hoose the incorrect statement 'us is a $roup o in ormation carryin$ wires 'us does not create delay in data trans er 'us can carry data or address ! bus can be shared by more than one de#ice The binary equi#alent o the decimal number ,.0312 is ,.,111 ,.1,11 ,.11,, ,.1,1, 3hich o the ollowin$ lo$ic amilies is well suited or hi$h speed operation TT( 4&( M-5

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'ubble memories are pre erable to loppy disks because - their hi$her trans er rate &ost needed to store a bit is less They consume less power *one o the abo#e The cost o storin$ one bit o in ormation is minimum in case o &ache .e$ister .!M *one o the abo#e Pseudoinstructions are !ssembler )irecti#es /nstructions in any pro$ram that has no correspondin$ machine code /nstructions in any pro$ram whose presence or absence will not chan$e the output or any input *one o the abo#e ! lip lop circuit can be used or &ountin$ 5calin$ .ecti ication )emodulation The number o address and data lines or a memory o 0 7 8 16 is9 1,, 16 11, : 12, 16 12, 12

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E",% s$"$ 0 n$ - #)w (s ($% ! TRUE )! FALSE+ C%))s $% 0)s$ "11!)1!("$ )n "n3 ENTER (n $% 4$ "!-)225 s% $ "$$",% 3 $) $% &' s$()n 1"1 !6 2)##)w(n. (ns$!',$()ns $% ! (n+ (1 7 10* 4'&)/& code uses 1 bits to represent a character. The speed imbalance between memory access and &P; operations is reduced by memory interlea#in$. The idea o #irtual memory is based on principal o locality o re erence. The 8-. operator is distributi#e o#er !*) operator. /n /*8 " instruction bus remains idle or one cycle. /nterrupt .5T 2.2 is both le#el and ed$e sensiti#e. /n 'oolean al$ebra Wx + yx + Wy can be reduced to Wx + yx . ! micro<pro$rammed control unit is aster than a hard wired control unit. Parallel printer does not use .5<232& inter ace. !n astable multi#ibrator can be used as a lip lop.

2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9 2.10

3+ M"$,% w)!3s "n3 1%!"s s (n ,)#'0n = w($% $% ,#)s s$ ! #"$ 3 0 "n(n.> w)!3(s*>1%!"s (s* (n ,)#'0n ?+ En$ ! :)'! s # ,$()n (n $% 4$ "!-)225 "nsw ! s% $ "$$",% 3 $) $% &' s$()n 1"1 !6 2)##)w(n. (ns$!',$()ns $% ! (n+ (1 7 10* = 3.1 3.2 3.3 3.0 3.2 3.6 3.1 3.: 3.@ 3.1, /n a =ectored interrupt /n order to sa#e accumulator #alue onto stack Parity bit is included or Ma$netic )isk is not a !n index re$ister is used or &ross !ssembler machine runs on one A+ @+ C+ A+ E+ F+ G+ H+ I+ 9+ K+ L+ M+ ? P;5" P53 will be used =olatile memory halts or a predetermined time and produces machine code or another

!ddress modi ication /nstruction set si>e is kept less Master/sla#e ?7<+lip<+lop ?7 +lip lop the branch is assi$ned to a ixed location in the memory 4rror correction M/M) architecture .-M .5 +lip< lop

-n arri#al o an interrupt, the &P; .acin$ problems do not exist =on *eumann architecture is not a ! typical characteristic machine is o ./5&

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E",% s$"$ 0 n$ - #)w %"s " -#"nB s1", $) 2($ )n )2 $% w)!3(s* )! 1%!"s (s* (n $% #(s$ - #)w+ En$ ! :)'! ,%)(, (n $% 4$ "!-)225 "nsw ! s% $ "$$",% 3 $) $% &' s$()n 1"1 !6 2)##)w(n. (ns$!',$()ns $% ! (n+ (1 7 10* !ccess time Machine instruction Microinstruction &ircular shi t re$ister )ecoder @+ E+ H+ K+ N+ -peratin$ system !rray )irect address mode Memory bu er re$ister Multiplexer C+ F+ I+ L+ O+ &ontrol store Processor .e$ister trans er lan$ua$e &arry look ahead adder 4ncoder

A+ A+ G+ 9+ M+ 0.1 4.2 4.3 4.4 4.5 4.6 4.7 4.8 4.9 4.10

The instruction o a micro pro$rammed control unit is called as AAAAAAAA. =ector processor can also be called as AAAAAAAA. /n AAAAAAAA the e ecti#e address is equal to the address part o the instruction. AAAAAAAA is collection o pro$rams that controls the operation o computer or the purpose o obtainin$ an e icient per ormance. AAAAAAAA has the capability o stoppin$ the computer. ! rin$ counter is aBn% AAAAAAAA. The AAAAAAAA anticipates the carry in ad#ance. The AAAAAAAA is used or storin$ the data bits. The time di erence between application o read si$nal and a#ailability o data on data lines are called as AAAAAAAA. !Bn% AAAAAAAA is a di$ital unction that con#erts binary in ormation rom one coded orm to another.

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PART TWO B!nswer any FOUR questions% 8+ a% &onsider a cache BM1% and main memory BM2% hierarchy with the ollowin$ characteristics. M19 16 7 words, 2, ns access time M29 1 M words, 0,, ns access time !ssume ei$ht word catch blocks and a set si>e o 226 words with set<associati#e mappin$ i) 5how the mappin$ between M2 and M1. ii) &alculate the e ecti#e memory access time with a catch hit ratio o hC,.@2. )esi$n a lo$ic circuit that per orms the operations o 4xclusi#e D -., 4qui#alence, *-. and *!*). ;se two selection #ariables. 5how the lo$ic dia$ram o one typical sta$e. (CD<* &onsider a our #ariable 'oolean unction9 + C E B,, 0, 6, 1, :, 1,, 11, 12%, Minimi>e this unction usin$ 7 map, and reali>e it usin$ $ates. 3hy *!*) $ate is called a uni#ersal $ate. ?usti y your answer. &on#ert decimal number B212%1, into i% binary, ii% binary coded hexadecimal, iii% '&), and represent each con#erted number in the ormat o 12 bit re$ister. (8D4DE* 3hat is the di erence between isolated //- and memory mapped //-. 3hat are the ad#anta$es and disad#anta$es o eachF ! 36 bit< loatin$ number has : bits plus a si$n bit or the exponent. The mantissa is assumed to be a normali>ed raction. *e$ati#e numbers in mantissa and exponent are in si$ned ma$nitude representation. 3hat are the lar$est and smallest positi#e quantities that can be represented, excludin$ >eroF 4xplain character oriented protocol used in data transmission. (8DED4* 3rite a macro named ADD which takes two ar$uments and returns the summation o these ar$uments. &all it in main pro$ram to per orm the additions o 9 i% 0, : ii% 1, 3 3rite an assembly lan$ua$e pro$ram to con#ert a decimal number to binary number. 3hat is the use o addressin$ modeF )i erentiate between index and base index addressin$ mode. (ED4D8* 3ith the help o suitable lo$ic dia$ram explain the unctionin$ o one bit !(; which is able to per orm basic arithmetic and lo$ic operations. (ist any i#e data trans er instructions. 4xplain the unctionin$ o &)<.-M stora$e de#ice. (8D8D8*

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