Analog & Digital Compared

Amplifiers and logic gates are certainly different in function, and mathematically, analog entails continuous functions while digital functions are discrete. (Sampled-data systems are in-between; their samples of continuous quantities occur discretely in time.) Analog and digital appear to be quite different realms of technology. Howe er, techniques of one often ha e analogous techniques in the other. Here, we ta!e a loo! at some similarities. "he difference between analog and digital electronics diminishes with comple#ity. As digital approaches the functional comple#ity of computation, difference equations appear, and are comparable in the discrete domain to differential equations. $S% theory is more li!e analog electronics than logic design. At the register le el, signal processing of discrete quantities is not unli!e analog signal processing. "o demonstrate the similarities, consider two technologies, opamps and A&$ con erters (A$'s). (hile A$'s span the gap between analog and digital (and are not purely digital), they will ser e to ma!e the comparison.

Starting with the op-amp, it is more of an integrator than an amplifier in that its open-loop gain begins rolling off near ) H*, as shown below.

+ow consider both integrating (dual-slope, - ) and parallel-feedbac! (successi e-appro#imation (SA), trac!ing) type A$'s. "he generali*ed parallel-feedbac! con erter scheme is diagrammed below. "hey also trade off speed for precision, with a plot similar to the op-amp, shown below.

As sampling rate increases, the number of digiti*ed bits decreases. ,or both categories of A$'s, digital feedbac! of bits compares to the op-amp feedbac!. ,or instance, the SA con erter ma!es one bit comparison per cloc! cycle. "he sample rate consequently rolls off at a slope of -. (-/ d0), as doubling the bits hal es the sample rate for the same cloc! frequency. 1ntegrating con erters accumulate more counter bits, timing out a prolonged integration of their inputs, leading to more bits, but at the e#pense of time. Again, the log-log bits-speed slope is -.. "o increase con erter speed, more processing is done in parallel. 1nstead of using a single comparator (which itself is a one-bit A$'), flash con erters use 2N comparators to con ert N bits of data simultaneously. "his bandwidth-e#tension technique has an analog in analog3 the f" multiplier. "he basic scheme is shown below.

"o double bandwidth at the same gain, A, use two amplifiers with transconductance A&2 in parallel. 4ach amplifier, ha ing half the gain of the original, has twice the bandwidth. And the currentsumming at the output node does not decrease bandwidth, but allows the addition of the indi idual amplifier gains. 0andwidth can be further e#tended using three amplifiers (f"-tripler), and more. 0ut e entually, side-effects from paralleling cause diminishing returns. 0ut the concept wor!s for low parallelism, 5ust as it does with comparators in flash con erters. A typical implementation of the f"doubler as a differential amplifer is shown below.

A 06" implementation (omitting biasing circuitry) as a current amplifier is shown below.

"he collector currents of the two diff-amp stages are connected in parallel, while their inputs are in series. 4ach diff-amp has a gain of A and an input of Vi&2. "hen the total gain is3

where m 7 2 for a doubler. "he gain-bandwidth of each diff-amp is f" (in the square brac!ets) multiplied by the leading m, for a gain-bandwidth of m f". ,or a single diff-amp, with twice the input oltage (the right side of the abo e equation), the gain is the same but with a gain-bandwidth of only f". %arallelism has its ad antages. ,inally, gain and precision can be traded off by cascading op-amps, as shown below.

Assume both op-amps ha e an open-loop gain of K and equal gain-bandwidths, f". "he second amplifier stage is faster than the first because its closed-loop gain is less, as shown on the 0ode plot (b), and it has a bandwidth of fbw2. "he cascaded combination has a gain-bandwidth that is no better than the indi idual amplifiers, but more loop gain is a ailable at higher frequencies. "he digital analog - another A$' type - is the two-stage or half-flash A$', s!etched out as follows.

"he two-stage A$' deli ers n bits, or, for A$'. 7 A$'2, 2 m bits. A same-speed, one-stage flash A$' of n bits has 2n comparators, while the abo e A$' has 2 2n/2 7 2n/2 8 .. "he two-stage A$' is less than half as fast but maintains the same precision of n bits with far fewer comparators. (hile comparison with the cascaded op-amp in this case is not direct and simple, there are similarities. 1n an op-amp, more amplifier stages are required to achie e more gain 5ust as more comparators are required in the full-flash A$' to achie e more bits of precision. 1n feedbac! amplifiers, more gain pro ides more precision. "he reduction in comparators of the half-flash is greater than its speed reduction, thereby ma!ing its speed&comparator ratio (roughly analogous to gain-bandwidth product) better than the full flash. "he cascaded op-amp similarly has no better speed than a single, closed-loop op-amp, but its precision at comparable speeds is better. "hese three analog-digital comparisons underlay the message that the general principle of precisionspeed trade-offs apply in both the analog and digital realms. 9nderstanding their application in one realm prepares one to comprehend their application in the other, lesser-understood, realm. Dennis L. Feucht, 2)))

ASICs Versus Semi-Discrete Design

Application-specific 1's (AS1's) ha e the benefit of integrating a ma#imum amount of circuitry for a particular function on a single 1'. "his sa es board space and cost. 0ut designers beware. :ou could be ;burned; by using an AS1' in your design.

The Appeal of ASICs

An e#ample of a class of AS1's is %,' or %,'&%(< ;combo; 1's, which contain essentially all the acti e control circuitry for power-factor correction and second-stage dc-dc con ersion. Some %,'&%(< 1's, such as <icro =inear>s <=?@)A, ta!e integration and small si*e to the limit. "he <=?@)A is pac!aged in an @-pin SB1'. (ith these ob ious benefits, it would seem that AS1's are the way to go, if the function you need has already been integrated. System-le el design then becomes a simplified tas! of following the ;typical circuit; in the part specifications, ma!ing minor ad5ustments for system specs, and voila! 0oard-le el design has become easy and hot-shot designers will e entually all wor! for semiconductor companies. 9nfortunately, this scenario is fictional or at least highly ideali*ed. A ;5ust right; AS1' can be ad5usted parametrically to the application while maintaining space and cost ad antages. 0ut the goal of commercial AS1' design is to ma!e it as general as possible in its specificity. 1f the AS1' is optimi*ed for one particular design, it is a custom 1', of little use for other applications. 1f it is too general, it is li!ely to be too suboptimal to be feasible. 1n reducing pac!age si*e and cost by reducing pin count, AS1's also reduce obser ability. 1n practice, a cheap AS1' will lure the unwary designer to adapt it to a somewhat different application than was intended. ,or instance, most %,' AS1's are based on a boost (common-acti e) con erter topology. 0ut what if you want to use a S4%1' insteadC 1t has the ad antage of eliminating poweron inrush current. "he current-limit thermistor, a somewhat large and e#pensi e part, can be eliminated. And though the S4%1' requires an e#tra winding, if the control circuitry is powered from a few turns on the boost power inductor, you already ha e a transformer. 0esides, the S4%1' .3. transformer suggests use of a low-cost power-line common-mode filter inductor. So you try to adapt an AS1' to a S4%1' topology. (hat happensC ,irst, the small-signal (incremental) transfer function is different. ,or a boost, the cycle-a eraged (low-frequency) transfer function is3

but for a S4%1', it is3

'onsequently, the ranges of oltages and currents changes, and parts alues (such as sense resistors) that are found in control loops, change accordingly. 0ut these alue changes affect loop beha ior. "he incremental control to input-current and control to output-current functions (though more difficult to deri e) are also different in form (and the possible sub5ect of a different article). "his also affects the control scheme; poles and *eros appear in astly different places (or not at all), and component alues can become unfeasible to implement. Desponse times can become unacceptable.

Additionally, AS1' control loops depend on a certain phase of input at their pins. 1n ersion requires additional circuitry. Suppose you sol e these problems only to find you cannot ma!e spec because AS1' performance is too limited for your adaptation. <ore subtle difficulties in ol e layout. 0ecause your topology is different, noise is higher at an AS1' pin, causing degraded performance. A short trace for a boost topology might be inescapably long for a S4%1' (or ice- ersa). "he AS1' is not designed to re5ect the higher noise, and you>re sun!. ,urthermore, your cle er enhancement cannot be implemented using the AS1' because you cannot get inside it and ma!e a change or two. AS1's do not always simplify design tas!s. And they can be e#pensi e because of their mar!et-limited functions. Another problem with AS1's is that they come and go. "hey are specific, and tend to ha e a short mar!et life. (hile 1 was designing a %,', 1 chose to use a 9nitrode 9''A@E@. 1t had a nifty scheme for feedforward compensation of line- oltage ariation using a $A', which minimi*es line ripple into the multiplier. (hile 1 was ma!ing progress on the design, "1 acquired 9nitrode and cancelled the part. %erhaps it was a good mar!eting decision for "1 but not for my pro5ect. 1f 1 had used a well-established, multiple-sourced AS1' 1 would ha e a oided this problem, but no such AS1's for %,' were a ailable. "hey were apparently too specific for that.

Semi-Discrete Design
0ecause of these design limitations using AS1's, the creati e designer tends to be pulled in the direction of design ersatility. "his leads to semi-discrete design - more parts than an AS1' but fewer than discrete transistors and <S1 1's. (<S1 stands for medium-scale integration, such as opamps, comparators, and dual flip-flops.) "hough the trend is to flee from lower le els of integration, to consider ma#imum integration a high-priority design criterion can lead to the traps described pre iously. ,or low to medium- olume products not facing e#treme space constraints, less integration can be optimal. Semi-discrete design is based on the principle of using only well-established parts that are multisourced and enduring, such as the 9'A@?2 %(< current controller, single-supply dual and quad op-amps and comparators (=<AE@, =<A2?, =<AF2, =<AAF), and a part such as a 'AA)@) for a multiplier. "hese parts are produced in high olume and ha e reached commodity price le els. "he sum of their costs can be less than an AS1'. "he disad antage of additional board space is offset by more accessible nodes to probe in test, thus reducing production test cost. ,or de elopment, such access is ob iously desirable. ,reed of AS1' constraints, no el benefits can be introduced, and the trade-off between parts count and performance better tailored to the application. ,or long product lifetimes, part obsolescence problems are minimi*ed or a oided. ,urthermore, semi-discrete designs become an ;elastic; technology base from which adaptations can be pulled further for pro5ects that differ from the base design. "his sa es redesign costs and reduces time-to-brea!e en.

Closure
Sometimes design trends should not be ta!en for granted. "hey are not always best for e ery pro5ect. (hile integration is generally a good trend, it can also produce undesirable side-effects in de elopment acti ities. Semi-discrete design is a concept that is worth !eeping in mind, if not applying as a design approach when feasible. Dennis L. Feucht, 2)))

Feedback Circuit Misconceptions

"ypical circuits te#tboo!s tell us that there are four basic feedbac! topologies. "he impression is gi en (if not stated) that any feedbac! circuit will conform to one of these four topologies. Bne of the tas!s of feedbac! analysis, it would seem then, is to identify to which of the four basic topologies a gi en feedbac! circuit conforms. 0ut this is misleading. "his article attempts to clarify the resulting confusion.

Feedback-Circuit Topologies
"he basic goal of feedbac!-circuit analysis is to ta!e the circuit diagram, which is sometimes a spaghetti-li!e connection of components, and adduce from it the transmittances (or gains or transfer functions) of the bloc!s G and of the classical feedbac! topology, shown below in bloc! diagram (a) and signal flow-path (b) representations. (Generali*ed electrical quantities - oltages or currents - are designated here as ;!; quantities, where ! is either v or i.)

Actual circuits can also ha e additional associated transmittances. "he more general feedbac! topology is shown below. "i and "o are outside the feedbac! loop but are included because they commonly occur with feedbac! circuits. Sometimes it is not ob ious from a circuit diagram that such bloc!s should be included.

0loc! diagrams do not represent circuit interconnections (topolog#) but instead describe the flow of electrical cause and effect. 4ach bloc! has an input (cause) and an output (effect) which is an electrical quantity. "he arrows represent causal constraints, pointing from output to input. "he input multiplied by the transmittance written in the bloc! is the output. ,or e#ample, !f 7 G !$. "he

summing bloc!, , adds its inputs according to the sign by the arrowhead. "his bloc! diagram is a graphic way of e#pressing the following algebraic equations3

"he first two equations describe the feedbac! loop itself. "he loop is closed and consists of G, and . Sol ing for the o erall closed-loop gain of the feedbac! amplifier, " 7 !o&!i, and is3

"he middle factor in parentheses is the gain of the closed feedbac! loop itself. Gi en a circuit diagram, if the corresponding bloc! transmittances can be found, the closed-loop feedbac! gain can be calculated from the abo e general e#pression. 'ircuits are usually not ob iously decomposable into the bloc! transmittances. (hat is needed is a procedure that deri es the bloc!s from feedbac! circuits in equi alent circuit form so that circuit analysis can then be used to determine their transmittances.

From Circuits to Block Diagrams

(hat is usually hardest in going from circuit to bloc! diagram is to identify the summing bloc!, , (and $, the error quantity) from the circuit diagram, and the pic!off circuit (and !f). Simplifying this tas! brings us to the ;four topologies; of te#tboo!s. (A circuit topolog# is essentially its schematic diagram, showing its structure through interconnection of its components.) "he four topologies are all combinations of current or oltage pic!off and error summing. As such, they are four possible topological characteristics of the feedbac! circuit. "he usual names gi en to the four are gi en in the following table. Electrical Quantity oltage current Summing Circuit Pickoff Circuit

series comparison shunt comparison

node sampling loop sampling

(hat is misleading in too many circuits te#tboo!s is the notion that a gi en circuit has one of these four topologies. 1n other words, it is con eyed that any gi en feedbac! circuit is constrained, for e#ample, to ha e either a series or shunt comparison for its summing circuit, and either node or loop sampling for its pic!off circuit. "he !ey insight here is that it is not the circuit %ut the anal#&er of it that determines 'hether voltages or currents are compared and sampled! 1f you ha e been thin!ing that the circuit itself (and not you) determines the electrical quantity summed or pic!ed off, then you would be loo!ing for some characteristic of the circuit topology to determine which quantity this is. 0ut #ou choose the quantities for summing and pic!off and then analy*e the circuit accordingly. "he choices are arbitrary, though some choices lead to a simpler analysis than others, as we will see. Bnly simple circuits with ideal sources constrain the choice to only one quantity because the other choice leads to a circuit degeneracy.

Choosing Pickoff Quantities

Starting with the pic!off circuit, what is essential is that an electrical quantity (current or oltage), !f, be identified as the pic!off quantity, !f, to be fed bac!. "he choice of !f is constrained to be the output quantity of G and the input quantity of . "he first step in the analysis is to choose !f. "here is often more than one choice that will result in a correct analysis, but also, one choice many times leads to the simplest analysis. 0ut the circuit is not the bloc! diagram, and it may not be ob ious from the circuit which quantity to choose. "o see what might happen, consider the bloc! diagram below. Suppose you choose a quantity that is inside G. G has been decomposed into cascaded bloc!s GA and G(. "he additional output bloc!, "o, is included between the pic!off point and the circuit output quantity, !o, when the chosen pic!off quantity is not the output quantity.

1f !f is chosen too much toward the input within the forward path, G, then common factors appear in the algebraic e#pressions for GA instead of G(. "his results in the following feedbac! equations3 and "o. As shown, G 7 GA G0, where !f is chosen as the output of

+ote that G( is a common factor of both the term of !$ and "o in !o. 0y letting !f be the output of G( instead, G( appears as a factor in the first equation and disappears from the others. 1f !f is instead chosen too close to the output, so that "o 7 "oA"o( and !f is the output of "oA, then3

1n this case, introducing factor "oA into the third equation remo es it from the first two. "he optimal pic!off quantity is the one which minimi*es common transmittances in these equations. Howe er, it is not necessary to choose, or e en identify, such a pic!off quantity. =et your intuition pic! a quantity which seems most appropriate. 1t becomes the input quantity to and "o, if not !o (in which case "o 7 .). Suppose you choose !f to be a oltage. Holtages occur at nodes. 'onsequently, !f is identified with a circuit node from which a connection to the feedbac!-path ( ) input is made. ,or a current, a pic!off loop must e#ist in which this current flows. A loop of G generates this current, and it flows through circuitry comprising the input of .

Choosing Summing Quantities

+ow let>s apply the same !ind of reasoning to the summing circuit. 1f !$ is chosen too close to the

output, common factors occur in the two terms of !$. =et !$ be the input to G(. "hen3

0y letting G 7 GAG(, GA becomes a factor in the first equation and is eliminated from the second. "he other case is that of choosing !$ too close to the input, as the input of "i(. "hen "i( appears as a common factor with G and in the error term containing .

0y mo ing !$ to the output of "i(, "i0 is eliminated from the first equation and becomes a factor in the first !$ term so that "i 7 "iA "i(.

term of !$ and

You Choose Pickoff and rror Quantities

"he form of input-networ! topology (series or shunt) is not generally determined by the circuit. 0ut the choice of error quantity !$ affects the choice of input topology. "his can be seen from the following input networ!.

1n this circuit, the output of the bloc! is represented by a generali*ed source (either "he enin or +orton equi alent) consisting of transmittance !(!f) and source resistance ) o. "he feedbac!-circuit input is a oltage source in series with an input resistance across which is oltage v.. 1f v. is chosen as v$, the -path port is made a "he enin circuit and the input forms a loop a series topology. 1f v2 is chosen for v$ instead, then con erting the input and feedbac! ports to +orton equi alent circuits results in a common node with oltage v$ a shunt topology. "he feedbac! circuit input topology is determined by choice of error quantity, and not by the circuit.

"he same !ind of argument applies to pic!off circuits. Bnce !f is chosen, then either a loop (for if) or node (for vf) as the pic!off circuit results. Bften, either choice can lead to a successful analysis.

Closure
"he !ey steps in analy*ing a feedbac! circuit are to choose pic!off and error quantities. (ith an awareness that input and output bloc!s may be required for some choices, consistent analysis will subsequently produce correct transmittance equations for G and (and "i and "o). 0ut do not be confused into thin!ing that your choices of !$ and !f are determined by the circuit topology. (hich of the four topologies results in your analysis depends on your choice of error and pic!off quantities, and not the circuit itself. Dennis L. Feucht, 2)).

lectrical Quantities
4lectricity is analogous to fluid flow, as compared in the table below.

Electrical Quantity
'harge

Fluid Flow Analog

,luid

Holtage

%ressure

'urrent

,low rate

Desistance

,low resistance (,anning friction factor)

,luid flows in pipes; electricity flows in electrical conductors, usually wires, circuit-board traces and components. (hat actually flows is electric charge, *+ measured in coulombs ('). ,urrent+ i+ is the rate of charge flow, or

"hat is, current is the change in charge flowing past a gi en point per change in time o er which the change in charge was measured. 'urrent is measured in units of amperes (A). Bne ampere is one coulomb per second. )esistance+ )+ determines how much current will flow when a oltage is placed across it. Holtage, v+ has units of olts, H, and is an ;across; quantity, li!e pressure and speed. Across quantities must be measured between two points, 5unctions or nodes. %ressure is measured with respect to atmosphere (gage), acuum (absolute), or with respect to some other 5unction in the plumbing (relati e). Speed is measured with respect to some reference frame that is considered at rest. Holtage is also measured across between two circuit nodes. "he node designated as ) H is also called ground. 9sually, oltage measurements are made with respect to ground; otherwise, they are ;floating; or differential measurements between two non-ground nodes. 'urrent, flow and force are through quantities and are measured in the %ranches of a networ! (whether it be wiring or plumbing). +etwor! nodes are connected by branches.

!hm"s #a$
"he most basic and often-used electrical equation is Ohms Law3

Desistance is defined by BhmIs =aw to be v&i. A .2 H battery with .) between its terminals results in ..2 A of current through both .) resistor and battery. 4lectrical components called resistors are used to limit or set current in a circuit with a gi en oltage, or set oltage for a gi en current. (A circuit element is an ideali*ation of an actual electronic part, or component.) Desistors are usually mar!ed with at least three color bands that indicate their resistance, in units of ohms ( ). ,or E J tolerance resistors, the first two bands are the first two significant digits of the alue, and the third band is the number of *eros to be added to the first two digits. A final band of gold (E J) or sil er (.) J) indicates the tolerance. ,or . J resistors, the first three bands are the first three digits; the fourth is the multiplier. "he color code is3

0=A'K

0DB(+

D4$

BDA+G4

:4==B(

GD44+

0=94

H1B=4"

GDA:

(H1"4

"he colors follow their order in the rainbow (e#cept the ends). A resistor with color bands, starting from the end, of green, brown, red (E, ., 2) has a alue of E.)) , or E.. !.

Sources and %ui&alent 'esistances

4lectrical sources are of two !inds3 oltage and current. An ideal oltage source will maintain its rated oltage across its terminals no matter what amount of current flows. A short () ) causes infinite current. "he output oltage of actual oltage sources, such as batteries, power supplies or electric generators, will decrease with increasing current. ,or a short (assuming no shutdown), the sourceIs rated oltage di ided by the resulting current is the equi alent internal resistance of the source. An actual oltage source can be modeled as in the following equi alent circuit3

"he .) resistor is in series with the .2 H oltage source. "he two small circles are the actual oltage source terminals, and the series resistance is internal to it. )L is the load resistance and is also in series with the internal resistance and ideal oltage source. "he connections of these three circuit elements form a closed loop. "he current e erywhere in the loop must be the same or else charge would accumulate or deplete (which it does not). "he current can be determined by BhmIs =aw3 .2 H is across .) plus )L+ or

Desistances in series add3

)series 7 )- . )/
"wo resistances in series are the equi alent of a single resistance with the sum of their alues. 0esides series connections, circuit elements can be connected in shunt or parallel, as shown for two resistors below3

Desistances in parallel (shunt) are equi alent to3

)parallel 0 )- MM )/ 7
"he parallel resistances can be replaced with a single, equi alent resistance of the abo e alue. <ost sources are a ailable as po'er supplies and are oltage sources, rated for a gi en oltage output for not more than a ma#imum output current. 'urrent sources supply a gi en current for not more than a ma#imum output oltage. "hey are often special-purpose supplies, such as the outputs of igniter pulse generators. "hey are limited by how much oltage can occur across their terminals when resistance approaches infinity (or, an open circuit). "his ma#imum oltage is sometimes called the current-sourceIs voltage compliance. 'urrent sources are limited by ma#imum resistances of their loads while oltage sources are limited by minimum resistances.

(irchhoff"s )oltage and Current #a$s

0esides BhmIs =aw, the most basic circuit principles are KirchhoffIs two laws. Kirchhoffs oltage Law (KH=) states that the sum of the oltages around a closed loop must equal *ero3

'urrent flows out of the positi e terminal of the source (by con ention) and causes oltage drops across resistors and other passive (non-power-generating) circuit elements. (Sources are acti e elements.) Holtage sources are, by con ention, oltage ;rises; because current goes into their negati e terminal and out the positi e terminal, from to 8. Holtages tra ersed in this direction are negati e. 1n contrast, current flows into the positi e oltage end of resistances, as shown below3

Applying KH=, VS 8 VD. 8 VD2 7 ) or, the sum of the oltage drops equals the oltage source3 VS 7 VD. 8 VD2 KH= is the analog of the principle that the sum of the pressure drops in a fluidic circuit equals the pressure source. Kirchhoffs Current Law (K'=) states that the sum of current into a node must equal *ero3

1n other words, charge does not accumulate in nodes. 0y con ention, currents flowing into a node are negati e and out of a node are positi e. "his is analogous to the principle that the sum of fluid flows into a 5unction must equal the flows out (for incompressible fluids). K'= is demonstrated by the following circuit3

Applying K'=, iout 7 i. 8 i2 All current into the 5unction must lea e it.

DC and AC
1n systems theory (whether it be electronic, chemical, mechanical, thermal or aerodynamic), some quantities remain constant while others change. A constant or static quantity is ;dc; and a changing or d#namic quantity is ;ac.; Historically, these electrical terms meant ;direct current; and ;alternating current,; but ;constant; and ;changing; are better descriptions. An ac wa eform can be added to a dc offset, as shown below3

"he ac wa eform is added to a dc amount that is the a erage of the (total) wa eform. "his a erage amount around which the ac component aries is the wa eformIs dc component. Ac and dc are often used to refer to the !ind of oltages a ailable from sources. 0atteries are ;dc; in that the oltage across their terminals is constant. $iesel-dri en generators put out a sinusoidal (;sinewa e;) oltage that has a frequency of typically /) H*. 0ecause it is a sinewa e, its oltage re erses (is bipolar), reaching positi e and negati e pea!s /) times per second. Some electronic components are inherently dynamic or ;ac; in their beha ior. "he basic dynamic circuit elements are capacitors and inductors. "ogether, they are called reactive ( ersus resisti e) elements. "ransformers are a ariation on inductors. "ransistors, integrated circuits, switches, lamps and connectors are not basic circuit elements, but can be modeled by equi alent circuits that can include reactances, resistances and controlled sources.

Fre%uenc* and Period

,requency, f, is the rate a periodic wa eform repeats. "he unit is Hert* (H*), which is ;per second.; +orth American electrical power has a frequency of /) H*. "he reciprocal of frequency is period, "1 " 0 .&f ,requency counter&timers are instruments that measure frequency, period, and other time-related aspects of periodic wa eforms. $elu#e digital multimeters ha e frequency measurement capability, as do most newer digital and some analog oscilloscopes.

)oltage and Current Di&iders

A ery common circuit used to reduce or scale a oltage is a voltage divider. 1t consists of 2 resistors and has an input and output. "he common terminal shared by input and output is grounded in the diagram below. (+ote the ground symbol.)

Ground is the !

node"

Holtage measurements are made relati e to ground unless otherwise noted. 1n general, the common terminal of the di ider need not be at ) H. "he general circuit for a oltage di ider, with common node at ground, is shown below.

"he input loop has three series elements3 vin (source), ). and )2. Applying KH= results in3 vin 7 vD. 8 vD2 At the output loop, the sensed oltage, vout, is3 vout 7 vD2 "hen the ratio of output to input oltage (the scale-factor) is3

"he oltages on the right side of this equation can be e#pressed in circuit element alues by applying BhmIs =aw. =et the input-loop current be i. "hen vD. 7 i ). vD2 7 i )2 Also by BhmIs =aw, i 0 vin&(). 8 )2) Substituting and simplifying,

"his is the basic oltage-di ider equation. 1t e#presses the scale-factor or attenuation of oltage from input to output. "he input nodes (input and common) are the pair of terminals across which the input oltage occurs. Such a pair is called a port. "he output port has vout across its pair of terminals. 0y con ention, current flowing into a port 8 terminal is positi e. A current di ider scales current in the )2 branch of parallel resistors with input current of iin to the parallel pair. "hen iout 7 i2 and the current-di ider formula (sol ed using K'=) is3

'urrent di iders attenuate current. +ote that )., not )2, is in the numerator.

The&enin"s and +orton"s Theorems

"he eninIs theorem is a way of simplifying circuits with (independent) sources to that of a single oltage source in series with a "he enin equi alent resistance. "his is the same equi alent circuit that was used earlier to model actual oltage sources. 1n general, an arbitrary circuit, as shown below, has a "he enin equi alent circuit, shown to the right. "he "he enin oltage source and resistance can be found as follows. "he "he enin oltage is found by lea ing the output port open. +o current will flow through )th and vth 7 voc where voc is the output open-circuit oltage. "he "he enin resistance is found by shorting the output and measuring the

resulting output short-circuit current, isc..

"hen )th 7 vth&isc Analytically, voc and isc are found by applying the basic circuit principles3 BhmIs =aw, KH= and K'=. 4mpirically, open-circuit oltage and short-circuit current are measured at the output. +ortonIs theorem reduces the same !ind of arbitrary networ! to a +orton equi alent circuit3 a current source, in, in parallel with a +orton equi alent resistance, )n. A +orton equi alent circuit can be deri ed by finding the "he enin circuit. "hen the +orton alues are3 in 7 vth&)th )n 7 )th

Superposition
=inear circuits (such as the abo e) with multiple sources can be sol ed for oltages and currents by sol ing the circuit for one source at a time while nulling (setting to *ero) the others3 oltage sources are shorted and current sources are opened. Add the results from each solution for each node ( oltages) and branch (currents) to get the combined (total) result. 1deal oltage sources ha e *ero resistance (shorted); ideal current sources ha e infinite resistance (open). "he following e#ample circuit demonstrates the use of "he eninIs and +ortonIs theorems and superposition. "he ;schematic; diagram uses a new symbol that of a battery for the .2 H oltage source. 1t is functionally identical to an ideal oltage source. A more common way to indicate a oltage source is to use a label, such as E H, to indicate that a E H source is connected from that node to ground. "o find the open-circuit ("he enin) oltage, use superposition. 0eginning with the .2 H source, null the E H source by replacing it with a short (to ground). "he resulting oltage di ider can be sol ed for vout. 9sing the di ider formula and sol ing,

Similarly, nulling the .2 H source and sol ing for the oltage contribution from E H,

"he superposition of these oltages results in

vth 7 @.2E H 8 ( ..E/ H) 7 /./F H "he easy way to sol e the abo e circuit for its "he enin equi alent resistance is to note that the ..) !, .2 H branch is in parallel with the 2.2 !, E H branch to ground. Holtage sources ha e ) resistance. 'onsequently, the equi alent resistance at the output port is 2.2 ! MM ..) !, or using the parallel resistance formula, )th 7 /@L.E "he "he enin resistance can also be found by shorting the output port and sol ing for the current. 9sing BhmIs =aw twice and K'=, isc 7 .2 H&..) ! 8 ( E H)&2.2 ! 7 F.LA mA "hen )th 7 vth&isc 7 /./F H&F.LA mA 7 /@L.E in agreement with the parallel-resistor result. "he +orton equi alent circuit is readily calculated from the "he enin circuit and is shown below. "he source symbol is that of a current source.

where in 7 isc 7 F.LA mA )n 7 )th 7 /@L.E

,nit Prefi-es
1n the pre ious e#ample, mA was used as a unit of current and ! for resistance. 4ngineering prefi#es for units are commonly used. "he most used are3 #nit Prefi$ Prefi$ %ame &ulti'lier

pico

.)-.2

nano

.)-F

micro

.)-/

milli

.)-A

!ilo

.)A

<

mega

.)/

giga (;5ig-a;)

.)F

Basic .easurement Instruments

"he most basic electronic test and measurement instrument worth owning is the digital multimeter ($<<). ,or about N.)), a meter (such as a 0ec!man $<2LO= or equi alent, for about N/)) measures oltage, current, resistance and other quantities (frequency, capacitance) and tests transistors and diodes. Bn low-resistance ranges, continuity (electrical connection of wires) can be tested by an audible beep. A big step up from a $<< is an oscilloscope, which plots a graph of input (probe) oltage ersus time. A Pscope is a ;window; into dynamic (changing-in-time) circuit beha ior. Holtage and time scales are ad5ustable (; olts&di and ;time&di ;). "he Pscope screen is li!e a window, and can only show a segment of the ongoing oltage function (or 'aveform) in time. Some way of selecting the alignment of this displayed window in time is needed. "he trigger system is used to start the trace on the screen at the same point on a repetiti e wa eform for each sweep of the beam across the face of the screen. 0y tracing out the same wa eform each time, the displayed trace loo!s stable. (hen the triggering is not correctly ad5usted, many different traces are drawn, showing an unstable display. "rigger source, mode, slope and le el controls are ad5usted to ma!e the trace stable. 1nstability is usually due to the trigger le el being set to outside the ma#imum bounds of the wa eform on ;normal; triggering mode. ;Auto; mode !eeps the trace going (to show the nowa eform baseline of ) H) and is generally the most useful mode. (hen iewing wa eforms of less than E) H*, howe er, normal mode is necessary for stability. Bscilloscopes come in two ma5or categories nowadays3 analog and digital. Analog Pscopes are unable to capture transient (one-time) wa eforms but are low-cost and show a continuous wa eform. $igital storage oscilloscopes ($SBs) now sell for under N.))) and are able to capture (or ;store;) single-shot e ents by sampling the input wa eform at points in time, resulting in a discrete (not continuous) display. "ransient capture is useful for roc!etry since firing e ents are not repetiti e. $SBs are a !ind of data acquisition system with a front-panel instead of a computer as interface. Another useful test instrument is the power supply. Supplies are required as subsystems in electronic equipment, but a general-purpose test-bench supply, with multiple outputs, including one or more with ariable output oltage, can e#pedite system testing.

'eactance
Desistors dissipate electric energy but do not store it. "he two basic !inds of circuit elements (ideali*ed components) that store energy are capacitors and inductors and are called reactances. "hey are duals of each other because the beha ior of one is the same as the other with oltage and current interchanged. Deactances are inherently dynamic and their beha ior depends on the rate of change of their current and oltage wa eforms.

Capacitors
'apacitors are components that store electric charge, *. "he charge is stored in electrically insulating (or dielectric) material that is between two conducting plates or sheets. A capacitor is analogous to a charge storage tan! and its alue is defined as

where , is capacitance, with units of farads (,), v is oltage, and d is ;an infinitesimal change in.; 1n other words, capacitance is the change in charge o er the change in oltage. (9sing notation from calculus, , is the deri ati e of * with respect to v; that is, it is the instantaneous slope of * plotted against v. ,or a constant capacitance, the slope of the *-v line, *&v, is ,. d*/dv is the slope of a line tangent at a gi en point on any continuous cur e.) ,or constant ,, , 7 */v. A farad is a coulomb& olt. 0ut a coulomb is an ampere-second (A s) so a farad is an As&H. 0y BhmIs =aw, a farad is the same as , s&, or a second per ohm. 'apacitors can be made by wrapping a plastic film (such as polycarbonate, polyester or polypropylene) between two sheets of aluminum foil. "he sheets are offset on the film so that each e#tends beyond the film at opposite ends. "he ends are crushed together and attached to metal leads. A capacitor can be constructed out of the plastic and aluminum films found in !itchens. 'apacitance in terms of geometry is3

where is the permittivit# (or dielectric constant), A is the area of the dielectric and l is its thic!ness. "he permitti ity has units of ,&m and is a measure of the ability of the insulator to store charge. "he permitti ity of acuum is ) 7 .&A/ n,&m or about @.@E p,&m. )elative permittivit#, r, is a factor multiplied to ) to produce total permitti ity3

7 r)
,or e#ample, !itchen plastic wrap (poly inylidene chloride) has r A.E ( A. p,&m) and a typical thic!ness of .E m ()./ mil). "hen a . inch (2E.? mm) wide by . foot (A)?.@ mm) long piece will ma!e a capacitor of ./ n,. 6ust as BhmIs =aw gi es the v-i relationship for resistors, the v-i relationship for capacitors can be found from its definition and the definition of current, i 7 d*/dt3

Sol ing for dv/dt, the rate of change of oltage across the capacitor is i/,. ,or a constant current flowing into ,, the oltage increases linearly. "he oltage ramps up for a step in current applied to it.

Although the current instantaneously steps to its alue, 2, the oltage ;lags; in its response. ,or a resistor, v would ha e the same wa eform as 2, a oltage step of ) 2. "his time dependence of capacitance is reflected in its unit (, 7 s&), which includes time as a basic quantity. As oltage increases, the electric field across the dielectric also increases until its brea!down oltage is reached and the dielectric material fails structurally. 'apacitors are specified for a ma#imum allowable oltage. "he highest charge density is achie ed in electrol#tic capacitors. "hey are also polari*ed and mar!ed for proper oltage polarity. De ersing the oltage on an electrolytic capacitor can destroy it e#plosi ely. "wo of them in series with opposing polarities can be used for bipolar ( ) applied oltages. 'apacitors in parallel add and in series, the total capacitance is li!e parallel resistors. "hese formulas can be deri ed from the abo e equations.

,parallel 7 ,. 8 ,2 ,series 7 ,. ,2&(,. 8 ,2) Inductors

1nductors store magnetic flu!, , in a magnetic field that is created by closed loops of current flowing in conductors (usually wires or circuit-board traces). 4ach loop produces a gi en flu# and is related to the magnetic flu! lin3age, , by the number of turns3

7 N
,lu# lin!age is the dual of current and is defined as

<agnetic flu# and flu# lin!age ha e units of H s. "he definition of inductance is3

,or constant L, L 7 /i. 1nductance has units of henries, H, which is the same as a olt-second&ampere. 0ecause H&A is , H s. 1nductance also has a time-dependent unit and, li!e capacitance, will ha e a time-related circuit response.

"he magnetic field of an inductor is concentrated within the current loop(s) and the amount of flu# stored depends on the permea%ilit# of the material containing the field. "he permeability of acuum or air is ) 7 ?)) nH&m ..2/ H&m. "he relati e permeability, r, of ferromagnetic materials, such as iron or ferrites, is ery high typically se eral thousand. "otal permeability is3

7 r )
A magnetic field will concentrate in (be contained by) high-permeability materials while being wea! in air. High- materials consequently can be used to shield circuits from stray magnetic fields. "he flu# produced by a gi en current, i, is proportional to the per-turn-s*uare inductance, or permeance, L:

7 L(N i)
"he terminal current is multiplied by the number of current-loops, or turns. A winding with N turns is equi alent to N

indi idual loops with current i. "he magnetic circuit ;sees; a current of (N i). %ermeance is also related to the geometry of the inductor by a formula li!e that for capacitance3

where A is the current-loop area containing the flu#, and l is the closed-path length of the flu#. "hese equations can be combined to find L by substituting for in the defining equation3

1nductance aries by the square of the number of turns. Substituting for the permeance,

A constant oltage applied across the terminals of an inductor will cause the current to increase linearly or ramp up. "his will continue until the flu# e#ceeds the ability of the magnetic (core) material to sustain it, and the inductor saturates, with a sharp decrease in inductance. "he v-i relation for inductance is found by substituting for d in its definition3

"hen sol ing for v,

1nductors in series add and in parallel are li!e resistors, assuming they share no flu# in common.

Lparallel 7 L. L2&( L. 8 L2) Lseries 7 L. 7 L2 Impedance

"he concept of resistance can be generali*ed to include reactances. "his more general ;resistance; is called impedance,

where ) is resistance, 4 is and 5 is reactance. ((e use 4 instead of i to a oid confusion with the symbol for current.) 1mpedance is a comple# number, with real and imaginary alues. Desistance is the real part of impedance; reactance is the imaginary part. 'omple# numbers can be represented as two-dimensional ectors. (hen plotted, the hori*ontal a#is is the real a#is and the ertical is the imaginary.

Shown abo e, 6. 7 2.2 ! 8 4..E ! . (hen added to 62, the sum is3

"o add comple# numbers in rectangular form, add the real and imaginary components indi idually. 'omple# numbers can also be represented in polar coordinates, with a magnitude (length of ector) and phase angle. "o con ert impedance from the rectangular form to polar form,

"he abo e impedance is con erted to polar form as

"he impedance ectors shown in the abo e diagram ha e ) and 45 alues as rectangular-form components. "he polarform magnitude is geometrically the length of the 6 ectors and their angle from the )-a#is is the phase angle. "o multiply comple# numbers in polar form, multiply the magnitudes and add the angles3

"o add comple# numbers in polar form, they must be con erted to rectangular form first3

"his rectangular form for 6 can also be written as a single mathematical e#pression by use of $uler7s formula, which relates trigonometry to comple# numbers3

Applying 4ulerIs formula to 6 abo e, the polar form for 6 results in a single e#pression3

1mpedance allows us to e#tend our e#isting circuit analysis techniques to circuits with reactances. (e now use impedance as we ha e resistance to sol e circuits once we ha e the reactances of capacitors and inductors. "he unit of reactance is the same as resistance (), or v&i. "o sol e the v-i relations for , and L, we first need the concept of comple# frequency. ,omple! fre*uenc#, s, is3

s 7 8 4
'omple# frequency is related to the deri ati e of a quantity with respect to time3 s ! d!/dt where ! is oltage or current. "hat is, whene er s is multiplied by a ariable, !, it can be transformed to the time domain as the deri ati e of ! with respect to time; s ! thus represents the rate of !. 9sing this approach, apply it to the v-i relations abo e for , and L to get3

,rom BhmIs =aw, we !now that v/i is a resistance. 1mpedance is e#pressed in the comple#-frequency domain ( sdomain) by sol ing the abo e equations for v&i.

"hese impedances can be used in circuit analysis in the same way ) is used for resistors. 0ecause s represents a

frequency, reactances are frequency-dependent. ,rom them, at a frequency of *ero (dc), capacitors are open circuits and inductors are short circuits. At infinite frequency, capacitors are shorts and inductors open.

Time and Fre%uenc* 'esponses

"he quic!ness of response of amplifiers and other circuits can be characteri*ed by their output when a step wa eform is applied to the input. "his is sometimes called the step response and is a function of time (in the time domain). "he step response of a capacitor to a current step input is a oltage ramp output. ,or a step input, a circuit that is underdamped will output a step wa eform that o ershoots the final step le el and oscillates or ;rings; about it for a while. An overdamped response does not o ershoot but ta!es e#cessi e time coming up to the final alue of the step. A response that rises in minimal time without o ershooting is called criticall# damped. "he time that a step wa eform ta!es to go from .) J to F) J of its final alue is called the risetime.

Steps are usually generated repetiti ely as s*uare-'aves. 4ach repetition of the square-wa e lasts long enough for circuit beha ior to reach constant alues, as though the square-wa e lasted fore er, li!e a step function. Square-wa es are obtained from electronic instruments that are wa eform sources, such as function generators or pulse generators. "he square-wa e period is set to be long enough (low enough square-wa e frequency) to gi e the step response adequate time to decay away so that the full response can be iewed on an oscilloscope. Step response is one way of obser ing the effect of circuit self-beha ior, which is called the transient response or natural response. (hen a reacti e component in a circuit contains energy, the response of the circuit to that energy is the transient response. 9nless the circuit is purely reacti e (no resistance), then this energy will e entually be dissipated, and the transient response will decay away in time. "he transient response is the beha ior of the circuit with no continual input applied. Another approach to analysis of circuit dynamics is in the fre*uenc# domain. Sinusoids (sine-wa es) of constant amplitude are applied to the input of a system and their frequency is aried. As frequency increases, the limited quic!ness of circuit response will cause the amplitude to decrease, or ;roll off; with increasing frequency. "he frequency at which roll-off becomes significant is called the %and'idth. 1n addition, the output sinusoids lag behind the input by some number of degrees of a cycle by some amount of phase (angle). 0oth amplitude (magnitude) and phase are affected by frequency and characteri*e the sinusoidal response. "he magnitude of (vo&vi) is the gain of the circuit as a function of frequency. 1ts phase ersus frequency is also significant. (hen plotted, they are called (ode or fre*uenc# response plots. 0ecause the frequency response depends on frequency, not time, it is the stead#-state response. "he total dynamic response of a circuit is the sum of the two responses3

(otal res'onse ) transient * steady+state

After enough time, the transient response decays away and the steady-state response alone is left. (hen the input wa eform is a sinusoid, the steady-state response is the frequency response. 1n practice, frequency response can be measured by networ! analy*ers (e#pensi e instruments), spectrum analy*ers (now under N.))), but good for frequencies abo e .)) !H* to . GH*), audio sine-wa e generators and the sine function of function generators. Sweeping function generators ary (or ;sweep;) their frequency linearly or e#ponentially (to gi e a log plot), and the output amplitude of the swept sine-wa es traces the magnitude of the frequency response on an oscilloscope. A slower way of obtaining frequency response is to use a fi#ed-frequency (non-sweeping) sine-wa e generator and measure output amplitudes at se eral frequencies with constant input amplitude. "hen plot the points. "he transient response is caused by initial energy in reacti e components3 oltages across capacitors or currents through inductors. "he circuit responds to this energy and its beha ior is the transient response. "he remaining steady-state

response is caused by a periodic input wa eform, and is also called the forced response. 1n summary, the two responses are3

transient3 time-domain response steady-state3 frequency-domain response

'eactance in the s-Domain

An elegant aspect of the use of comple# frequency is that the transient response results from the real component and the frequency response from the imaginary component. 0y substituting s 7 4 into the impedance formulas for , and L abo e, the reactance alues of each are obtained3

where 7 2 f and f is frequency, in Hert* (H*); is the ;radian frequency.; ,urthermore, because s is in the denominator of 6', its imaginary component contains .&4 7 4. An imaginary number is plotted on the ertical (imaginary) a#is of a comple#-number plot and consequently has a phase angle of F) deg. And a negati e imaginary number (such as 4) has an angle of F) deg. 1n polar form, 4 7 ., F) deg and 4 7 ., F) deg. %lots of impedance magnitude ersus frequency are called reactance plots and are con eniently o erlaid on reactance charts which ha e alues of ), L and , already drawn. (See reactance chart.) Halues of ) are hori*ontal lines. Halues of 5= increase with frequency and are parallel lines with a slope of . (8?E deg) on a log-log scale; alues of 5' ha e a slope of -. ( ?E deg) and decrease with frequency.

Circuit Anal*sis in the s-Domain

An e#ample of circuit analysis in the s-domain is the oltage di ider consisting of a resistor and capacitor, as shown below.

"he di ider formula is applied using the abo e impedance for ,3

(hat is the transmittanceC 1t is a comple# number that aries with frequency, s. 'omple# gain A (s) can be represented as ha ing a magnitude, A , and an angle, . ,requency response is found by substituting s 7 4 and reducing to polar form.

+ote that angles follow the rules of e#ponents. An angle in the denominator is negated when mo ed to the numerator. (hen the magnitude and phase gi en here are plotted ersus (or f), the following frequency-response plots result.

"he frequency at which the amplitude decreases by a two-port networ!.

is called the %and'idth, fbw, and is a measure of the speed of

Appro-imate Fre%uenc*-'esponse from the s-Domain

"he frequency response plots for the D' integrator can be closely appro#imated with line segments on a log-log chart of magnitude ersus frequency, , and a semi-log chart of phase ersus . "hese ;asymptotic appro#imations; are shown below for the D' integrator.

"he straight-line appro#imation for magnitude is hori*ontal (or ;flat;) out to the brea! frequency, fb, and then decreases (or ;rolls off;) at a slope of -.. "he phase is flat to a decade before fb, then decreases at -?E &decade, crossing -?E at fb, and becoming flat at -F) at .) fb. Ha ing sol ed for the transmittance (out&in) of a circuit, the general form is a rational algebraic e#pression in s of the form3

,or the D' integrator, K 7 ., p. 7 -.&),, and there are no &., &2, "he rational e#pression is what results algebraically when the polynomials of both numerator and denominator are factored. "he &i are called &eros and are the roots of the numerator polynomial; the pi are called poles and are roots of the denominator polynomial. "he poles characteri*e the transient response of the circuit and the *eros characteri*e the steady-state response. K is the dc response, the frequencyindependent amplification or attenuation of the circuit. %oles cause the frequency response to decrease with frequency, or ;roll off.; Qeros cause the opposite effect. "his can be demonstrated by the following circuit.

"he transmittance of this circuit can be determined by applying basic circuits laws, using .&s, for the impedance of the capacitor. After some algebraic manipulation, the result is

where ).MM )2 7 )p is the alue of ). and )2 in parallel. "he circuit has a dc gain equal to the oltage di ider formula, for without , it is a resisti e di ider.

"his ;lead-lag; circuit has a single pole at the comple# frequency, p 7 -.&)p ', and one *ero at frequency & 7 -). ,. 0ecause resistors ha e positi e resistances, )p R )., and the pole will always be at a higher frequency than the *ero. "he asymptotic appro#imation of its frequency response is shown below. "he *ero has the opposite effect of a pole; it causes the magnitude plot to increase at a 8. slope at the *ero frequency, f* 7 .&2 ). ,. "he phase increases at 8?E &decade until it reaches the influence of the pole phase, at fp. "he slopes of *ero and pole cancel and the phase is flat until .) f*, where the *ero loses its influence. "he pole then rolls the phase off until a decade past the pole frequency, at .) fp. "he pole also cancels the 8. magnitude slope of the *ero, resulting in a flat response from fp to higher frequencies. 0y using the pole and *ero appro#imation rules, magnitude and phase plots can be constructed for any combination of poles and *eros. 0ut there is one complication. ,rom algebra, a polynomial can be factored into products that can contain not only real roots but also comple# ones which appear in pairs, symmetric about the real a#is, in the form3

s 7 - 4
where - is the real component and 4 is the imaginary component. 'omple# poles and&or *eros can appear in the transmittances of circuits with two or more reactances. "he number of poles will equal the number of reacti e components and also be the degree of the denominator polynomial. ,or arbitrarily complicated circuits, both numerator and denominator of the transmittance will consist of products of first and second-degree factors. "he first-degree factors will be real and the (reduced) second-degree factors will be comple# or imaginary. 'omple# poles and *eros cause resonances in circuits. "he two !inds of resonances are series and parallel resonance. "he linear appro#imations for resonances can be ery inaccurate around the resonant frequency when the resonance is highly underdamped. "he appro#imate frequency response plots for resonances are shown below.

"he phase slope depends on how underdamped the resonance is, as does the magnitude pea! at resonance. A parallel resonance changes from a 8. to a -. magnitude slope through the resonant frequency, fr, and a series resonance changes from -. to 8. slope. A series resonance can occur when an inductor and capacitor are in series, and a parallel resonance when in parallel. "he resonant impedance in either case is

A series resonance is criticall# damped when a series resistance, )s 7 2 6r; a parallel resonance is damped when a parallel resistance, )p 7 6r&2. 1n both cases, the resistance must equal the alue of the combined reactance of the L and ,. A critically damped circuit has poles that are real but border on being comple#. "he step response for critical damping rises as quic!ly as possible without o ershoot (no ringing). "he resonant frequency of an =' circuit (both series and parallel) is3

Fre%uenc* 'esponse from 'eactance Charts

,or circuits with more than two reactances, the algebraic method of finding the transmittance consists of sol ing ndegree polynomials. "his can be difficult e en for a third-degree polynomial, and are often sol ed numerically for higher-degree polynomials. 0ut before resorting to a computer, there is a graphical method that often produces adequate results using the reactance chart. Series and parallel combinations of D' and D= circuits are shown, with reactance charts. "he method is demonstrated using the following circuit.

"he upper and lower impedances of the di ider are plotted on the reactance chart. "he upper branch is ). and is a flat line on the chart. "he parallel combination of )2 and , is plotted by plotting each separately.

(here )2 crosses ,, , dominates (or ;swamps out;) )2 so that its impedance is appro#imately the combined impedance abo e the frequency where the impedances are equal (which is .&2 )2 ,). "he combined impedance is then the composite plot labeled )2 MM ,.

"he di ider transmittance is found by the oltage-di ider formula, 62&(6. 8 62) 7 62&6in. 6in is plotted, beginning at ). 8 )2 and e#tending to brea! frequency .&)2 ,. 1t then decreases to ).. (here it meets )., a dotted line is e#tended down and intersects )2 MM , at the parallel equi alent resistance of the two resistors.

0ecause the plot is log-log, di ision is accomplished by subtraction. 62 and 6in maintain equal ertical separation until 6in flattens out at ). while 62 continues to roll off. "his results in a frequency response magnitude plot that is flat out to .&(). MM )2) ,, then rolls off with a -.slope. "he reactance chart impedances and transmittance for the lead-lag circuit are shown below.

"he difference between )2 and 6in decreases at frequency .&). ,; the denominator of the impedance di ider, 6in, is decreasing, causing vo&vi to increase, until 6in flattens out. At that frequency, .&(). MM )2) ,, the capacitor is essentially a short and passes vi to vo. "he transmittance is then one.

Time-Domain 'esponse
"he time-domain response can also be appro#imated from the s-domain circuit transmittance. "he real component of a pole causes an e#ponential response of the form e-t& , where is the time constant,

7 .&
and is the negati e real component of the pole. ,or a real pole of an D' circuit, 7 ) ,, and for an D= circuit, 7 L/). "he step response of a real (negati e) pole is an e#ponential rise with time constant . After one time constant, the step has risen to e-. /A J of the final alue. After E , the e#ponential is within . J of the target alue. A measure of the speed of response to a step is the risetime, the time the response ta!es to go from .) J to F) J of the target alue. ,or single-pole circuits with time constant, , the risetime is

tr 2.2
A ? H step applied to an D' integrator results in the oscilloscope wa eform shown below, where ) 7 ..)) ! and , 7 .) n,. "he time constant is

7 ) , 7 .)-E s 7 .) s

"he wa eform rises to about /A J of ? H, or 2.E H in .) s, and after E , or E) s, it has reached the target alue of ? H.

"he D' differentiator, under similar conditions, beha es similarly, as shown below. 1n this case, the wa eform steps to ? H, then decays to its ) H target.

,or comple# poles at - 8 4 , the real (- ) component ( S )) causes a decaying e#ponential response as before, but the imaginary component causes a sinusoidal response. <athematically, this follows from 4ulerIs equation3

<ore generally, the response of a pole at s 0 - .4 is3

where is the phase angle of the sinusoid. "his time response is a decaying sinewa e. "he following D=' circuit was built and the step response acquired.

"he response to a ? H step at vo is shown below, and is underdamped. "he wa eform o ershoots the ? H target and oscillates (or ;rings;) around it. "he ringing is a decaying (or ;damped;) sinewa e. "he pulse generator that supplied the step had a .)) output resistance, and this generator resistance was in series with the =' circuit. "he ringing is no longer discernible after about two cycles. "he comple# pole can be e#pressed in polar form, as a magnitude and angle, , relati e to the (negati e) real a#is. ,or negati e real poles, 7 ), and the response is a decaying e#ponential. ,or 7 F) degrees, the pole is imaginary and the response is a non-decaying sinusoid. Bn the 4 a#is, 7 ), and the time constant of a pole on the 4 a#is is .&) or infinite. 1n other words, the decay time is fore er. ,or poles with angles in between ) and F) degrees, the closer the angle is to F) degrees, the more underdamped is the response. 0y counting the cycles on an oscilloscope, Ns, the pole angle can be estimated.

Ns + cycles ) ).A )./ . 2 E

"he pole angle of a series resonant circuit is

+ degrees
) A) ?E /) LE @?

and for a parallel resonant circuit, it is

"he pole angle for this series resonant circuit is calculated by first finding the resonant impedance,

"hen is cos-.T).2LEU L? . "he resonant frequency is

0ecause period is the reciprocal of frequency,

"r 7 ...? s
(hen a sinuosid is damped, its frequency decreases to

1n this case, sin ).FF and "d ...E s. 0y noting that the time scale of the oscillograph is E)) ns per di ision (spacing between dotted ertical lines), or E)) ns&di , the period of the oscillation is about . s. "he wa eform pea!s at about E.E H, or has an o ershoot of E.E H - ? H 7 ..E H. "he ratio of o ershoot to target oltage is the fractional overshoot, 8p. "he pole angle can also be calculated from it as

1n this case, 8p ..E H&?.) H 7 ).ALE, and LA , in good agreement with the other calculation. ,inally, because time and frequency responses are related, risetime and bandwidth are related for circuits near critical damping by the appro#imation,

tr ).AE&fbw

Closure
"he concept of resistance was e#tended to include reacti e circuit elements, capacitance and inductance, as impedance, a comple# number in ol ing comple# frequency, s. (ith reactances e#pressed in s, we could apply circuit laws (BhmIs =aw and KirchhoffIs laws) and de elop transmittances for two-port circuits. 0ecause the algebraic e#pressions for transmittances in ol e sol ing nth-degree polynomials for their roots (poles and *eros), a graphical method was introduced based on the reactance plots of circuit impedances. ,or single-pole circuits, arious circuit properties were de eloped, such as the time constant and bandwidth. ,or a single comple#-pole pair, the concept of resonance, with its resonant impedance, 6r, and resonant frequency, fr, were e#pressed in circuit component alues L and ,. "ime-response characteristics such as risetime can be related to frequency-response characteristics, such as bandwidth. "he principles illustrated here all in ol ed passi e circuits (no transistors or op-amps, etc.), but can also be applied directly to acti e circuits. "his article has merely introduced the analysis of circuit dynamic response theory, but these basic concepts and analysis methods should be adequate for the simpler (and most common) circuits encountered in electronics applications, and for understanding the terminology applied to them in the literature.

Diodes
Diodes are electronic de ices made from semiconductor materials such as silicon. 1n their pure form, these materials do not conduct electricity and are electrical insulators. 0ut by adding a small amount of either p or n-type impurity, e#cess positi e or negati e charges are introduced into the bul! semiconductor. "his charge is free to tra el as electrical current, lea ing behind fi#ed ions of the opposite charge bound in the crystalline lattice of the semiconductor material. 0y placing n and p-type material together, a p-n 4unction is formed, as shown below.

"his is a diode. 9pon 5oining p and n materials, positi e charge (called ;holes;) and negati e charge (electrons) diffuse into the opposing material where they encounter opposite charges and recombine; their charges cancel. As charges diffuse, they lea e behind fi#ed charges which tend to impede further diffusion. As holes diffuse into the n side of the 5unction, they lea e fi#ed negati e ions which tend to counter the diffusion of electrons mo ing into the p material. =i!e charges repel. "he fi#ed charges produce an electric field which opposes diffusion and results in a region in which few mobile charges e#ist. "his is the space-charge la#er or p-n 4unction. "he symbol and electrical beha ior of diodes is shown below3

"he arrow part of the symbol is the p side and the ertical bar is the n side. (hen a dc oltage of about ).L H or more is applied in the for'ard direction ('ith the arrow of the diode symbol), current flows. (hen the oltage is less than ).L H (including re erse or negati e oltage), no current flows. "he positi e applied field repels mobile holes, dri ing them toward (and across) the 5unction, o ercoming its opposing electric field barrier. 4lectrons are similarly repelled toward the 5unction and cross it, recombining with holes. <ore charge flows into the diode to replenish recombined holes and electrons and e#ternal current flows. 1f the e#ternally applied oltage polarity is re ersed, mobile charges are attracted to the 8 and applied oltages and away from the 5unction. "his further depletes the regions around the 5unction of charge. (here there is no charge, bul! silicon is an insulator and does not conduct. +o holes and electrons cross the 5unction to recombine and no e#ternal current flows.

"he diode oltage-current (or v-i) relation is shown in the plot below3 Abo e about ).L H of forward oltage, the current increases quic!ly and is ery sensiti e to diode oltage. 1t is difficult to control diode current by attempting to carefully ad5ust the forward oltage. 1nstead, a resistor is usually placed in series with the diode to a oltage source, as shown below3

0ecause the supply oltage (.2 H) is so much larger than the diode oltage ().L H), most of its oltage is dropped across the resistor, which dominates in setting the current. "he dc operating-point of ).L H and ...A mA are the %ias oltage and current of the diode.

Bipolar /unction Transistors

"ransistors are two diodes 5oined with a ery thin common region, the %ase. (hen the base-emitter (%-e) 5unction is forward biased, mobile charges from the emitter cross the %-e 5unction. Some recombine, resulting in base current. 0ut because the base is so thin, most cross the base-collector (%-c) 5unction, which is re ersed-biased. "he charges from the emitter are minorit# carriers in the base and are attracted across the %-c 5unction to become collector current. (hat ma!es transistors so useful as circuit elements is that a small amount of base-emitter current controls a larger amount of collector-emitter current. A small electrical input can be amplified by a transistor. "his !ind of transistor is the %ipolar 4unction transistor (06"). "he two polarities of 06"s are npn and pnp. "heir symbols are shown below3

4ach has three terminals3 %ase+ emitter+ collector. A small amount of current flowing into (out of) the base of an npn (pnp) causes a flow of current times larger from collector to emitter (emitter to collector), in the direction of the arrow. "hat is, ic 7 ib 0eta () is typically about .)) in small-signal transistors and 2) in power 06"s. "he base and collector currents 5oin in the emitter so that ie 7 ib 8 ic 7 ( 8 .)ib

A small amount of base current thereby controls a larger amount of emitter and collector current. "he base current results from a forward-biasing base-emitter oltage, v04.

D*namic 'esistance
0y BhmIs =aw, v/i is a resistance. (hat is the resistance of a diodeC ,rom the abo e v-i cur e, )d 7 ).L H&. mA 7 L)) "his resistance is the in erse-slope (.&slope) of a line from the origin to the point ().L H, . mA) on the diode cur e. "his is the static (or dc) resistance. ,or a small ariation of oltage around ).L H, the change in current is much larger (lower resistance). "his d#namic (or ac) resistance is the in erse-slope of a line tangent to the cur e at the operating point+ which is ().L H, . mA). $ynamic resistance is calculated from the solid-state equation for p-n 5unctions as3

where i is the diode current. ,or the gi en operating point ( i 7 . mA), rd is 2/ for small changes around the operating point. "his diode dynamic resistance is much smaller than the static resistance.

Common- mitter Amplifier

06"s ha e two diodes (or p-n 4unctions)3 base to emitter and base to collector. 1n an npn 06", the %-c 5unction is normally re erse-biased. (hen it is forward-biased, the base is ).L H greater (more positi e) than the collector. "his state is called saturation. (hen 06"s are used as switches (as in digital or computer circuits) they are either off (no %-e or %-c forward bias) or else ;full on; (saturated3 %-e and %-c forward biased). ,or linear amplification, the %-c 5unction is re erse-biased (off) and the %-e 5unction is forward-biased (on). 0oth input and output wa eforms ha e a range they must stay within. A simple one-transistor amplifier can be built as shown below, using both positi e and negati e supplies3

"his circuit has two loops3 input and output. ,or the input loop, a change in the input oltage vin causes a change in oltage across )4 and the transistor %-e 5unction dynamic resistance, re. "o find re the static emitter current must first be found before the dynamic resistance can be calculated. (See the equation for rd abo e.) "herefore, sol ing transistor or diode circuits (those with nonlinear elements) has two steps3 .. Static circuit analysis3 operating point(s) or %ias .. $ynamic circuit analysis3 dynamic resistances and amplification "o sol e for the static currents and oltages, we obser e first that if Vbe of the transistor is about ).L H and vin has no static oltage component (V04 7 ) H), then the EH supply is applied across ).L H in series with )4. "his circuit is ..) ! or ?.A mA. "he base current is 24&( 8 .) or (for 7 FF) ?A A. "he collector current is the emitter current less the base current. "he ratio of collector to emitter current is called alpha (), defined as similar to the pre ious diode circuit, where )4 largely determines emitter current. 1n this case, it is about (E H ).L H)&

,or 7 FF, 7 ).FF. "hen 2' is ().FF) (4.3 m) = 4.26 mA. "his current drops (?.2/ mA) (2.2 !) or F.AL H across )= so that the collector oltage (to ground) is3

V' 7 .2 H F.AL H 7 2./A H "his is greater than the base oltage () H) and the %-c 5unction is re ersed biased as required for linear operation. "he static oltages and currents ha e now been determined and dynamic analysis can proceed. "he dynamic emitter resistance is 2/ mH&24 or about / . "he total resistance across which vin is applied is the transresistance r<3 r< 7 re 8 )4 7 / 8 ..) ! ..) ! 0ecause re aries with temperature and static emitter current, in good design it is dominated by )4, a stable resistor, so that r< is stable; it affects the amplification or voltage gain (A ) which is3 A 7 vout&vin where vout and vin are dynamic oltages. "he significance of r< is that it determines the emitter current3 r< 7 vin&i4 "he emitter current does not flow in the base circuit, where the input oltage is applied. "he current goes somewhere other than through the input oltage source, vin. 'onsequently, r< is a ;transfer resistance; or transresistance. And transistor is short for ;transfer resistor.; +ow that i4 is calculated from vin and circuit elements of the input loop, i' is 5ust i4 and the change in oltage it causes across )= is vout 7 )= i4 "he minus sign is the polarity of the oltage change at the collector (to ground). An increase in collector current causes an increase in oltage drop across )= which subtracts from the collector supply (.2 H), causing a decrease in collector oltage. (e ha e wor!ed our way from input to output. %utting the abo e equations together, the gain is3

0esides , the gain is a ratio of two resistances, the collector (or ;load;) resistance and the transresistance. "his is the general form of amplifier gain e#pressions. ,or our e#ample, A 2.2. "he output oltage range is about A H and is limited by saturation at its minimum and cutoff (*ero collector current) at its ma#imum. "his design is saturation limited. ,or ma#imum linear dynamic range (largest undistorted output wa eform), the collector oltage operating point would be about / H, halfway between saturation and cutoff. 'alculation of saturation must also ta!e into account base oltage, which is ma#imum (positi e, not *ero) when collector oltage is minimum. 1t is found from the gain e#pression.

B/T .odel
A 06" circuit model for a transistor biased in the linear region of operation (a d#namic model for small ariations around the operating-point alues) is shown below3

"he collector is connected to a current source controlled by the base current. 'ollector oltage ariations across the

current source (which has infinite resistance) do not affect the collector current. "he collector is thereby isolated from the base-emitter input circuit. "he !ey model element is the dependent current source, which pro ides amplification. "he dynamic base resistance is not re, though it is across the base-emitter terminals. 0ase resistance is greater because the collector current also flows through re in response to base current. "he resulting base-emitter dynamic resistance can be deri ed as the ; transform; formula3

"his equation says that resistance from the base will be 8 . times larger than that in the emitter. "his applies to all resistance through which the emitter current flows. 1n the amplifier circuit of last section,

or (.)))(1006), somewhat more than .)) !. "he output resistance of the abo e amplifier (from collector to ground) is that of a current source in parallel with the load resistor, )=. 'urrent sources ha e infinite resistance (appear as open circuits), lea ing the load resistance as the output resistance. "he significance of input and output resistances is discussed in ;0asic Amplifier 'ircuits.; "he collector characteristic curves for an npn 06" are shown below. "he collector current is plotted as a function of collector-to-emitter oltage, with base current as a parameter, stepped by 20 for each new cur e. "hese cur es are plotted by an instrument called a transistor curve tracer. +ote that for these cur es, the E) A base current cur e is at about the E mA collector-current le el. "he is therefore about E mA&E) A, or .)).

"he collector cur es are not flat but increase slightly with collector oltage. ,or the gi en transistor model, the cur es would be flat because the collector current-sourceIs current output is not affected by the oltage across it. 0ut actual transistors are better modeled by including a resistance (ro) from collector to emitter. 1t typically has a large alue and

can usually be disregarded. "he collector cur es slope downward toward the left and intersect the v'4 a#is at VA, the ;4arly oltage;3

VA is typically E) H. "hen for 2, 7 . mA, ro 7 E) !. A second feature of the collector cur es is that they oltage ;saturate; below (in this case) ).. H. "his suggests that the base-collector diode becomes forward biased at a v'4 of ).. H, or H'0 7 ).E H. ,or pnp 06"s, the cur es are similar but currents and oltages are of opposite polarity. Such cur es are found in the third quadrant (negati e v'4, negati e i') with negati e i0. Ha ing both polarities of transistors leads to greater fle#ibility in circuit design.

Field- ffect Transistors

,ield-effect transistors (,4"s) operate differently than 06"s. 1nstead of a base, there is a gate to which a oltage is applied. "his oltage creates an electric field across a channel between drain and source. As the gate-to-source oltage aries, the resistance of the channel aries. 9nli!e 06"s, no gate current flows and the input resistance is infinite.

9unction ,4"s (or 6,4"s) ha e a diode between gate and source which must be !ept re erse-biased for linear operation. 1nstead of a re erse-biased diode gate, metal-o#ide semiconductor ,4"s (or <BS,4"s) ha e a metal gate separated by a thin glass (silicon-dio#ide) layer of insulation o er the channel. 0oth 6,4"s and <BS,4"s ha e the same dynamic model, shown below with their symbols. "he ,4" model is simpler than that of the 06". 1t is a oltage-controlled current source in its linear region of operation. 'ompared to a 06", 7 . and rs is analogous to re but typically has a larger alue, around .)) . A ,4" can be substituted for a 06" in the abo e amplifier circuit and, using these correspondences, dynamic analysis is similar. %channel de ices ha e the same polarity of gate (base), source (emitter) and drain (collector) as pnp 06"s. 6,4"s are depletion-mode de ices because they conduct (i$S ) mA) with *ero gate-source oltage. 0ut almost all a ailable <BS,4"s are enhancement-mode de ices; they are off with *ero gate-source oltage. (hen vGS is around E H for <BS,4"s (or S .2 H for power <BS,4"s), they are ;full on; and operate in the resistance region. "his corresponds to the oltage saturation region of a 06". "he difference is that the channel (drain-to-source) resistance aries somewhat linearly with vGS.

,4"s are characteri*ed by a threshold voltage (pinch-off voltage for 6,4"s), V", of usually about 2 H. ,or n-channel ,4"s, if the drain oltage remains greater than the gate oltage by V", the transistor will operate in the linear region, where the abo e model applies. "o bias ,4"s, a dominating source resistor ()4 SS rs) returned to a supply much larger than the threshold oltage will determine source current and the gate-source oltage will be whate er corresponds to that current. "his approach is essentially the same as that for 06"s e#cept that base-emitter oltages (around ).L H) are smaller than the gate-source bias oltages of ,4"s, which can be o er a olt. ,or linear operation, the drain (on nchannel de ices) must be !ept sufficiently abo e the gate oltage. "he dynamic source resistance rs can be found in the de ice specifications (data boo!) as .&gm.

Po$er Transistors
%ower transistors ha e large emitter&collector areas to handle large currents and&or oltages. "heir pac!ages are made to mount on heat sin!s, to conduct away heat generated by power dissipation in the transistor. =inear amplifiers operate transistors in the linear region (and not as switches) with relati ely high power loss. "hese inefficiencies are minimi*ed by switching transistors between oltage saturation (low oltage, high current) and cutoff (high oltage, no current). ,or both on and off states, either transistor (collector&drain) oltage or current is near *ero. 0y (attIs =aw for power, with units of watts ((), : 7 v i and : ) (. Switching reduces power loss because : is *ero (or nearly so) in both states. $uring the on state, transistor c-e or d-s oltages are not *ero and conduction loss occurs. Also during switching, neither oltage nor current are near *ero and for the brief time it ta!es to switch between states, s'itching loss occurs. 1t increases proportionally with both switching frequency and the switching time. ,or high-power applications, control of power is achie ed by switching transistors on for a fraction of the switching period, D, called the dut# ratio3

As D is aried, the a erage output oltage and current is D V and D 2, where V and 2 are the off- oltage and on-current. =inear control of the average alues is thus obtained by this scheme for switching transistors, and is called pulse-'idth modulation (%(<). 1t is commonly found in motor and other actuator controllers and in power con erters such as switching power supplies. A newer power de ice, the insulated gate %ipolar transistor (1G0") has <BS,4" input and 06" output characteristics. 1t has gate, emitter and collector. 06"s are capable of higher current densities than ,4"s while <BS,4"s ha e no dc gate current. "he disad antage of 1G0"s is that they ha e an additional output series p-n 5unction, with its additional oltage drop. "herefore, 1G0"s are superior for c-e oltages e#ceeding 2)) H. <BS,4"s switch fastest, then 1G0"s, and 06"s are slowest.

Transistor Packages
=ow-power or small-signal transistors usually come as discrete components in "B-F2A pac!ages. %ower transistors come in "B-22), "B-2?L or "B-2)? pac!ages, shown below, with terminals identified3

+ot all 06"s in "B-22) pac!ages ha e the abo e pin-outs of their terminals (though most do). "B-2?L cases are larger than "B-22), but with roughly the same shape. "B-2)? pac!ages mount on a flat metal plate with holes for base&gate and emitter&source terminals, and two holes for bolts that hold transistor, soc!et and heat sin! (which could be the plate) onto the mounting plate. 1nsulators are often required between power transistors and mounting plate. "he 5unction temperature of silicon de ices must be !ept beneath about .E) ' to a oid damage. 6unction temperature, "6, can be calculated from power dissipation, :, and the total thermal resistance, )6A that is, the 5unction-to-ambient (air, en ironment) resistance by the thermal analog of BhmIs =aw3 " 7 : )thermal where temperature drop is li!e oltage, power li!e current, and thermal resistance li!e electrical resistance. 1n particular, 5unction temperature can be calculated from3

where the thermal resistances (in order) are from 5unction to transistor case, case to heat-sin!, and heat-sin! to ambient temperature. "B-22) )9, is typically about . '&( and "B-2)? pac!ages are about a third to a fifth of that. Heat-sin! thermal resistances are gi en in heat-sin! data sheets and ary greatly with air flow, which causes con ecti e heat transfer. Btherwise, the contact of the metal transistor pac!age with a metal heat-sin! (often through a thermally but not electrically conducting insulating pad) allows conducti e heat transfer. "hermal pads for "B-22) pac!ages ha e typical thermal resistances of . degree '&(.

Ideal Amplifiers
A port is a pair of terminals of a networ! (circuit). Across the port is a oltage, v, and through it flows a current, i, as shown below.

Amplifiers ha e two ports, input and output. An electrical 'aveform is a oltage or current as a function of time. A wa eform to be amplified is applied to the input port and another wa eform appears at the output port that is larger than the input wa eform. 1nput and output quantities can be either oltages or currents, resulting in four basic !inds of amplifiers3 Amplifier "ype 1nput Vuantity Butput Vuantity

Holtage, A

oltage, vi

oltage, vo

'urrent, Ai

current, ii

current, io

"ransresistance, )m

current, ii

oltage, vo

"ransconductance, Gm

oltage, vi

current, io

1n the table under amplifier type is the e#pression for amplification or gain (or transfer function), which is the output quantity di ided by the input quantity. 1n general, A 7 !o&!i, where ! is either a oltage or current. An ideal input port is not affected by input source resistance nor is an ideal output port affected by output load resistance. "he general amplifier is shown below3

"he combination source&resistance symbol is a generali*ed source3 either a "he enin or +orton equi alent circuit. "he amplifier has an input resistance )in and output resistance, )out. "he input source, !i (where !i is vi or ii), has resistance )i. 1t forms a di ider ( oltage or current) with )in so that !i !in. Similarly, output resistance )out forms a di ider with

output port load resistance )= so that the output !out 7 K !in !o. "he amplification of !in by K results in !out that is K times larger. K is the gain, and it scales !in. (Gain less than . is called attenuation.) 1f source or load resistance is un!nown or aries with K, then error in the o erall amount of gain results. An accurate (or at least unchanging) gain is required for calibrated sensor circuits, so that the transducer output is multiplied by a !nown (and constant) amount. An e#ample of a oltage amplifier is shown below3

"he o erall oltage gain is3

"he first factor is the input oltage di ider attenuation, the second is the amplifier oltage gain and the third is the output oltage di ider attenuation. ,or the ideal oltage amplifier, A 7 K. "his is achie ed when )in approaches infinity (open-circuit input) and )o 7 ). "he ideal port resistances are gi en in the following table3 %ort "ype 1deal Desistance

Holtage input

infinite (open)

'urrent input

*ero

Holtage output

*ero

'urrent output

infinite (open)

1n practice, good amplifier design approaches the ideal so that input and output loading does not affect the o erall amplifier gain accuracy.

Transistor Configurations
"ransistors ha e three terminals connected to input and output circuit loops. Bne-transistor amplifiers are two-port networ!s; one of the three transistor terminals must be shared by both input and output ports as the common terminal. "his results in three possibilities. "he first is the common emitter ('4) amplifier. "he emitter is common to both input and output, as shown below.

"he emitter is part of both input and output loops. 1t is the common terminal of the transistor that is connected to both an input and output port terminal. (ith a series emitter resistor )4 the emitter terminal is still common to both loops. "he output loop current is shown flowing from the power supply (8V''), through )= and the 06", through )4 to ground, which is connected to the negati e terminal of the supply. "he closure of the output loop from ground to 8V'' implies flow through the oltage-source, 8V''. "he common-base ('0) configuration is shown below3

"he common-collector ('4) configuration, also !nown as the emitter-follo'er, is shown below.

Common- mitter Amplifier

"he '4 amplifier was analy*ed in the Transistors chapter. "he oltage gain was found by the transresistance approach3 a ratio of output (load) resistance and transresistance, the resistance across which the input oltage de elops the common (emitter) current. +ot all of the emitter current gets to the collector. Some is lost to the base, and the factor accounts for this in the oltage-gain equation3

0ecause ., the oltage gain is a ratio of resistances. "he input oltage vi is applied across r<, producing i4 7 vi&r<. "hen i' ( 7 i4) gets through to the collector and de elops a oltage of vo 7 i' )= at the output. 0y sol ing these equations for A , the abo e gain equation results. "he input resistance of the '4 is vi&ii 7 vi&i0 or

"he resistance of the input loop is the base resistance in series with the resistance in the emitter-side of the circuit, referred to the base by the transform. (See Transistors for details.) At the output node, the 06" transistor model shows a current source (infinite resistance) in parallel with load resistance )=. "he output resistance is therefore )=. "he '4 amplifier has relati ely high input resistance due to the -transform effect at the base. 1t is better as a oltageinput port. 1ts output resistance is relati ely low if the load resistor is not made too large. "he current gain of the '4 is io&ii 7 i'&i0 7 . 1ts input-loop transresistance used to calculate gain is r<, but the o erall amplifier transresistance is )m 7 vo&ii 7 A rin and its transconductance is the in erse of the transresistance, or Gm 7 .& )m.

Common-Base Amplifier
"he '0 amplifier input source is in the emitter loop so that emitter current flows through it. "his current is 8 . times larger than the base current. 'onsequently, the '0 input resistance is relati ely low and would ma!e a better currentinput than oltage-input port. 1ts input resistance is

or typically about )4. 1ts output resistance is the same as the '4, or )=. "he '0 oltage gain is

9nli!e the '4, it is non-in erting (no negati e sign). "he '0 current gain is , or slightly less than one. 'ompared to the '4, the '0 input resistance is lower by ( 8 .) and is therefore better as a current-input port than the '4. According to the ideal-port table, the '0 most closely approaches an ideal current amplifier, though its current gain is slightly less than oneW

Common-Collector Amplifier
"he '' or emitter-follo'er has the same input resistance as the '4 but its output resistance is

or typically about re, a relati ely small resistance of around a few ohms. (ith high input resistance and low output resistance, the '' appears to approach the ideal oltage amplifier. 9nfortunately, its oltage gain is only

or typically somewhat less than one. "he port resistances approach the ideal but the oltage gain is not high enough to be useful. "he current gain, howe er, is 8 .. +one of the three single-transistor configurations is ideal as any of the four amplifier types. Amplifiers can better approach the ideal by combining configurations into multi-transistor amplifiers.

Cascade Amplifier
Amplifiers are cascaded when the output of the first is the input to the second. "he combined gain is

where vi2 7 vo.. "he total gain is the product of the cascaded amplifier stages. "he complication in calculating the gain of cascaded stages is the non-ideal coupling between stages due to loading. "wo cascaded '4 stages are shown below.

0ecause the input resistance of the second stage forms a oltage di ider with the output resistance of the first stage, the total gain is not the product of the indi idual (separated) stages. "he total oltage gain can be calculated in either of two ways. ,irst way3 the gain of the first stage is calculated including the loading of ri2. "hen the second-stage gain is calculated from the output of the first stage. 0ecause the loading (output di ider) was accounted for in the first-stage gain, the second-stage gain input quantity is the ;2 base oltage, v02 7 vo.. Second way3 the first-stage gain is found by disconnecting the input of the second stage, thereby eliminating output loading. "hen the "he enin-equi alent output of the first stage is connected to the input of the second stage and its gain is calculated, including the input di ider formed by the first-stage output resistance and second-stage input resistance. 1n this case, the first-stage gain output quantity is the "he enin-equi alent oltage, not the actual collector oltage of the stage-connected amplifier. "he second way includes interstage loading as an input di ider in the gain of the second stage while the first way includes it as an output di ider in the gain of the first stage. 0y cascading a '4 stage followed by an emitter-follower ('') stage, a good oltage amplifier results. "he '4 input resistance is high and '' output resistance is low. "he '' contributes no increase in oltage gain but pro ides a near oltage-source (low resistance) output so that the gain is nearly independent of load resistance. "he high input resistance of the '4 stage ma!es the input oltage nearly independent of input-source resistance. <ultiple '4 stages can be cascaded and '' stages inserted between them to reduce attenuation due to inter-stage loading.

Darlington Amplifier
A '' stage followed by another '' stage has an input resistance of about ( 8 .)2 times the emitter resistance of the second stage. <ore precisely, using the transform, it is

1f )4. is remo ed, the second term is about 2 times )42. ,urthermore, if the collectors are connected together, the result is a $arlington stage, as shown below.

"his stage can be iewed as a ;$arlington transistor; because it has three terminals and an equi alent of about 2. $arlington 06"s can be used in any of the three 06" configurations.

Differential Amplifier
A differential or emitter-coupled 06" pair is formed, as shown below, by a ''&'4 stage dri ing a '0 stage. "he first stage is a '4 to the first output, vo and is a '' to the second stage.

A differential-input amplifier has an input port for which the negati e ( ) terminal is not necessarily connected to the common node (usually ground). A differential amplifier (or diff-amp) amplifies the difference between its input terminals3

Amplifiers with differential outputs ha e two output terminals, neither of which is necessarily common with an input terminal or ground. "he output is !o 7 !o8 !o "he 2-transistor diff-amp has differential inputs and outputs. "he oltage gain is found by calculating the gain from each input to each output (? gains). "he differential gain is the ratio of the difference of the outputs o er the difference of the inputs. 1f the gain magnitude (absolute alue, neglecting sign) to the output is different for the two inputs, the amplifier is not differential. "he abo e amplifier gain can be calculated using the transresistance method. "he current-source resistor )44 forms a di ider between stages. 1deally, )44 is a current source. "he diff-amp circuit is also symmetrical if corresponding components ha e equal alues3 )=. 7 )=2 7 )= )4. 7 )42 7 )4 )0. 7 )02 7 )0 and )44 SS )4 then the oltage gain is

,or non-negligible )44, a di ider is formed between stages consisting of the source-transistor )4 and )44. Apply "he eninIs theorem for a "he enin equi alent source dri ing )4 of the other stage.

Complementar* Stages
+ot only can npn 06"s or n-channel ,4"s be used in stages, so can their complementary de ices, pnp 06"s and pchannel ,4"s. Ha ing both polarities of transistors allows for more !inds of amplifiers and ma!es biasing easier. ,or e#ample, a complementary cascade amplifier is shown below. "he second ('4) stage uses a pnp 06". 1n a representation similar to the power-supply oltage sources, the input oltage source is implicit by the vi label at the input node. Also, the 8 terminal of vo is labeled by ;vo; and is understood to be ta!en with respect to ground (as the terminal).

1ts gain equation is the same as the all-npn cascade. "he ad antage of the complementary cascade amplifier is that the '0-stage collector supply (ground) must be at a lower oltage than that of the base, allowing a ground-referenced output. ,or the all-npn cascade, 8V'' adds to the output oltage de eloped across )= instead. A complementary cascode ('4 followed by '0) is shown below, with a 6,4" input stage for high input resistance. 4#cept for the ,4" (with rs instead of re) and the addition of )=., the gain and port resistance formulas are the same as the all-npn cascode. "he ;2 base-biasing di ider resistors form the equi alent )0.

<any other amplifiers of two or more transistor stages can perform better than the three one-transistor configurations. "he ones described here are among the most common and should be recogni*able as ;components; of larger circuits.

Block Diagram of Feedback Circuits

'ircuits that combine some of their output with input are feed%ac3 circuits. "he general case is shown as a bloc! diagram below, where ! quantities are oltages or currents.

0loc! diagrams do not represent circuit interconnections but instead describe the flow of electrical cause and effect. 4ach bloc! has an input (cause) and an output (effect). "he arrows point from outputs to inputs. "he output of a bloc! is the input multiplied by the transmittance written in the bloc!. ,or e#ample, !f 7 G !4. "he summing bloc!, , adds its inputs according to the sign by the arrowhead. "his bloc! diagram is a graphic way of e#pressing the following algebraic equations3

"he first two equations describe the feedbac! loop itself. "he loop is closed and consists of G, , and . "i and "o are bloc!s before and after the feedbac! loop. "hey are outside the loop but are included here because they commonly occur in feedbac! circuits. Sol ing for the o erall closed-loop gain of the feedbac! amplifier, " 7 #o&!i, it is

"he middle factor in parentheses is the gain of the closed feedbac! loop itself. Starting with a circuit diagram, if the corresponding bloc! transmittances can be found, the closed-loop feedbac! gain can be calculated from the abo e general e#pression. 'ircuits are usually not ob iously decomposable into the bloc! transmittances. (hat is needed is a general procedure that deri es the bloc!s from feedbac! circuits in equi alent circuit form so that circuit analysis can then be used to determine their transmittances. "he electrical circuit diagram equi alent of bloc!s in the bloc! diagram are two-port networ!s. 1f circuitry can be represented by two-port networ!s, the transmittances are then easy to find.

T$o-Port +et$orks
A t'o-port net'or3 has two ports. "he circuitry at each port can be represented as either a "he enin or +orton equi alent circuit, as shown below. All networ!s can be reduced to one or the other of these equi alent circuits, which themsel es are duals.

"o represent amplifiers as two-port networ!s, one port is designated as the input and the other, the output. "he outputport source has a alue " !in dependent on (or controlled by) an input-port quantity !in ( oltage or current) and " is the transmittance. "he resulting networ! is shown below.

"he controlling ariables of these dependent sources are the oltages or currents of the other port. "he beha ior of a two-port networ! is fully determined by its port quantities. "ransmittance, ", can be one of four !inds, based on the current and oltage combinations of the two ports3

Holtage gain 7 A 7 vout&vin 'urrent gain 7 Ai 7 iout&iin "ransresistance 7 )m 7 vout&iin "ransconductance 7 Gm 7 iout&vin
As an e#ample of how to deri e two-port equi alent circuits, the common-emitter amplifier (shown below) can be represented as a two-port networ!.

"he two ports of the amplifier are already identified, by the pairs of circles at input and output. 1f the output port is dri en by a oltage or current, no change occurs at the input port, and the re erse transmittance through the amplifier is *ero. 0ut from input to output port, the transmittance is the oltage gain, A . A two-port equi alent circuit is shown below.

where )in, )out, and A are as calculated in the chapter on ;Amplifier 'ircuits.; "he output port, as shown here, is a "he enin equi alent circuit.

Port 'esistances $ith Dependent Sources

"he resistance of a port, as represented by its "he enin or +orton resistance, cannot be found by shorting a dependent "he enin oltage source or by opening a dependent +orton current source. "o do so could affect the quantity the source is dependent upon and lead to erroneous results. A dependent source can only be remo ed by causing its controlling ariable to be set to *ero that is, by nulling it. "he port resistance can then be found. A dependent source can beha e as a resistance if its controlling ariable is the dual terminal (port) quantity. "his is shown by the su%stitution theorem3 across an arbitrary networ! with a port ha ing oltage v is a dependent current source of current v/r. "his current source is equi alent to a resistance of r, by BhmIs =aw. "he dual is a networ! with a port ha ing current i flowing into a dependent oltage source of alue i r. 1t too is equi alent to r. Any resistance associated with a dependent source must therefore be remo ed by nulling its controlling quantity so that the port resistance alone remains.

1f a two-port networ! contains a source dependent upon the current of the other port, then by opening the other port, the resistance of the sourceIs port can be found. Similarly, a source dependent upon the oltage of the other port can be nulled by shorting the other port. "he controlling varia%le must %e associated 'ith the other port, or the networ! is not self-contained. "he two-port nulling rules are shown abo e.

0eneral Feedback Circuit

"he feedbac! bloc! diagram is brought closer to actual feedbac! circuits as a general feedbac! circuit consisting of ported networ!s, shown below.

"his rather in ol ed diagram can represent 5ust about any feedbac! circuit of interest, and is worth some further in estigation. "he ! ariables are generali*ed port quantities (current or oltage). Delating this to the feedbac! bloc! diagram3 "i e#tends from !i into the input networ! to sum with !0, resulting in !4, the error quantity and input of G. is in the input networ!. As we will see, either currents or oltages - quantities with the same units - can be added. G starts at !4 of the upper two-port and e#tends from !Go through the output networ! to !f, the input to the feedbac! bloc!, . "he pic!off circuitry that splits into output and feedbac! paths occurs in the output networ!. "his feedbac! circuit model assumes that the re erse transmittance through is negligible. "o e#tends from !f to the circuit output quantity !o. (the lower two-port networ!) starts at !f and e#tends from !Ho through the input networ! to !0.

Input +et$ork Summing

"he summation symbol of the bloc! diagram can be reali*ed at the circuit le el in the ways currents and oltages add (or subtract). KirchhoffIs =aws sum currents (K'=) and oltages (KH=)3 'urrents sum at nodes. Holtages sum around loops. 1nput networ!s can be simplified to one of two basic topologies3 series (common loop) or shunt (common node). "he three port quantities of the input networ! combine as a sum of oltages around a loop for which loop current is common, or as a sum of currents at a node for which the node oltage is common. "he input !i is modified by "i before it appears in the loop or at the node. "he general forms of the two input networ! topologies are shown below. 1n the series topology, the common input networ! quantity is the loop current, i4. 1t is common to all three input ports and when set to *ero, or nulled by opening the loop, nulls the G-path transmittances3 !(!4) becomes nulled when i4 is nulled, thereby nulling the G source. Similarly, both of the G-path transmittances dependent on v4 in the shunt (parallel) topology are nulled by shorting the common input node.

1n choosing the common input quantity as the error quantity, both KirchhoffIs =aws and BhmIs =aw ( =) apply in the summation equation. ,or an error current around the common loop (series topology),

,or an error oltage at the common node (shunt topology),

0y choosing instead the error oltage (input to G) in the series topology or the error current in the shunt topology, summation is by KirchhoffIs =aws alone. Another approach to summing in circuits is by superposition. 1n linear systems, the contributions of sources independent of each other can be calculated and their indi idual contributions to circuit quantities added for the total quantities. "he general principle is shown below for both oltage and current summing.

(hen superposition is used for error summing, the input networ! cannot be reduced to a single loop or node. ,eedbac! analysis can still be carried through but there is no common quantity which, when nulled, nulls the input to G. Howe er, the input to G (upon which its controlled source depends) itself can be nulled.

Choosing x 1 xf and the Input +et$ork Topolog*

0efore transmittances can be found, !4 and !f must be chosen. "hese choices are largely arbitrary and are usually not unique. Howe er, some choices ma!e the resulting feedbac!-circuit analysis easier than others. ,or a difficult analysis, choose a different circuit quantity for !4 or !f, guided by the pre iously described input and output networ! considerations. 1f !f is chosen too close to the input, common factors appear in the e#pressions for is the output of GA instead of G0, as shown below. "his results in feedbac! equations3 and "o. =et G 7 GA G0, where !f

G0 is common to both the term of !4 and "o in !o. 0y letting !f be the output of G0 instead, G0 appears as a factor in the first equation and disappears from the others. 1f !f is instead chosen too close to the output, so that "o 7 "oA "o0 and !f is the output of "oA, then3

1n this case, introducing factor "oA into the third equation remo es it from the first two. 1f !4 is chosen too close to the output, common factors occur in the two terms of !4. =et !4 be input to G0. "hen

0y letting G 7 GA G0, GA becomes a factor in the first equation and is eliminated from the second. "he final case is that of choosing !4 too close to the input, as the input of "i0. "hen "i0 appears as a common factor with G and in the error term containing .

0y mo ing !4 to the output of "i0, "i0 is eliminated from the first equation and first !4 term so that "i 7 "iA "i0.

term of !4 and becomes a factor in the

"he form of input-networ! topology (series or shunt) is not determined by the circuit. "he choice of !4 affects the choice of input topology. "his can be seen from the following input networ!.

1f v. is chosen as v4, the -path port is made a "he enin circuit and the input forms a loop a series topology. 1f v2 is chosen for v4 instead, then con erting the input and feedbac! ports to +orton equi alent circuits results in a common node with oltage v4 a shunt topology.

T$o-Port %ui&alent Circuits

"he transmittances of the general feedbac! bloc! diagram are found by first finding the equi alent circuits of upper and lower two-port networ!s shown in the general feedbac! circuit. %ort resistances are found first by applying two-port nulling to dependent sources. %ort resistances enter the calculation of transmittances by forming di iders in the input and output networ!s or by changing the gain of amplifier circuits. Bther sources that contribute to the output port of the transmittance being found but which are not part of its path must be nulled. After nulling,, transmittance is found by applying amplifier or di ider analyses that include port resistances. "o find the two-port equi alent circuits, null the controlling ariable of each port and find the port resistance. "o find )Go, null !4 to null the G output source. "o null !4, short the node of v4 or open the loop of i4. "hen inspect the G output port (at !Go) for its resistance, )Go, using circuit analysis. "o find )Ho, null !f. ,or vf, short its node; for if, open its loop. "his nulls the !(!f) source of the input-networ! feedbac! port, allowing its resistance, )Ho, alone to appear across the output port.

+e#t, the transmittances are found. "o find "i, null !f. "his both nulls the feedbac! contribution to !4 (which is !0) and presents the feedbac! port resistance, )Ho, to the input networ! for calculation of "i. ,ind the transmittance from !i to !4 by circuit analysis. "o find G, the effect of loading by the output networ! and )Hi are included in calculating the G transmittance. "o find , null the independent source !i by shorting, if vi, and opening, if ii. Apply circuit analysis from !f forward through the path to !0 or to !4. "hen

,inally, find "o 7 !o&!f.

Feedback Anal*sis Procedure

A general procedure can now be gi en for sol ing feedbac! circuits. 0efore the actual procedure is applied, simplify the circuit, if possible, using "he enin and +orton equi alent circuits, and feedbac!-analy*e the simpler circuit. .. Choose xf" !f is dependent on !4. ,or vf, identify a node; for if, identify a loop. 2. Choose xE and identify the in'ut network to'ology" !4 is dependent on !i and !0(!f). %ort oltages sum around a loop; port currents sum at a node. ,or series (loop) topology, i4 is the common input-networ! quantity to both error and feedbac! ports; for shunt (node) topology, v4 is the common quantity. 4ither v4 or i4 can be chosen for !4. ,or error-summing by superposition, no common input-networ! nulling quantity e#ists; multiple loops or nodes e#ist. A. Find Ti" "i is found by nulling !0 by nulling !f. 2nput-networ! feedbac!-port resistance, )Ho, is found by nulling !f and determining )Ho. 1f !f 7 vf, short the vf node; if if, open the if loop. "hen "i 7 !4&!i with !f 7 ). ?. Find transmittances of G" G 7 !f&!4 while nulling !(!Ho). <utput networ! port resistance, )Go is found by nulling the input-networ! common error quantity (i4 for loop; v4 for node). E. Find H" +ull input source !i. 1f !i 7 vi, short it; if ii, open it. "hen /. Find To" "o 7 !o&!f. 7 !0&!f 7 (!4&!f) with !i 7 ).

+on-In&erting !p-Amp
+ow that the general procedure for analysis of feedbac! amplifier circuits has been de eloped, it will be applied to specific amplifiers. "he first e#ample of its use is the non-inverting op-amp configuration, shown below.

"he triangular amplifier symbol with 8 and inputs (differential input) and single-ended (ground-referenced) output is the symbol of an operational amplifier, or op-amp. 1t has infinite input resistance, an ideal oltage-source output (*ero output resistance) and infinite oltage gain. 1n practice, actual op-amps approach these conditions sufficiently so that use of the ideal op-amp model is often 5ustified. 1f the model is made slightly more realistic by assuming a finite oltage gain of K,

where v8 is the oltage at the op-amp 8 (nonin erting) input. "hen the oltage amplifier can be analy*ed using the feedbac! analysis procedure. .. 'hoose !f 7 vo. "his choice is the only path bac! to the input from the amplifier output, through )f. "he amplifier output quantity is the same as the feedbac! quantity. "he feedbac! node is the op-amp output. 2. 'hoose !4 7 v4 7 v8 v , and note that the input circuit is a loop with vi, v4, and v0 in series. 0ecause the op-amp input resistance (across v4) is infinite, i4 is *ero. A. "i 7 .; vi adds directly to v4 as v8 in the error loop. "his can be found by nulling vf 7 vo by shorting the op-amp output. (ith vf 7 vo shorted, no input attenuation3 "i 7 .. to ground. "his results in vi 7 v8 and v= at ) H, lea ing v4 7 v8 with

?. G 7 vo&v4 7 K. "o e#amine output loading on G, open the error-summing loop at the v node. "his nulls i4 (which is *ero anyway). "hen v4 7 ), and the output resistance loading the op-amp is )f 8 )i. 0ecause the opamp output is an ideal oltage source, its *ero output resistance allows no loading effect, no attenuation between the op-amp "he enin equi alent output, v(v4), and the amplifier output, vo. 1n other words, v(v4) 7 vo. E. (ith vi shorted, 7 (v4&vf). "his is negati e the attenuation of the oltage di ider from vf 7 vo to v8 or

/. 0ecause !o 7 vo 7 !f 7 vf, "o 7 .. +ow that all of the quantities of the feedbac! formula are !nown, the feedbac!-amplifier oltage gain (or closed-loop gain) can be found by substitution3

<ultiplying numerator and denominator of the gain e#pression by .&K, then for large K (as K approaches infinity), .&K approaches ) and for the ideal non-in erting op-amp, the oltage gain formula is3

,or e#ample, if )f 7 .) ! and )i 7 ..) !, then the op-amp oltage gain is ...

In&erting !p-Amp
"he other basic op-amp configuration, the in erting configuration, is shown below.

"o analy*e this amplifier, apply the feedbac! analysis procedure3 .. 'hoose !f 7 vo. As with the nonin erting op-amp, the only path bac! to the input is )f which connects to vo. 2. 'hoose !4 7 i4, the current flowing into the node of the in erting op-amp terminal. 4rror current is summed at this node; it is dependent upon input current through )i and feedbac! current through )f. 0oth sources are +orton equi alents, in parallel across v (shunt topology). "he common input-networ! node quantity is v .

Shorting v nulls the forward path through G. A. +ull !f 7 vo by shorting the output (to ground); )Ho 7 )f. "hen "i 7 i4&vi. +o current flows into either input of the op-amp. "herefore, i4 7 ii and i4&ii 7 .. 0ut from the +orton equi alent of the input current source, ii 7 vi& )i, and "i 7 .&)i.

"he error quantity, i4, is the sum of the currents from the two current sources at the top node. ,or the G path, v is the op-amp input quantity, not i4. G consists of two cascaded transmittances, (v &i4) times (vo&v ). "he first transmittance is the resistance of the op-amp in erting-input node. 1nclude the G input loading of )Ho by shorting vo. "his has the effect of grounding the output side of )f, and )Ho 7 )f. 1n the equi alent circuit abo e, it is the same as opening the output current source. "hen )Ho 7 )f, and the resistance across v- is . "he error current times this node resistance is v- .

"he second transmittance is K, the oltage gain of the op-amp. ?. "he feedbac!, !(!f) 7 i0(vo) 7 vo&)f. "his is the current source of the +orton equi alent feedbac! circuit (output of ) and it is nulled by setting !f 7 vo to *ero. (ith this nulling,

E. "o find , null ii. "his is the +orton input circuit, where ii 7 vi&)i. "o null it, open the current source. "hen (vo&)f)&vo 7 .&)f. /. ,inally, "o 7 . because vf 7 vo. 7 (i4&vo). 0ut i4 is only the current from the +orton feedbac! source, which is vo&)f. Substituting, 7-

+ow that the transmittances ha e been found, the closed-loop oltage gain is

(hen K becomes large, this reduces to

An alternati e analysis demonstrates a different choice of !4 that uses superposition to sum error quantities. .. 'hoose !f 7 vo. As with the nonin erting op-amp, the only path bac! to the input is )f which connects to vo. 2. 'hoose !4 7 v4 7 v and obser e that !0 must be a oltage that sums in a circuit with vi. (!0 is the feedbac! with resistances )i and )f, respecti ely. 0ecause the input port to G is across the op-amp input terminals, this port is in parallel with the input and feedbac! sources and no single series loop e#ists. 'onsequently, !4 7 v4 7 v must be obtained by superposition. "o null the G transmittance, v4 is shorted. A. "i 7 v4&vi with feedbac! nulled by shorting vo. "he feedbac! port resistance )Ho is found to be )f. "hen "i is a quantity that sums directly with "i !i.) "he input and feedbac! sources are oltage sources vi and vo in series

oltage di ider3

?. "o find G output loading, )Go and )Hi are *ero because of the ideal op-amp output. (hen v4 is nulled, the

output node is )f in parallel with the op-amp output resistance, which is *ero ohms. "hen G 7 vo&v4 7 vo&v 7 -K. E. +ull vi by shorting it. "hen the path from vo to v4 is a di ider the same one as for "i but in the re erse direction, or

v0 is the "he enin equi alent oltage at v due to vo. 0ecause of summing con ention, it subtracts from v4, and the sign appears in . /. "o 7 . because vGo 7 vo. Substituting the abo e transmittances into the feedbac! formula produces the same result as the pre ious analysis. Another choice of !4, the oltage across )i, is also wor!able, but much more difficult. 1n this case, the error quantity is chosen too close to the input and a redundant factor, )f&)i, appears in both G and . (1t cancels, resulting in the same closed-loop gain as already deri ed.) An e#ample of an in erting op-amp3 )f 7 .) ! and )i 7 ..) !. "hen the op-amp oltage gain is .). "he difference between the in erting and nonin erting op-amp configurations is where ground is connected. (ithout rewiring, if the in erting input oltage-source 8 terminal is grounded instead of its terminal, the non-in erting configuration results. "he non-in erting configuration has a gain of one more because the input source is added to the op-amp output.

T$o-Port #oading Theorem

'alculation of two-port equi alent circuits is simplified when two independent ports are connected ia a common resistance, as shown below for the oltage case. "he lower two-port equi alent circuit is deri ed from the upper circuit by applying superposition at nodes ha ing vA and v03

"hese equations are equi alent to

where vA and v0 are calculated assuming the other is gi en. 1n general, if vA were found, including the loading by port ( on the vA node, then v0 can be found assuming vA. (hat the abo e deri ation shows is that both vA and v0 can be found assuming the other already has been. "he current dual circuit is shown below. %ort currents iA and i0 are found assuming that the other is already determined. "he corresponding equations are3

"his loading theorem is applicable, for instance, to the lower two-port networ! of a feedbac! circuit when !f and !4 are connected by a resistance.

B/T Feedback Amplifier

"he discrete-component 06" amplifier shown below resembles the in erting op-amp and demonstrates use of the twoport loading theorem.

Assuming that the transistors are biased for linear operation (so that the 06" model is alid), the feedbac! analysis procedure is as follows. .. 'hoose !f 7 vo. "his is the output node. 2. 'hoose !4 7 i4 7 i0., the current into the base of ;.. 'omponents connect to this node from both the input and output nodes, in parallel. "he shunt input-networ! topology is consequently the most easy to identify. "he

equi alent input networ! is shown below.

"he +orton equi alent input and feedbac! circuits are in parallel with the input of G. and v0. is the common input-port error quantity. A. 0ecause of rin3 "i
a current-di ider is formed by )0 in parallel with )f and rin. After nulling vo (by shorting it), )Ho 7 )f and

"his is the fraction of input current, vi&)0, that flows through rin, which is i0..

?.

G 7 vo&i4 7 vo&i0.. (hile nulling the input-port common error quantity (the node oltage, v0.), at the G output node, )Hi (7 )f) is in parallel with )42, as G output loading. "he gain of the first stage, neglecting the loading of ;2, is v'.&i0. 7 1 )=. "he total gain is the product of first and second-stage gains, or

0oth input and output loading of the G path is ta!en into account in G.

E.

"he feedbac! bloc!, , is found by nulling the input quantity, and calculating

"he fraction of current due to vo that is i0. is found by the current di ider formula and multiplying by output the equi alent current3

/.

"o 7 ., because the feedbac! quantity, !f 0 vo.

"he abo e quantities are substituted into the feedbac! equation to calculate the closed-loop gain. "he choice of i0. for the error quantity was not the only possibility. "his amplifier could ha e been analy*ed by assuming the base oltage of ;. to be the error quantity. ,or step ?, the loading theorem is applied to allow us to assume that vo and v0. are the actual (loaded) node oltages with )f the connecting resistance. "hen the effects of the input and output networ!s (due to loading) can be ta!en into account. 1nput summing would then be applied by superposition of vi and vo to the calculation of v0., from the equi alent circuit, shown below.

+ote that this circuit is similar to the in erting op-amp, with the addition of rin and the input and output loading of G. "he G path is an in erting amplifier, but has non-ideal input resistance.

Closure
<any other e#amples of feedbac! circuits could be gi en. (ith the networ! and feedbac! analysis principles gi en here, most of them can be analy*ed with sufficiently accurate results. ,eedbac! principles apply to more than electronic circuits. 4lectronic circuits are but one application area of feedbac! theory, which is an important part of the field of control theory.