Manual Osciloscópio TMS320VC5416 PDF

TMS320VC5416 DSK Technical Reference
2002
DSP Development Systems
TMS320VC5416 DSK Technical Reference
506005-0001 Rev. A March 2002
SPECTRUM DIGITAL, INC. 12502 Exchange Drive, Suite 440 Stafford, TX. 77477 Tel: 281.494.4505 Fax: 281.494.5310 sales@spectrumdigital.com www.spectrumdigital.com
IMPORTANT NOTICE Spectrum Digital, Inc. reserves the right to make changes to its products or to discontinue any product or service without notice. Customers are advised to obtain the latest version of relevant information to verify that the data being relied on is current before placing orders. Spectrum Digital, Inc. warrants performance of its products and related software to current specifications in accordance with Spectrum Digitals standard warranty. Testing and other quality control techniques are utilized to the extent deemed necessary to support this warranty. Please be aware that the products described herein are not intended for use in life-support appliances, devices, or systems. Spectrum Digital does not warrant nor is Spectrum Digital liable for the product described herein to be used in other than a development environment. Spectrum Digital, Inc. assumes no liability for applications assistance, customer product design, software performance, or infringement of patents or services described herein. Nor does Spectrum Digital warrant or represent any license, either express or implied, is granted under any patent right, copyright, or other intellectual property right of Spectrum Digital, Inc. covering or relating to any combination, machine, or process in which such Digital Signal Processing development products or services might be or are used. WARNING This equipment is intended for use in a laboratory test environment only. It generates, uses, and can radiate radio frequency energy and has not been tested for compliance with the limits of computing devices pursuant to subpart J of part 15 of FCC rules, which are designed to provide reasonable protection against radio frequency interference. Operation of this equipment in other environments may cause interference with radio communications, in which case the user at his own expense will be required to take whatever measures necessary to correct this interference.
Copyright 2002 Spectrum Digital, Inc.
Contents
Introduction to the TMS320VC5416 DSK Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Provides you with a description of the TMS320VC5416 DSK Module, key features, and board outline. 1.0 Overview of the TMS320VC5416 DSK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.1 Key Features of the TMS320VC5416 DSK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.2 Functional Overview of the TMS320VC5416 DSK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Operation of the TMS320VC5416 DSK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Describes the operation of the TMS320VC5416 DSK. Information is provided on the DSKs various interfaces. 2.0 The TMS320VC5416 DSK Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.1 The TMS320VC5416 DSK Board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.1.1 Power Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.2 TMS320VC5416 Memory Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.2.1 Program Memory Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.2.2 Data Memory ........................................................ 2.2.3 I/O Space .......................................................... 2.2.4 Interface CPLD ...................................................... 2.2.4.1 CPLD Control Registers and Status Registers ........................... 2.4.4.1.1 DSP USER_REG Register (I/O Address 0x0000) ...................... 2.2.4.1.2 DSP Daughter Card Register (I/O Address 0x0001) . . . . . . . . . . . . . . . . . . . . . 2.2.4.1.3 DSP CODEC_L_CMD (I/O Address 0x0002) and ...................... CODEC_H_CMD Register (I/O Address 0x0003) 2.2.4.1.4 Version Register (I/O Address: 0x0004) .............................. 2.2.4.1.5 DSP DM_CNTL Register (I/O Address 0x0005) ....................... 2.2.4.1.6 MISC Register (I/O Address 0x0006) ................................ 2.2.4.1.7 CODEC_CLK Register (I/O Address: 0x0007) ......................... 2.2.5 Flash ROM ......................................................... 2.2.6 SRAM Interface .................................................... 2.2.7 Codec Interface .................................................... 2.2.7.1 Programming the Codec Interface .................................... 2.2.7.2 Programming the Data Interface ..................................... 2.2.7.3 PCM3002 Codec Input/Output Circuitry ............................... 2.2.8 Daughter Card Interface ............................................. 2.2.8.1 Program Space Accesses .......................................... 2.2.8.2 Data Space Accesses ............................................. 2.2.8.2.1 Data Space 32 Bit Accesses ...................................... 2.2.8.3 I/O Space Accesses ............................................... 2.2.8.3.1 I/O Space 32 Bit Accesses ........................................
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B C D
2.2.9 Wait States ....................................................... 2.2.9.1 Software Wait State Generator ...................................... 2.3 TMS320VC5416 DSK Jumpers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.3.1 JP4, DSP Configuration .............................................. 2.4 TMS320VC5416 DSK Connectors ....................................... 2.4.1 Expansion Connectors ............................................... 2.4.2 P1, Memory Expansion Connector ...................................... 2.4.3 P2, Peripheral Expansion Connector .................................... 2.4.4 P3, HPI Expansion Connector ......................................... 2.4.5 J1, Microphone Connector ............................................ 2.4.6 J2, Audio Line In Connector ........................................... 2.4.7 J3, Audio Line Out Connector .......................................... 2.4.8 J4, Headphones/Speaker ............................................. 2.4.9 J5, Optional Power Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.4.10 J6, +5 Volt Connector ............................................... 2.4.11 J7, External JTAG Connector ......................................... 2.4.12 JP1, PLD Programming Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.5 User LEDS .......................................................... 2.5.1 System LEDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.6 Switches ............................................................. 2.6.1 Reset Switch/Reset Logic ............................................ 2.6.2 4 Position User DIP Switch ............................................ 2.7 J201, Universal Serial Bus (USB) Embedded JTAG Emulation Connector ....... TMS320VC5416 DSK CPLD Equations ...................................... . Lists the VHDL for CPLD U18, used on the TMS320VC5416 DSK A.1 CPLD Equations for VC5416 DSK ......................................... TMS320VC5416 DSK Schematics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Contains the schematics for the TMS320VC5416 DSK TMS320VC5416 DSK List of Materials ........................................ Contains the list of materials used to build the TMS320VC5416 DSK TMS320VC5416 DSK Mechanical Information ................................ Contains the mechanical information about the TMS320VC5416 DSK
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About This Manual This document describes the board level operations of the TMS320VC5416 DSP Starter Kit (DSK) module. The DSK is based on the Texas Instruments TMS320VC5416 Digital Signal Processor. The TMS320VC5416 DSK is a table top card to allow engineers and software developers to evaluate certain characteristics of the TMS320VC5416 DSP to determine if the processor meets the designers application requirements. Evaluators can create software to execute onboard or expand the system in a variety of ways. Notational Conventions
This document uses the following conventions. The TMS320VC5416 will sometimes be referred to as the C54XX. The TMS320VC5416 DSK will sometimes be referred to as the DSK. Program listings, program examples, and interactive displays are shown is a special italic typeface. Here is a sample program listing. equations !rd = !strobe&rw;
Information About Cautions This book may contain cautions. This is an example of a caution statement. A caution statement describes a situation that could potentially damage your software, or hardware, or other equipment. The information in a caution is provided for your protection. Please read each caution carefully. Related Documents Texas Instruments TMS320VC54XX Users Guide Texas Instruments TMS320VC54XX Fixed Point Assembly Language Users Guide Texas Instruments TMS320VC54XX Fixed Point C Language Users Guide Texas Instruments TMS320VC54XX Code Composer Studio Users Guide
Table 1: Hardware History Revision B C Beta Release Production Release History
Table 2: Manual History Revision A Beta Release History
Chapter 1 Introduction to the TMS320VC5416 DSK
Chapter One provides a description of the TMS320VC5416 DSK along with the key features and a block diagram of the circuit board.
Topic
1.0 1.1 1.2 Overview of the TMS320VC5416 DSK Key Features of the TMS320VC5416 DSK Functional Overview of the TMS320VC5416 DSK
Page
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Spectrum Digital, Inc

1.0 Overview of the TMS320VC5416 DSK The TMS320VC5416 DSK is a stand-alone development and evaluation module. It allows evaluators to examine certain characteristics of the C5416 digital signal processor (DSP) to determine if it meets their application requirements. Furthermore, the module is an excellent platform to develop and run software for the TMS320VC5416 family of processors. The DSK allows full speed verification of VC5416 code. With 64K words of on board RAM memory, 256K words of on board Flash ROM, and a Burr Brown PCM 3002 stereo codec, the board can solve a variety of problems as shipped. Three expansion connectors are provided for interfacing to evaluation circuitry not provided on the as shipped configuration. To simplify code development and shorten debugging time, a special version of Code Composer Studio is shipped with the board. 1.1 Key Features of the TMS320VC5416 DSK The VC5416 DSK has the following features: VC5416 operating at 16-160 MHz. On board USB JTAG controller with plug and play drivers 64K words of on board RAM 256K words of on board Flash ROM 3 Expansion Connectors (Memory Interface, Peripheral Interface, and Host Port Interface) On board IEEE 1149.1 JTAG Connection for Optional Emulation Debug Burr Brown PCM 3002 Stereo Codec +5 volt operation
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TMS320VC5416 DSK Module Technical Reference

1.2 Functional Overview of the TMS320VC5416 DSK Figure 1-1 shows a block diagram of the basic configuration for the VC5416 DSK. The major interfaces of the DSK include the target RAM and ROM interface, FPGA interface, Codec interface, and expansion interface. The VC5416 interfaces to 64K words of on board RAM and 256K words of Flash ROM. An external I/O interface supports parallel I/O ports and multi channel buffered synchronous serial ports. A Flash Boot ROM is mapped into data memory space. Four stereo jacks provide input and outputs to and from the codec.
A D D R E S S / D A T A / C O N T R O L E X P A N S I O N
Embedded USB JTAG Controller
JTAG DATA SRAM 64K x 16 ADDRESS
TMS320VC5416
DECODE FPGA CONTROL
McBSP Flash ROM 256K x 16 McBSP User Switch
McBSP HPI -IO
E X P A N S I O N
STEREO CODEC User LEDs DATA
HPI EXPANSION
Figure 1-1, BLOCK DIAGRAM, TMS320VC5416 DSK
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Chapter 2 Operation of the TMS320VC5416 DSK
This chapter describes the operation of the TMS320VC5416 DSK, the key interfaces and an outline of the circuit board.
Topic
2.0 The TMS320VC5416 DSK Operation 2.1 The TMS320VC5416 DSK Board 2.1.1 Power Connector 2.2 TMS320C5416 DSK Memory Interface 2.2.1 Program Memory Interface 2.2.2 Data Memory 2.2.3 I/O Space 2.2.4 Interface CPLD 2.2.4.1 CPLD Control Registers and Status Registers 2.2.4.1.1 DSP USER_REG Register (I/O Address 0x0000) 2.2.4.1.2 DSP Daughter Card Register (I/O Address 0x0001) 2.2.4.1.3 DSP CODEC_L_CMD (I/O Address 0x0002) and CODEC_H_CMD Register (I/O Address 0x0003) 2.2.4.1.4 Version Register (I/O Address: 0x0004) 2.2.4.1.5 DSP DM_CNTL Register (I/O Address 0x0005) 2.2.4.1.6 MISC Register (I/O Address 0x0006) 2.2.4.1.7 CODEC_CLK Register (I/O Address: 0x0007) 2.2.5 Flash ROM Interface 2.2.6 SRAM Interface 2.2.7 Codec Interface 2.2.7.1 Programming the Codec Interface 2.2.7.2 Programming the Data Interface 2.2.7.3 PCM3002 Codec Input/Output Circuitry
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Topic
2.2.8 Daughter Card Interface 2.2.8.1 Program Space Accesses 2.2.8.2 Data Space Accesses 2.2.8.2.1 Data Space 32 Bit Accesses 2.2.8.3 I/O Space Accesses 2.2.8.3.1 I/O Space 32 Bit Accesses 2.2.9 Wait States 2.2.9.1 Software Wait State Generator 2.3 TMS320VC5416 DSK Jumpers 2.3.1 JP4, DSP Clock and Mode Configuration 2.4 TMS320VC5416 DSK Connectors 2.4.1 Expansion Connectors 2.4.2 P1, Memory Expansion Connector 2.4.3 P2, Peripheral Expansion Connector 2.4.4 P3, HPI Expansion Connector 2.4.5 J1, Microphone Connector 2.4.6 J2, Audio Line In Connector 2.4.7 J3, Audio Line Out Connector 2.4.8 J4, Headphone/Speaker Connector 2.4.9 J5, Optional Power Connector 2.4.10 J6, +5 Volt Connector 2.4.11 J7, External JTAG Connector 2.4.12 JP1, PLD Programming Connector 2.5 User LEDs 2.5.1 System LEDs 2.6 Switches 2.6.1 Reset Switch/Reset Logic 2.6.2 4 Position User DIP Switch 2.7 J201, Universal Serial Bus (USB) Embedded JTAG Emulation Connector
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2.0 The TMS320VC5416 DSK Operation This chapter describes the VC5416 DSK module, key components, and how they operate. It also provides information on the DSKs various interfaces.The VC5416 DSK consists of five major blocks of logic. C5416 External memory Codec Interface CPLD Registers and Interface Expansion interface JTAG Interface
2.1 The TMS320VC5416 DSK Board The VC5416 DSK is a 8.25 x 4.5 inch (210 x 115 mm.) multi-layer board which is powered by an external +5 volt only power supply. Figure 2-1 shows the layout of the VC5416 DSK.
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J1 J2 J3 J4 P1 P3
J201
J6
J5
J7
P2
S1
JP1
D9-12
TP6-9
S2
JP4
Figure 2-1, TMS320VC5416 DSK 2.1.1 Power Connector The VC5416 DSK is powered by a +5 volt only, 3 amp power supply which is available with the module. The typical board current requirements, without expansions boards, is 0.5 - 0.75 amps. The power is supplied via 2.5 millimeter jack JP6. If expansion boards are connected to the module a higher amperage power supply may be necessary. The board also has a +3.3 and +1.6 volt regulator to provide power to the lower voltage components.
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2.2 TMS320C5416 DSK Memory Interface The DSK includes 64K words of SRAM. The board also features 256K words flash ROM for boot loading. It is important to remember that internal memory has a higher precedence than the external memory. For more information on the memory in the device populated in your DSK card please refer to Texas Instruments TMS320C54XX Users Guide or TMS320VC5416 data sheet. Futhermore, it is important to take into account that external memory is affected by wait-states. Wait state generation for off-chip memory space (data, program, or I/O) is done with the Software Wait State Generation Register(SWWSR). To obtain wait states for off-chip memory, bits in the SWWSR must be appropriately programmed. The board powers up with maximum wait-states. The DSK board does not generate wait states via the ready signal for external program memory, data memory, or I/O accesses. External memory decode is done via CPLD U8. The complex program logic device selects the RAM, FLASH ROM, or on board peripherals. The VHDL for the CPLD are included in Appendix A. The internal PMST register (Processor Mode Status Register) greatly affects the memory decode for the VC5416 and VC5416 DSK. The user should be familiar with this register to help in the understanding of the DSKs operation. The figure below shows the bit fields of the PMST register and a brief description of the registers function bits.
15 IPTR 7 6 5 4 AVIS R/W-0 3 2 1 0 SST R/W-0
MP/MC OVLY MP/MC Pin R/W-0
DROM CLKOFF SMUL R/W-0 R/W-0 R/W-0
Figure 2-2, Processor Mode Status Register (PMST) The bit fields in PMST are described in the table below. Table 1: PMST Bit Field Definition Bit # Bit Name Reset Value Function Interrupt vector pointer - The 9-bit IPTR field points to the 128-word program page where the interrupt vectors reside. The interrupt vectors can be remapped to RAM for boot-loaded operations. At reset, these bits are all set to 1; the reset vector always resides at address FF80h in the program memory space. The RESET instruction does not affect this field.
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IPTR
1FFh
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Table 1: PMST Bit Field Definition Bit # Bit Name Reset Value Function
Microprocessor/microcontroller Mode - MP/MC enables/ disables the on-chip ROM to be addressable in program memory space. - MP/MC = 0: The on-chip ROM is enables and addressable. - MP/MC = 1: The on-chip ROM is not addressable. MP/MC is set to the value corresponding to the logic level on the MP/MC pin when samples at reset. This pin is not samples again until the next reset. The RESET instruction does not affect this bit. This can also be set or cleared by software. RAM overlay. OVLY enables the on-chip dual address dual-access data RAM blocks to be mapped into program space. The values for the OVLY bit are: 5 OVLY 0 - OVLY = 0: The on-chip RAM is addressable in data space but not in program space. - OVLY = 1: The on-chip RAM is mapped into program space and data space. Data page 0 (address 0h to 7Fh)., however it not mapped into program space. Address visibility mode. AVIS enables/disables the internal program address to be visible at the address pins. - AVIS = 0: The external address lines do not change with the internal program address. control and data lines are not affected and the address bus is driven with the last address on the bus. - AVIS = 1: This mode allows the internal program address to appear at the pins of the 5416 so that the internal program address can be traced. Also, it allows the interrupt vector to be decoded in conjunction with IACK when the interrupt vectors reside in-chip memory.
MP/MC
MP/MC Pin
AVIS
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Table 1: PMST Bit Field Definition Bit # Bit Name Reset Value Function DROM - Enables on-chip DARAM4-7 to be mapped into data space. The DROM values are: 3 DROM 0 - DROM = 0: The on-chip DARAM4-7 is not mapped into data space - DROM = 1: The on-chip DARAM4-7 is mapped into data space 2 CLKOFF 0 CLKOUT off. When the CLKOFF bit is a 1, the output of the CLKOUT is disabled and remains at a high level Saturation on multiplication. When SMUL = 1, saturation of a multiplication result occurs before performing the multiplication in a MAC or MAS instruction. The SMUL bit applies only when the OVM=1 and FRCT=1. Saturation on store. When SST = 1, saturation of the data from the accumulator is enabled before storing in memory. The saturation is performed after the shift operation
SMUL
N/A
SST
N/A
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2.2.1 Program Memory Interface There are two configurations for program memory. The selection of these configurations is done by the 54Xs OVLY bit. When in OVLY mode, addresses 0x0000 - 0x8000 are internal for every page. This is the preferred mode to be used by the DSK. When in linear mode program memory is mapped externally. Manual sections 2.2.5 and 2.2.6 show how on-board memory is mapped into the external spaces of the processor. The following figure shows the program memory map for TMS320VC5416.
Page 0 Program Reserved (OVLY=1) External (OVLY=0) 0x007F 0x0080 On-Chip DARAM0-3 (OVLY=1) External (OVLY=0) 0x7FFF 0x0000 0x8000 External 0xFF7F 0xFF80 Interrupts (On-Chip) 0xFFFF MP/MC=1 (Microprocessor Mode) Hex 010000 Program On-Chip DARAM0-3 (OVLY=1 External (OVLY=0) Hex 020000 Program On-Chip DARAM0-3 (OVLY=1 External (OVLY=0) Hex 030000 Program On-Chip DARAM0-3 (OVLY=1 External (OVLY=0)
Hex
Page 0 Program Reserved (OVLY=1) External (OVLY=0) 0x007F 0x0080 On-Chip DARAM0-3 (OVLY=1) External (OVLY=0) 0x7FFF Hex 0x0000 0x8000 External 0xBFFF 0xC000 0xFEFF 0xFF00 0xFF7F 0xFF80 0xFFFF On-Chip ROM (4K x 16 bit) Reserved Interrupts (On-Chip)
MP/MC=0 (Microcomputer Mode) Hex 040000 Program On-Chip DARAM0-3 (OVLY=1 External (OVLY=0) Hex 7F0000 Program
On-Chip (DARAM4-7 (MP/MC=0) External 01FFFF (MP/MC=1) Page 1 XPC=1
017FFF 018000
On-Chip (SARAM0-3 (MP/MC=0) External 02FFFF (MP/MC=1) Page 2 XPC=2
027FFF 028000
On-Chip (SARAM4-7 (MP/MC=0) External 03FFFF (MP/MC=1) Page 3 XPC=3
037FFF 038000
047FFF 048000
On-Chip DARAM0-3 (OVLY=1 External 7FFFFF (OVLY=0) 7F8000 External 7FFFFF
External 04FFFF Page 4 XPC=4
Page 127 XPC=7Fh
Figure 2-3, TMS320VC5416 DSK Program Space
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2.2.2 Data Memory The external data memory is mapped from 0x8000 to 0xFFFF for the DSK. This allows a reach of 32K words. The on board CPLD further supplies 5 additional address lines to allow for thirty-two (32), 32K word pages to be accessed in data space. All on board accesses are mapped into the processors data memory space from 0x8000 to 0xFFFF and use the extended address lines from the CPLD. Refer to the section on Data Space Access for how the DSP and CPLD pages address interact. The figure below shows the data space memory map for the TMS320VC5416 processor.
Hex 0x0000 0x005F 0x0060 0x007F 0x0080 On-Chip DARAM0-3 (32K x 16 bit) 0x7FFF 0x8000 On-Chip DARAM4-7 (DROM=1) or External (DROM=0) Scratch-Pad RAM Data Memory-Mapped Registers
0xFFFF Address ranges for on-chip DARAM in data memory are: DARAM0: 0x0080-0x1FFF DARAM1: 0x2000-0x3FFF DARAM2: 0x4000-0x5FFF DARAM3: 0x6000-0x7FFF DARAM4: 0x8000-0x9FFF DARAM5: 0xA000-0xBFFF DARAM6: 0xC000-0xDFFF DARAM7: 0xE000-0xFFFF
Figure 2-4, TMS320VC5416 DSK Data Space
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2.2.3 I/O Space The TMS320VC5416 processor has no on-chip I/O accesses. The DSK uses this space to access the on board CPLD and expansion connectors for daughter card accesses. The I/O map for the TMS320VC5416 DSK is shown below. The CPLD has eight (8) 8 bit registers which control various functions as explained in the Interface CPLD section of this manual.
Hex 0x0000 0x0007 0x0008 Reserved 0x7FFF 0x8000 0xFFFF Daughter Card Access CPLD Configuration Registers
Figure 2-5, TMS320C5416 I/O Space
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2.2.4 Interface CPLD The VC5416 uses a CPLD to interface to the Flash ROM, SRAM, Codec control, and the Daughter Card Interface. The CPLD is mapped into the I/O address space and contains eight (8) 8-bit registers as shown below. 2.2.4.1 CPLD Control Registers and Status Registers There are eight DSP CPLD registers mapped into the DSP's lower I/O address space starting at address 0x0000 to 0x0007. Since the CPLD decoder only uses part of the DSPs Address for decoding, the registers will be mirrored within the I/O space addresses in 64 word increments within the lower 16K of the I/O address space. It is recommended that the CPLD registers only be accessed at locations 0x0000 to 0x0007 so future implementations will not case software changes. The table below shows the bit definitions for the 8 registers in CPLD. Table 2: CPLD Register Definitions
I/O Addr 0 1 Name USER_REG DC_REG Bit 7 USR_SW3 R DC_DET R Bit 6 USR_SW2 R DC_IO_CTL R/W 0 Bit 5 USR_SW1 R DC_STAT1 R Bit 4 USR_SW0 R DC_STAT0 R Bit 3 USR_LED3 R/W DC_RST R 0(on reset) Bit 2 USR_LED2 R/W 0 Bit 1 USR_LED1 R/W DC_CNTL1 R/W 0(low) Bit 0 USR_LED0 R/W DC_CNTL0 R/W 0(low)
CODEC_L
CODEC_L_CMD[7..0] R/W 0 CODEC_H_CMD[15..8] R/W 0 CPLD_VER[3.0] R DM_SEL R/W 0(int) CODEC_RDY R 0(Ready) 0 MEMTYPE_DS R/W 0(flash) 0 MEMTYPE_PS R/W 0(flash) 0 DM_PG4 R/W 0(page 0) 0 0 DM_PG3 R/W 0(page 0) 0 BOARD VERSION[2.0] R DM_PG2 R/W 0(page 0) DC_WIDE R/W 0(16 bits) CLK_STOP R/W DM_PG1 R/W 0(page 0) DC32-ODD R/W 0(even) CLK_DIV1 R/W DM_PG0 R/W 0(page 0) BSP2SEL R/W 0(CODEC) CLK_DIV0 R/W
CODEC_H
4 5
VERSION DM_CNTL
MISC
CODEC_CLK
DIV_SEL R/W
Note: R indicates Read Only, R/W indicate Read and Writable
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2.2.4.1.1 DSP USER_REG Register (I/O Address 0x0000) The USER register controls the status of the 4 user LEDs and the state of the 4 Position User DIP Switch. The table below summarizes (bold indicates default) the function of each bit in the USER_REG register. Table 3: USER_REG Bit Definition Bit #
7 6 5 4 3 2 1 0
Name
USER_SW3 USER_SW2 USER_SW1 USER_SW0 USER_LED3 USER_LED2 USER_LED1 USER_LED0
R/W
R R R R R/W R/W R/W R/W
Description
User DIP Switch S2-4 (1 = Off, 0=On) User DIP Switch S2-3 (1 = Off, 0=On) User DIP Switch S2-2 (1 = Off, 0=On) User DIP Switch S2-1 (1 = Off, 0=On) User Defined LED D12, Control(0=Off, 1=On) User Defined LED D11, Control(0=Off, 1=On) User Defined LED D10, Control(0=Off, 1=On) User Defined LED D9, Control(0=Off, 1=On)
2.2.4.1.2 DSP Daughter Card Register (I/O Address 0x0001) The DC_REG register provides user control of the two daughter card control outputs, the daughter card reset signal, and the status of the two daughter card Status signals and the Daughter Card Detect Signal. The table below summarizes (bold indicates default) the function of each bit in the DC_REG register. Table 4: DC_REG Bit Definitions Bit #
7 6 5 4 3 2 1 0
Name
DC_DET DC_IO_CTL DC_STAT1 DC_STAT0 DC_RST 0 DC_CNTL1 DC_CNTL0
R/W
R R/W R R R/W R R/W R/W
Description
Daughter Card Detection(0=No board, 1=Daughter Card Detected) 0=None, 1=DC_RE-,DC_WE- active on I/O Cycles Daughter Card Status 1 (0=low, 1=high) Daughter Card Status 0 (0=low, 1=high) Daughter Card Reset (1=Reset Active Low) Always zero Daughter Card Control 1 (0=low, 1=high) Daughter Card Control 0 (0=low, 1=high)
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2.2.4.1.3 DSP CODEC_L_CMD (I/O Address 0x0002) and CODEC_H_CMD Register (I/O Address 0x0003) This Read/Write register is use to send command codes to the on board Burr-Brown PCM3002 CODEC. The two 8-bit register form the 16 command word that is to be sent to the CODEC. Any read accesses to these two I/O addresses will only read the last command that was written to the CODEC. Write accesses to I/O address 0x0002 will only store the byte into the CODEC_L register. After the completion of a write to I/O address 0x0003, the CPLD will transfer the complete 16-bit command word to the CODEC. Refer to the PCM3002 data sheet for complete definition of the bits and commands. NOTE: After each write of CODEC_H register the DSP is required to wait 1 millisecond, before writing any data to either location. The user may poll bit 7 of I/O address 0x06 (MISC Register) to determine if the Codec is Ready, this bit contains the CODEC_RDY- bit. When the CODEC_RDY- is equal to zero (0x0), then a new command can be written to these command registers. When the CODEC_RDY is equal to one (1), then the previous command in still be shifted into the PCM3002 device. 2.2.4.1.4 Version Register (I/O Address: 0x0004) This register contains two version codes of the DSK. The CPLD version code is the upper 4-bits of this register. The CPLD version code is coded into the device during compilation of the VHDL source. The board version code is read from the lowest 3-bits of this register. The board version is set during board assembly. Table 5: Version Register Bit Definitions Bit #
7 6 5 4 3 2 1 0
Name
CPLD_VER3 CPLD_VER2 CPLD_VER1 CPLD_VER0 0 DSK_VER2 DSK_VER1 DSK_VER0
R/W
R R R R R R R R
Description
Most Significant CPLD Version Bit CPLD Version Bit CPLD Version Bit Least Significant CPLD Version Bit Always 0 Most Significant DSK Board Version Bit DSK Board Version Bit Least Significant DSK Board Version Bit
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2.2.4.1.5 DSP DM_CNTL Register (I/O Address 0x0005) The DM_CTRL register enables the DSP software to control the data and program memory space selection between external on-board and off-board daughter card memory. This Register also supplies the upper page address bits for data memory accesses. Since the 5416 DSK only provides a 32K window for external data memory 5 additional address bits are supplied by the CPLD, to expand the DSKs data reach. The DM_SEL bit selects whether accesses to data memory locations at 0x8000 to 0xFFFF are onboard, or whether the accesses select daughter card memory locations. MEMTYPE_DS selects whether onboard data memory accesses from 0x8000 to 0xFFFF access flash memory (The default at reset to allow the DSP to support parallel booting from on-board FLASH) or whether these accesses select the on-board SRAM. Note that DM_SEL has precedence over MEMTYPE_DS, therefore DM_SEL must be 0 to access on board data memory space. MEMTYPE_PS selects either Flash in external on board program space (MEMTYPE_PS=0) or SRAM in external on board space (MEMTYPE_PS=1). All external accesses to program space from 0x000000 to 0x3FFFFF access on board memory. Accesses from 0x40000 to 0x7FFFFF access daughter card program space memory. The DM_PG[4..0] bits are used as Page address bits for Data memory accesses. The DSPs address A0-A14 plus the 5 DM_PG[4-0] are combined to make a 19 bit word address. Both the SRAM and the FLASH as well as the Daughter Card Interface use this access mechanism. (Note that the SRAM pages are 32K each, and the FLASH pages are 32K each.) With the five DM_PG bits provided, thirty-two, 32K data memory pages can be accessed onboard, as well as on a daughter card.
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The table below shows the DM_CTL bit definitions. Table 6: Data Memory (DM_CNTL) Bit Definitions Bit #
7 6 5 4 3 2 1 0
Name
DM_SEL MEMTYPE_DS MEMTYPE_PS DM_PG4 DM_PG3 DM_PG2 DM_PG1 DM_PG0
R/W
R/W R/W R R/W R/W R/W R/W R/W
Description
Data Memory Selection (0=on board memory, 1 daughter card) 0= FLASH ENABLED, 1 = SRAM Memory For Data Space Access 0= FLASH ENABLED, 1 = SRAM Memory For Program Space Access Flash/SRAM/Daughter Cards Memory Page Bit 4 (defaults to 0) MSB Flash/SRAM/Daughter Cards Memory Page Bit 3 (defaults to 0) Flash/SRAM/Daughter Cards Memory Page Bit 2 (defaults to 0) Flash/SRAM/Daughter Cards Memory Page Bit 1 (defaults to 0) Flash/SRAM/Daughter Cards Memory Page Bit 0 (defaults to 0) LSB
Descriptions appearing in bold are defaults.
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2.2.4.1.6 MISC Register (I/O Address 0x0006) The MISC Register contains function bits that control data memory access width, the DSPs MCBSP2 selection and the Codec Control Shift register ready status. DB_WIDE determines whether daughter card data memory and I/O accesses are 16 or 32-bit. When 32-bit (wide) mode is selected, daughter card data memory and I/O accesses are asserted to the daughter card based on the DB_32ODD selection. When DB_WIDE is 0, 16-bit accesses are performed, and when DB_WIDE is 1, 32-bit accesses are performed. DB_32ODD selects whether a 32 bit daughter card accesses are to an even (0) or odd (1) address. This selection is required to enable data and I/O selects to the daughter card at the appropriate time. If a 32-bit daughter card access is to an odd address, then DB_32ODD should be to 1. If a 32-bit daughter card access is to an even address, then DB_32ODD should be 0. For, 32-bit daughter card writes, the upper 16 bits should be written first to the destination address plus 1, and then lower 16 bits should be written to the destination address. For example, for a 32-bit write to daughter card memory at 0x8000, DB_32ODD should be 0, the most-significant word (MSW) should be written to 0x8001, and the least-significant word (LSW) should be written to 0x8000. For 32-bit daughter card reads, the lower 16 bits should be read first from the source address, and then the upper 16 bits should be read from the source address plus 1. For example, for a 32-bit read from daughter card memory at 0x8001, DB_32ODD should be 1, the LSW should be read from 0x8001 and the MSW should be read from 0x8002 CODEC_RDY is the status bit of the Control channel shift register for the on board PCM3002 Codec. Before writing to the Codec Control channel the CODEC_RDY bit should be checked. BSP2SEL is used to determine if the McBSP 2 channel on the 5416 is used to access the data channel on the onboard PCM3002 codec or if the McBSP 2 channel will be routed to the HPI Expansion Connector. Table 7: MISC Register Bit Definitions Bit #
7 6 5 4 3 2 1 0
Name
CODEC Ready 0 0 0 0 DC_WIDE DC32_ODD BSP2SEL
R/W
R R R R R R/W R/W R/W
Description
CODEC Command Transfer Ready (0-ready, 1=not ready) Always zero Always zero Always zero Always zero Daughter Card Data Memory Width Select (0=16 bits, 1=32 bits) 32 Bit Daughter Card Address Access Mode (0=even, 1=odd) McBSP2 Select (0=PCM3002 Data Channel,1=Daughter card)
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2.2.4.1.7 CODEC_CLK Register (I/O Address: 0x0007) This register controls the divide ratio of the PCM3002 Codec. At reset the register is initialized to zero (0x00). The Codec input Clock is 12.288 Megahertz at reset. The Codec Output clock is equal to the Codec input Clock resulting in a 48Khertz sample rate. The Codec input clock can be divided and sent to the codec output Clock via this register. The CLK_DIV bits are only valid when the DIV_SEL bit is set to 1. Table 8: Codec Clock Register Bit Definitions Bit #
7 6 5 4 3 2 1 0
Name
0 0 0 0 DIV_SEL CLK_STOP CLK_DIV1 CLK_DIV0
R/W
R R R R R/W R/W R/W R/W
Description
Always zero Always zero Always zero Always zero 1=Codec Clock Divide Selected Rate is set by CLK_DIV Bits 0=Codec In Clock same as Codec Out Clock CLK_STOP 00 divide by 2 (fs=24Khz.), 01=divide by 4 (fs=12Khz), 10=divide by 6 (fs=8Khz), 11 divide by 8 (fs=6Khz)
There is a specific sequence that must be followed when changing the Clock divider to ensure proper operation. This sequence is outlined below. 1) Set the CLK_STOP bit CODEC_CLK_REG = CODEC_CLK_REG | CLK_STOP; 2) Set the CLK_DIV1 and CLK_DIV0 bits CODEC_CLK_REG = (CODEC_CLK_REG & ~0x03) | (USER_CLK_DIV1 | USER_CLK_DIV0); 3) Reset the CLK_STOP bit CODEC_CLK_REG = CODEC_CLK_REG & ~CLK_STOP; 4) Set the DIV_SEL CODEC_CLK_REG = CODEC_CLK_REG | DIV_SEL;
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2.2.5 Flash ROM Interface The 256K word Flash is mapped into the VC5416s program space and data space. This flash is meant for boot loading of programs using the VC5416s parallel boot loader in microcontroller mode or direct loading in microprocessor mode. For data space accesses there are eight pages (8) of 32K words of flash mapped in the VC5416s data space from 0x8000 to 0xFFFF. The selected page is determined by the CPLDs DM_PG[4:0] bits in the DM_CTRL register. These pages are referred to as F_PAGE0 - F_PAGE7 for easy reference. Various control bits in the DM_CTRL register and the VC5416s internal PMST register affect the decoding as shown in the tables below. The table below shows how this memory is mapped via data memory accesses. External Data Accesses in 0x08000-0x0FFFF are paged with A0-A14 being supplied directly by the DSP and page address DM_PG[0-4] being supplied by the interface CPLD. Note: Address line A15 is not used but must be a 1 to access external data space. Table 9: FLASH ROM Data Space Access Addressing
A15=1 DM_PG4 M19 DM_PG3 M18 DM_PG2 M17 DM_PG1 M16 DM_PG0 M15 M 1 4 M 1 3 M 1 2 M 1 1 M 1 0 M 9 M 8 M 7 M 6 M 5 M 4 M 3 M 2 M 1 M 0 A 1 4 A 1 3 A 1 2 A 1 1 A 1 0 A 9 A 8 A 7 A 6 A 5 A 4 A 3 A 2 A 1 A 0 DSP Address Page Address Memory Address
A[15:0] is DSP Address DM_PG[4:0] are located in DM_CTNL Register of CPLD at I/O Location 0x0005 bits 4-0. See section 2.2.4.1.5 that discusses the DM_CTNL register. M[19:0] is memory Address
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The PMST Register and the interface CPLD are the factors that control the Data memory decoding as shown in the table below. Table 10: Flash ROM Data Memory Address
DSP ADDRESS RANGE 0x0000-0x07FFF 0x8000-0xFFFF 0x8000-0xFFFF 0x8000-0xFFFF 0x8000-0xFFFF 0x8000-0xFFFF 0x8000-0xFFFF 0x8000-0xFFFF 0x8000-0xFFFF 0x8000-0xFFFF 0x8000-0xFFFF DM_PG[4.0]** X X 0 1 2 3 4 5 6 7 8-31 DROM* X 1 0 0 0 0 0 0 0 0 0 DM_SEL** X X 0 0 0 0 0 0 0 0 0 MEMTYPE_DS** X X 0 0 0 0 0 0 0 0 0 ACCESS Internal DARAM and Registers Internal DARAM External (F_PAGE0) External (F_PAGE1) External (F_PAGE2) External (F_PAGE3) External (F_PAGE4) External (F_PAGE5) External (F_PAGE6) External (F_PAGE7) External Flash IMAGES
Note: External address is A0-A14 plus 5 page register bits. * in VC5416 processors PMST register ** in CPLD registers
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Program space directly accesses the flash memory as long as the access is between 0x000000 to 0x3FFFFF. The overlay and MP/MC- bits in the PMST register will determine if the memory is internal or external. MEMTYPE_PS determines if SRAM or flash ROM is selected. Table 11: Flash ROM Program Memory Address
DSP ADDRESS RANGE 0x000000-0x007FFF 0x000000-0x007FFF 0x008000-0x00BFFF 0x00C000-0x00FFFF 0x00C000-0x00FFFF 0x01000-0x017FFF 0x010000-0x017FFF 0x018000-0x01FFFF 0x020000-0x027FFF 0x020000-0x027FFF 0x028000-0x02FFFF 0x030000-0x037FFF 0x030000-0x037FFF 0x038000-0x03FFFF MP/MC * X X X 0 1 X X X X X X X X X OVLY * 1 0 X X X 1 0 X 1 0 X 1 0 X . . . 0x3F8000-0x3FFFFF 0x400000-0x407FFF X X 1 1 X 0 External Image F_PAGE 7 Internal Daughter Card Access in 32K pages (0x8000-0xFFFF) if OVLY=1 All pages from 0x4000000x7FFFFF if OVLY=0 IMAGES MEMTYPE_PS** X 0 0 X 0 0 X 0 X 0 0 X 0 0 ACCESS Internal External F_PAGE 0 External F_PAGE 1 Internal External F_PAGE 1 Internal External F_PAGE 2 External F_PAGE 3 Internal External F_PAGE 4 External F_PAGE 5 Internal External F_PAGE 6 External F_PAGE 7
0x408000-0x40FFFF
* in VC5416 processor ** in CPLD
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2.2.6 SRAM Interface
The 64K word SRAM is mapped into the VC5416s program space and data space. This SRAM provides a mechanism to support on chip DMA and allows development of boot code for flash rom For data space accesses there are two pages (2) of 32K words of SRAM mapped in the VC5416s data space from 0x8000 to 0xFFFF. The selected page is determined by the CPLDs DM_PG[4:0] bits in the DM_CTRL register. These pages are referred to as SR_PAGE0 and SR_PAGE1 for easy reference. Various control bits in the DM_CTRL register and the VC5416s internal PMST register affect the decoding as shown in the tables below. The table below shows how this memory is mapped via data memory accesses. External Data Accesses in 0x08000-0x0FFFF are paged with A0-A14 being supplied directly by the DSP and page address DM_PG[0-4] being supplied by the interface CPLD. Note: Address line A15 is not used but must be a 1 to access external data space. Table 12: SRAM Data Space Access Addressing
A15=1 DM_PG4 M19 DM_PG3 M18 DM_PG2 M17 DM_PG1 M16 DM_PG0 M15 M 1 4 M 1 3 M 1 2 M 1 1 M 1 0 M 9 M 8 M 7 M 6 M 5 M 4 M 3 M 2 M 1 M 0 A 1 4 A 1 3 A 1 2 A 1 1 A 1 0 A 9 A 8 A 7 A 6 A 5 A 4 A 3 A 2 A 1 A 0 DSP Address Page Address Memory Address
A[15:0] is DSP Address DM_PG[4:0] are located in DM_CTNL Register of CPLD at I/O Location 0x0005 bits 4-0. See section 2.2.4.1.5 that discusses the DM_CTNL register. M[19:0] is memory Address
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The PMST Register and the interface CPLD are the factors that control the Data memory decoding as shown in the table below. Table 13: SRAM Data Memory Address
DSP ADDRESS RANGE 0x0000-0x07FFF 0x8000-0xFFFF 0x8000-0xFFFF 0x8000-0xFFFF 0x8000-0xFFFF DM_PG[4.0]** X X 0 1 2-31 DROM* X 1 0 0 0 DM_SEL** X X 0 0 0 MEMTYPE_DS** X X 1 1 1 ACCESS Internal DARAM and Registers Internal DARAM External (SR_PAGE0) External (SR_PAGE1) External SRAM IMAGES
Note: External address is A0-A14 plus 5 page register bits. * in VC5416 processors PMST register ** in CPLD registers
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Program space directly accesses the SRAM as long as the access is between 0x000000 to 0x3FFFFF. The overlay and MP/MC- bits in the PMST register will determine if the memory is internal or external. MEMTYPE_PS determines if SRAM or flash ROM is selected. Table 14: SRAM Program Memory Address
DSP ADDRESS RANGE 0x000000-0x007FFF 0x000000-0x007FFF 0x008000-0x00BFFF 0x00C000-0x00FFFF 0x00C000-0x00FFFF 0x01000-0x017FFF 0x010000-0x017FFF 0x018000-0x01FFFF MP/MC * X X X 0 1 X X X OVLY * 1 0 X X X 1 0 X . . . 0x3F8000-0x3FFFFF 0x400000-0x407FFF X X 1 1 X 0 Image SR_PAGE 1 Internal Daughter Card Accesses in 32K pages (0x8000-0xFFFF) if OVLY=1 All pages from 0x4000000x7FFFFF if OVLY=0 IMAGES MEMTYPE_PS** X 1 1 X 1 0 X 0 ACCESS Internal External SR_PAGE 0 External SR_PAGE 1 Internal External SR_PAGE 1 Internal Image SR_PAGE 0 Image SR_PAGE 1
0x408000-0x40FFFF
* in VC5416 processor ** in CPLD
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2.2.7 Codec Interface The DSK uses a PCM3002 stereo Codec to provide analog inputs and outputs. The interface to the codec is through two channels, one for control the other for data. The CPLD on the DSKs is used to interface to the control channel via 2 8 bit registers in I/O space CODEC_L and CODEC_H. Furthermore, the CPLD generates all required timing signals for the PCM3002 via a clock oscillator and the CODEC_CLK control register. The default CODEC system clock is 12.488-MHz. The CPLD uses the CODEC system clock to generate a bit clock of 3.0122-MHz and a frame sync signal of 48-KHz. This can be changed to other frequencies as outlined in the CODEC_CLK section of the CPLD. The Data to the codec, is supplied via the VC5416s McBSP2 interface. There is a bit in the MISC register of the CPLD which will allow the McBSP2 register to be routed to the HPI expansion connector, however, the default path is to the PCM3002 Codec. The diagram below shows the interconnection between the Codec, CPLD, and DSP.
HPI CONNECTOR
TMS320VC5416
M c B S P 2
QUICK SWITCH MUX BCLKIN LRCIN DIN DOUT
DATA I/F
ADDRESS CONTROL
DATA
PCM3002
MC
CPLD
MD ML
CONTROL I/F
SYSCLK
12.288 Mhz OSC
Figure 2-6, TMS320VC5416 DSK CODEC INTERFACE
2-24

2.2.7.1 Programming the Codec Control Interface The PCM3002 Control Interface has four 16-bit internal registers that are software controlled via a serial interface. The CPLD has two internal 8-bit registers that when written in sequence will transfer their contents to the CODECs control interface. The serial master control signals of the CODEC consist of the CODEC_MC (master clock), CODEC_MD (master data), and CODEC_ML (master load). To write a control word to the CODEC, the user will write two 8-bit bytes to the CPLD at I/O locations 0x0002 (CODEC_L), and 0x0003 (CODEC_H). The first byte is the lower order byte of the 16-bit control word, the second byte is the higher order byte of the 16-bit control word. After the completion of the write to CODEC_H, the CPLD will automatically transmit the data serially to the CODEC control interface over the master control signals. Before another Control Interface Codec Transfer is done, the programmer needs to check the CODEC_RDY bit in the MISC Register of the CPLD (IO address 0x0006 bit 7). This bit gives the current state of the control interface shift register in the CPLD. For additional information about the control bits of the CODEC, please refer to the PCM3002 data sheet. 2.2.7.2 Programming the Data interface The Data interface on the PCM3002 is connected to the McBSP2 pins on the VC5416 DSP. The table below shows the pin assignments of this interconnection. Table 15: PCM3002 - VC5416 Interconnect PCM3002 Signal Type SYSCLK BCLKIN LRCIN DIN DOUT I I I I O CPLD Signal CODEC_CLK CODEC_BCLK N/A N/A N/A Type O O VC5416 Signal Type N/A BCLKR2 BCLKX2 BFSR2 BFSX2 BDX2 BDR2 I O O I
The CPLD has a CODEC_CLK register that allows the programmer to change the sampling frequencies shown in the CODEC_CLK register section.
2-25

2.2.7.3 PCM3002 Codec Input/Output Circuitry Four industry standard 3.5 mm. connectors are used in the audio interface, one for line-level audio inputs, one for a microphone, one for line-level audio outputs, and one for speakers or headphones. The line-level inputs are stereo, while the microphone input only supports a single channel (mono). On the output side there are stereo connections on both the amplified and unamplified signals. The two analog inputs (line and microphone) are AC coupled, active filtered and mixed prior to being digitized by the PCM3002E connected to the McBSP2 port of the DSP. The line-level input has a fixed gain of 0dB. The line-level inputs support signal levels of up to 2Vrms. The microphone input is designed for electret microphones that require a bias voltage. A dynamic microphone can be used if capacitors are used to block the bias voltage. The maximum allowable signal level from the microphone is 1 Vrms. The microphone input has a potentiometer which allow the user to adjust gain on the microphone input. The DAC output from the PCM3002 CODEC has programmable attenuation from +0dB to mute in 1.5dB increments. The DAC output channel is filtered using a multiple-feedback 2nd order active filter. The post-filter has a cut-off frequency of 30KHz. The post-filtered information is directly passed to a standard stereo audio jack for line-level loads (~10Kohms) and also passed through an output driver stage for connection to low impedance speakers or headphones (e.g. 8 to 32 ohms).
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2.2.8 Daughter Card Memory Interface The 5416 DSK supports the standard daughter card interface interconnections. Accesses to the Daughter-cards can be done via Program Space, Data Space, or I/O space. On the 5416 DSK Daughter cards all spaces support 16 data bits transfers and Data Space and I/O accesses can support 32 data bits transfers. DM_SEL must be set for data space accesses. I/O space and program space accesses use memory decode to control accesses It is recommended to run the EMIF in CLKOUT/2 mode at higher clock rates (above 100 MHz) to avoid buffer conflicts. Sample programs for accessing daughter card 16 bit program memory, 16 and 32 bit data memory, and 16 and 32 bit I/O memory are included in the .pdf file: c:\TI\docs\pdf\5416_dsk_expsw.pdf. 2.2.8.1 Program Space Accesses Daughter-Card Program Space accesses on the DSK are available when A22 is a logic 1. All Daughter Card Program Space accesses are 16 bits wide. Therefore, all external accesses from 0x400000 to 0x7FFFFF access the daughter card space. Note that if the OVLY bit is selected only the upper 32K of each (0x8000 - 0xFFFF) is mapped to the daughter card interface. These accesses are shown in the table below: Table 16: Program Space Accesses DSP Address Range 0x000000-0x3FFFFF 0x400000-0x407FFF 0x400000-0x407FFF 0x408000-0x40FFFF 0x410000-0x417FFF 0x410000-0x417FFF 0x418000-0x41FFFF 0x42000 to 0x7FFFF * In VC5416 processor OVLY * X 1 0 X 1 0 X See above maps Access On-board/internal Internal DSP Access Daughtercard Daughtercard Internal DSP Access Daughtercard Daughtercard Same as above maps
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2.2.8.2 Data Space Accesses Daughter card data memory accesses on the DSK are available when A15 is a logic 1, DROM is turned off in the PMST register, and the DM_SEL bit in the DM_CNTL register of the CPLD is set to 1. The address range from the DSP is 0x8000 to 0xFFFF, however the 5 DM_PG[0:4] bits are added to the DSPs A0-A14 lines to make thirty-two (32) 32K 16 bit accessible pages. Both 16 and 32 bit accesses are available for the data space accesses. These accesses are shown in the table below: Table 17: Data Space Accesses
DSP Address Range 0x0000-0x7FFF 0x8000-0xFFFF 0x8000-0xFFFF 0x8000-0xFFFF 0x8000-0xFFFF DM_PG[4:0]** X X 0 1:31 0 DROM* X X 0 0 0 DM_SEL** X 0 1 1 1 MEMTYPE_DS** X X X X X DC_WIDE** X X 0 0 1 DC32_ODD** X X X X 0 ACCESS Internal Onboard/internal Daughtercard 16 bit access page 0 Daughtercard 16 bit access page 1-31 Daughtercard 32 bit access page 0 even address Daughtercard 32 bit access page 0 odd address Daughtercard 32 bit access page 1-31 even address Daughtercard 32 bit access page 1-31 odd address
0x8000-0xFFFF
0x8000-0xFFFF
1:31
0x800-0x7FFFF
1:31
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2.2.8.2.1 Data Space 32 Bit Accesses Like with 16 bit data accesses there are two 32 (thirty-two) 32K word pages available to daughter card accesses. However, for 32 bit data space accesses specific sequences must be programmed to get correct 32 bit wide data transfers For even address sequences (e.g. 0x28400) the accesses are broken up into 2 accesses one at 0x8400 and one at 0x8401.Note the upper address comes from the DM[0:4] bits. The DC-32 Odd bit in the CPLD MISC register should be set to 0, and the sequence below shows the correct access procedure. Write Sequence: 1. Set the page address in DM_CTNL to 00101 binary. This will point to page 0x28. 2. Set the DC_WIDE bit and clear the DC32_ODD bit in the CPLD MISC register 3. Do the 2 Data Space accesses: - Most Significant WORD at ODD address (0x8401) - Least Significant word at EVEN address (0x8400) 4. Turn off the DC_WIDE bit in the MISC register Read Sequence 1. Set the page address in DM_CTNL to 00101 binary. This will point to page 0x28. 2. Set the DC_WIDE bit and clear the DC32_ODD in the CPLD MISC register 3. Do the 2 Data Space accesses: - Least Significant WORD at EVEN address (0X8400) - Most Significant word at ODD address (0x8401) 4. Turn off the DC_WIDE bit in the MISC register For Odd address sequences (e.g. 0x28401) the accesses are broken up into 2 accesses one at 0x8401 and one at 0x8402. The DC-32 Odd bit in the CPLD MISC register should be set to 1, and the sequence below shows the correct access procedure Write Sequence: 1. Set the page address in DM_CTNL to 00101 binary. This will point to page 0x28. 2. Set the DC_WIDE bit and clear the DC32_ODD in the CPLD MISC register 3. Do the 2 Data Space accesses: - Most Significant WORD at EVEN address (0x8402) - Least Significant word at ODD address (0x8401) 4. Turn off the DC_WIDE bit in the MISC register Read Sequence 1. Set the page address in DM_CTNL to 00101 binary. This will point to page 0x28. 2. Set the DC_WIDE bit and clear the DC32_ODD in the CPLD MISC register 3. Do the 2 Data Space accesses: - Least Significant WORD at EVEN address (0x8401) - Most Significant word at ODD address (0x8402) 4. Turn off the DC_WIDE bit in the MISC register
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2.2.8.3 I/O Space Accesses Daughter-Card I/O Space accesses on the DSK are available when the DSPs address bit A15 is a logic 1. The address range for I/O accesses is 32K Words from 0x8000 to 0xffff. Access data width can be either 16 bits or 32 bits wide. These accesses are shown in the table below: Table 18: I/O Space Accesses DSP Address Range 0x0000-0x7FFF 0x8000-0xFFFF 0x8000-0xFFFF 0x8000-0xFFFF DC_WIDE ** X 0 1 1 DC32_ODD** X X 0 1 Access On-board Daughtercard 16 bit Access Daughtercard 32 bit Access Daughtercard 32 bit Access
** In CPLD Note specific sequences are necessary for 32 bit access. For 16 bit accesses there is no specific programming sequences that need to be implemented.
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2.2.8.3.1 I/O Space 32 Bit Accesses For 32 bit accesses specific sequences must be programmed to get correct 32 bit wide data transfers For even address sequences (e.g. 0xC000) the accesses are broken up into 2 accesses one at 0xC000 and one at 0xC001. The DC-32 Odd bit in the CPLD MISC register should be set to 0, and the sequence below shows the correct access procedure. Write Sequence: 1. Set the DC_WIDE bit and clear the DG32_ODD bit in the CPLD MISC register 2. Do the 2 I/O accesses: - Most Significant WORD at ODD address (0xC001) - Least Significant word at EVEN address (0xC000) 3. Turn off the DC_WIDE bit in the MISC register Read Sequence 1. Set the DC_WIDE bit and clear the DG32_ODD bit in the CPLD MISC register 2. Do the 2 I/O accesses: - Least Significant WORD at EVEN address (0XC000) - Most Significant word at ODD address (0xC001) 3. Turn off the DC_WIDE bit in the MISC register For Odd address sequences (e.g. 0xC001) the accesses are broken up into 2 accesses one at 0xc001 and one at 0xc0002. The DC-32 Odd bit in the CPLD MISC register should be set to 1, and the sequence below shows the correct access procedure Write Sequence: 1. Set the DC_WIDE and DC32_ODD bits in the CPLD MISC register 2. Do the 2 I/O accesses: - Most Significant WORD at EVEN address (0xC002) - Least Significant word at ODD address (0xC001) 3. Turn off the DC_WIDE bit in the MISC register Read Sequence 1. Set the DC_WIDE and DC32_ODD bits in the CPLD MISC register 2. Do the 2 I/O accesses: - Least Significant WORD at EVEN address (0xC001) - Most Significant word at ODD address (0xC002) 3. Turn off the DC_WIDE bit in the MISC register
2-31

2.2.9 Wait States The TMS320VC5416 has an on chip wait state generator controller controlled by registers SWWSR and SWCR mapped in the data memory. The table below shows these 2 registers and their function. 2.2.9.1 Software Wait State Generator The software wait state generator on the TMS320VC5416 can be extended external bus cycles by up to 14 machine cycles. Devices that require more then 14 wait-states can be interfaced using the hardware READY line. The software wait state register, SWWSR, controls the operation of the wait state generator. The 14 LSBs of the SWWSR specifies the number of wait states (0-7) to be inserted for external memory accesses to five separate ranges. This allows a different number of wait states for each of the 5 address ranges. Additionally, the software wait state multiplier, SWSM, bit of the wait state control register, SWCR, defines a multiplication factor of 1 or 2 for the number of wait states. At reset, the wait state generator is initialized to provide 7 wait states on all external memory accesses. The SWWSR bit fields are shown in the table below. Table 19: SWWSR Register Bit Fields Bits Space Read, Write Reset Value 15 XPA R/W 0 14 I/O R/W 111 12 11 Data R/W 111 9 8 Data R/W 111 6 5 R/W 111 3 2 R/W 111 0
Program
Program
2-32

The bit fields in SWWSR are described in the table below. Table 20: SWWSR Bit Field Definition Bit # Bit Name XPA Reset Value 0 15 Function Extended program address control bit. XPA is used in conjunction with the program space fields (bits 0-5) to select the address range for program space wait states I/O space. The field value (0-7) corresponds to the base number of wait states for I/O space accesses within addresses 0x0000-0xFFFF. The SWSM bit of the SWCR defines a multiplication factor of 1 or 2 for the base number of wait states. Upper Data Space. The field value (0-7) corresponds to the base number of wait states for external data space accesses within addresses 0x8000-0xFFFF. The SWSM bit of the SWCR defines a multiplication factor of 1 or 2 for the base number of wait states. Lower Data Space. The field value (0-7) corresponds to the base number of wait states for external data space accesses within addresses 0x0000-0x7FFF. The SWSM bit of the SWCR defines a multiplication factor of 1 or 2 for the base number of wait states. Upper Program Space. The field value (0-7) corresponds to the base number of wait states for external program space accesses within addresses: 5-3 Program 111 - XPA= 0: 0x8000 - 0xFFFF - XPA= 1: The upper program space bit field has no effect on wait states The SWSM bit of the SWCR defines a multiplication factor of 1 or 2 for the base number of wait states. Lower Program Space. The field value (0-7) corresponds to the base number of wait states for external program space accesses within addresses: 2-0 Program 111 - XPA= 0: 0x8000 - 0x7FFF - XPA= 1: 0x00000 - 0xFFFFF The SWSM bit of the SWCR defines a multiplication factor of 1 or 2 for the base number of wait states.
14-12
I/O
111
11-9
Data
111
8-6
Data
111
2-33

The software wait state multiplier bit of the software wait state control register, SWWSR, is used to extend the base number of wait states selected by the SWWSR. The SWSR bit fields are shown in the table below. Table 21: Software Wait State Control Register Bits Fields Bit # Function Reset, Write Reset Value 15 Reserved R/W 0 1 0 SWSM R/W 0
The bit fields in SWWSR are described in the table below. Table 22: SWWSR Bit Field Definition Bit # 15-1 Bit Name Reserved Reset Value 0 Function These bits are reserved and unaffected by writes Software wait state multiplier. Used to multiply the number of wait states defined in the SWWSR by a factor of 1 or 2. 0 SWSM 0 - SWSM = 0: wait state base values are unchanged (multiplied by 1) - SWSM = 1: wait state base values are multiplied by 2 for a maximum of 14 wait states.
This controller allows various regions in memory to be programmed to different wait state values. The TMS320VC5416 powers up with maximum wait states. On the TMS320VC5416 DSK the access time for various components in the table below. Table 23: Memory Wait States Device SRAM Flash CPLD Access Time 12 ns. 70 ns. 60 ns. Decoder 10 ns. 10 ns. Total Access Time 22 ns. 80 ns. 60 ns.
2-34

The access time on the TMS320VC5416 is ta(A)M1 for non-consecutive accesses and ta(A)M2 for consecutive accesses. The table below shows various access times for various frequencies. Table 24: Access Times Frequency 160 Mhz. 120 Mhz. 96 Mhz. 48 Mhz. 2H 6.25 ns. 8.33 ns. 10.4 ns. 20.83 ns. Each Wait State WS*6.25 ns. WS*8.33 ns. WS*10.4 ns. WS*20.83 ns. ta(A)1st Cycle (2H-4) 2.25 ns. 6.4 ns. 6.4 ns. 16.83 ns.
It is recommended to operate the EMIF in CLKOUT/2 mode at higher frequencies (CPU frequency from 96 - 160 Mhz.) to avoid buffer contention from daughter card buffers. Note that wait states with EMIF in CLKOUT/2 mode can be programmed to one-half the value in the table below. The table below shows the maximum wait states for the various frequencies. various frequencies. Table 25: Minimum Wait States Frequency 160 Mhz. 120 Mhz. 96 Mhz. 48 Mhz. SRAM 3 2 2 0 Flash 12 10 7 4 CPLD 9 7 6 3
2-35

2.3 TMS320VC5416 DSK Jumpers The TMS320VC5416 DSK has a single jumper block, JP4, which controls the power up CLKMODE and MP/MC setting. 2.3.1 JP4, DSP Clock and Mode Configuration Jumper JP4 is a 4 x 2 connector that determines the power up CLKMODE on the DSP, and selects whether the DSP is in microcomputer mode or microcontroller mode. The table below shows the clock and mode selection settings. Table 26: JP4, DSP Configuration CLKMD1
OFF OFF OFF OFF ON ON ON ON OFF OFF OFF OFF ON ON ON ON
CLKMD2
OFF OFF ON ON OFF OFF ON ON OFF OFF ON ON OFF OFF ON ON
CLKMD3
OFF ON OFF ON OFF ON OFF ON OFF ON OFF ON OFF ON OFF ON
MP/MC
OFF OFF OFF OFF OFF OFF OFF OFF ON ON ON ON ON ON ON ON
Clock Mode
1/2 x CLKIN PLL Off, OSC On 1 x CLKIN PLL On, OSC On 1/4 x CLKIN PLL Off, OSC On 2 x CLKIN PLL On, OSC On RESERVED 5 x CLKIN PLL On, OSC On 10 x CLKIN PLL On, OSC On 1/2 x CLKIN PLL Off, OSC Off 1/2 x CLKIN PLL Off, OSC On 1 x CLKIN PLL On, OSC On 1/4 x CLKIN PLL Off, OSC On 2 x CLKIN PLL On, OSC On * RESERVED 5 x CLKIN PLL On, OSC On 10 x CLKIN PLL On, OSC On 1/2 x CLKIN PLL Off, OSC Off
DSP MP/MC Mode

Microprocessor Mode Microprocessor Mode Microprocessor Mode Microprocessor Mode Microprocessor Mode Microprocessor Mode Microprocessor Mode Microprocessor Mode Microcontroller Mode Microcontroller Mode Microcontroller Mode Microcontroller Mode Microcontroller Mode Microcontroller Mode Microcontroller Mode Microcontroller Mode
Note: * is the default setting. This is the 2 x CLKIN PLL On, OSC On, Microcontroller Mode The figure below show JP4 in the default configuration. CLKMD1 CLKMD2 CLKMD3 MP/MC Figure 2-7, JP4, DSP Configuration - Default Setting 2-36 TMS320VC5416 DSK Module Technical Reference JP4

2.4 TMS320VC5416 DSK Connectors The TMS320VC5416 DSK has sixteen (16) connectors which provide the user access to the various on the DSK. The position of each connector is identified in Figure 2-1.These connectors, their size, their function, and the side of the printed circuit board they are mounted on are shown in the table below. Table 27: TMS320VC5416 DSK Connectors Connector P1 P2 P3 J1 J2 J3 J4 J5 * J6 J7 J201 JP1 JP4 # Pins 80 80 80 2 2 2 2 4 2 14 5 10 8 Function Memory Peripheral HPI Microphone Line In Line Out Speaker Optional Power Connector +5 Volt External JTAG USB JTAG CPLD Programming DSP Configuration Jumper
Note: * Not populated 2.4.1 Expansion Connectors The TMS320VC5416 DSK supports three expansion connectors that follow the Texas Instruments interconnection guidelines. The expansion connector pinouts are described in the following three sections. Note: I is on an Input pin O is on an Output pin Z is on a High Impedance pin
2-37

2.4.2 P1, Memory Expansion Connector
Table 28: P1, Memory Expansion Connector Pin #

1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71 73 75 77 79
Signal Name
+5 Volts DC_A19 DC_A17 DC_A15 DC_A13 GND DC_A11 DC_A9 DC_A7 DC_A5 +5 Volts DC_A3 DC_A1 DC_A21 GND GND DC_D31 DC_D29 DC_D27 DC_D25 +3.3 Volts DC_D23 DC_D21 DC_D19 DC_D17 GND DC_D15 DC_D13 DC_D11 DC_D9 GND DC_D7 DC_D5 DC_D3 DC_D1 GND DC_REDC_OEDC_MSTRBGND
I/O/Z
O O O O O O O O O O O O O O O O I/O/Z I/O/Z I/O/Z I/O/Z O I/O/Z I/O/Z I/O/Z I/O/Z O I/O/Z I/O/Z I/O/Z I/O/Z O I/O/Z I/O/Z I/O/Z O O O O O O
Pin #
2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 74 76 78 80
Signal Name
+5 volts DC_A18 DC_A16 DC_A14 DC_A12 GND DC_A10 DC_A8 DC_A6 DC_A4 +5 Volts DC_A2 DC_A0 DC_A20 GND GND DC_D30 DC_D28 DC_D26 DC_D24 +3.3 Volts DC_D22 DC_D20 DC_D18 DC_D16 GND DC_D14 DC_D12 DC_D10 DC_D8 GND DC_D6 DC_D4 DC_D2 DC_D0 GND DC_WEDC_RDY DC_DSGND
I/O/Z
O O O O O O O O O O O O O O O O I/O/Z I/O/Z I/O/Z I/O/Z O I/O/Z I/O/Z I/O/Z I/O/Z O I/O/Z I/O/Z I/O/Z I/O/Z O I/O/Z I/O/Z I/O/Z O O O I O O
2-38

2.4.3 P2, Peripheral Expansion Connector
Table 29: P2, Peripheral Expansion Connector Pin #

1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71 73 75 77 79
Signal Name
I/O/Z
Pin #
Signal Name
I/O/Z
O O O O O
+12 Volts * O 2 -12 Volts * GND O 4 GND +5 Volts O 6 +5 Volts GND O 8 GND +5 Volts O 10 +5 Volts RESERVED 12 RESERVED RESERVED 14 RESERVED RESERVED 16 RESERVED RESERVED 18 RESERVED +3.3 Volts O 20 +3.3 Volts DC_BCLKX0 I/O/Z 22 RESERVED DC_BFSX0 I/O/Z 24 DC_BDX0 GND O 26 GND DC_BCLKR0 I/O/Z 28 RESERVED DC_BFSR0 I/O/Z 30 DC_BDR0 GND O 32 GND DC_BCLKX1 I/O/Z 34 RESERVED DC_BFSX1 I/O/Z 36 DC_BDX1 GND O 38 GND DC_BCLKR1 I/O/Z 40 RESERVED DC_BFSR1 I/O/Z 42 DC_BDR1 GND O 44 GND DC_TOUT O 46 RESERVED RESERVED 48 DC_INT1DC_XF O 50 DC_BIOGND O 52 GND INT3I 54 RESERVED RESERVED 56 DC_IOSTRBRESERVED 58 RESERVED RESETO 60 RESERVED GND O 62 GND DC_CNTL1 O 64 DC_CNTL0 DC_STAT1 I 66 DC_STAT0 DC_INT2I 68 DC_INT3DC_PSO 70 DC_ISRESERVED 72 RESERVED RESERVED 74 RESERVED DC_DETECTI 76 GND GND O 78 DC_CLKOUT/2 GND O 80 GND * Provided from optional power connector J5
O O/Z O I O O/Z O Z O I I O O
O O I I O
O O O
2-39

2.4.4 P3, HPI Expansion Connector
Table 30: P3, HPI Expansion Connector Pin #

1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71 73 75 77 79
Signal Name
+5 Volts HP_BCLKX2 HP_BFSX2 HP_BDX2 RESERVED GND HP_HRW HP_HASHP_HCNTL1 HP_HDS2 +5 Volts HP_HRDY HP_HPI_EN RESERVED RESERVED GND RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED GND RESERVED RESERVED RESERVED RESERVED GND HP_D7 HP_D5 HP_D3 HP_D1 GND HP_HOLDARESERVED HP_DSPIACKGND
I/O/Z
O I/O/Z I/O/Z O/Z O I I I I O O I
Pin #
2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 74 76 78 80
Signal Name
+5 Volts HP_BCLKR2 HP_BFSR2 HP_BDR2 HP_CLKOUT/2 GND HP_HCNTL0 HP_HCSHP_HBIL HP_HDS1 +5 Volts HP_HPINTHP_HPI16 RESERVED RESERVED GND RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED GND RESERVED RESERVED RESERVED RESERVED GND HP_D6 HP_D4 HP_D2 HP_D0 GND HP_HOLDRESERVED HP_RSTGND
I/O/Z
O I/O/Z I/O/Z I O O I I I I O O I
O I/O/Z I/O/Z I/O/Z I/O/Z O O O O
O I/O/Z I/O/Z I/O/Z I/O/Z O I O O
2-40

2.4.5 J1, Microphone Connector The microphone interfaces to the PCM3002E via a simple op-amp circuit. The input is a 3.5 mm. stereo jack. Both inputs are connected to the microphone so it is monaural. The signals on the plug are shown in the figure below.
Ground Microphone In Figure 2-8, Microphone Stereo Jack 2.4.6 J2, Audio Line In Connector The audio line in is a stereo input. This input interfaces to the PCM3002E via a simple op-amp bias circuit. The input connector is a 3.5 mm stereo jack. The signals on the mating plug are shown in the figure below.
Ground Right Line In Left Line In Figure 2-9, Audio Line In Stereo Jack 2.4.7 J3, Audio Line Out Connector The audio line out is a stereo output. This output is driven by the PCM3002E through a simple op-amp circuit. The output connector is a 3.5 mm stereo jack. The signals on the mating plug are shown in the figure below.
Ground Right Line Out Left Line Out Figure 2-10, Audio Line Out Stereo Jack
2-41

2.4.8 J4, Headphone/Speaker Connector Connector J4 is a headphone/speaker jack. It is driven by a small TPA302 amplifier connected to the PCM3002E codec and can drive standard headphones or a high impedance speaker directly. The standard 3.5 mm jack is shown in the figure below.
Ground Right Headphone Left Headphone Figure 2-11, Headphone Jack 2.4.9 J5, Optional Power Connector Connector J5 is an optional power connector. It will operate with the standard personal computer power supply. To populate this connector use a Molex #15-24-4041. The table below shows the voltages on the respective pins. Table 31: J5, Optional Power Connector Pin # 1 2 3 4 Voltage Level +12 Volts -12 Volts Ground +5 Volts
WARNING ! Do not plug into J5 and J6 at the same time. 2.4.10 J6, +5 Volt Connector Power (5 volts) is brought onto the TMS320VC5416 DSK via the J6 connector. The connector has an outside diameter of 5.5 mm. and an inside diameter of 2.5 mm. The The diagram of J6, which has the input power is shown below. +5V J6 Ground PC Board Front View Figure 2-12, TMS320VC5416 DSK Power Connector 2-42 TMS320VC5416 DSK Module Technical Reference

2.4.11 J7, External JTAG Connector The TMS320VC5416 DSK is supplied with a 14 pin header interface, J7. This is the standard interface used by JTAG emulators to interface to Texas Instruments DSPs. The pinout for the connector is shown figure 2-6 below.
TMS TDI PD (+3.3V) TDO TCK-RET TCK EMU0
1 3 5 7 9 11 13
2 4 6 8 10 12 14
TRSTGND no pin (key) GND GND GND EMU1
Header Dimensions Pin-to-Pin spacing, 0.100 in. (X,Y) Pin width, 0.025-in. square post Pin length, 0.235-in. nominal
Figure 2-13, JTAG INTERFACE The signal names for each pin are shown in the table below. Table 32: J7, JTAG Interface Pin # 1 2 3 4 5 6 7 8 9 10 11 12 13 14 Signal Name TMS TRSTTDI GND PD no pin TDO GND TCK-RET GND TCK GND EMU0 EMU1
2-43

2.4.12 JP1, PLD Programming Connector This connector interfaces to the Altera CPLD, U18. It is used in the in the factory for the programming of the CPLD. This connector is not intended to be used outside the factory. 2.5 User LEDs TheTMS320VC5416 DSK has four user definable light emitting diodes (LEDs). These LEDs are used by the Power On Self Test (POST) but are available for user programs. They are accessed via the I/O address 0x0000. The function of each LED is shown in the table below. Table 33: User LEDs Reference Designator
D9 D10 D11 D12
LED #
1 2 3 4
Color
Green Green Green Green
Controlling Signal
CPLD Register 0, Data Bit 0 CPLD Register 0, Data Bit 1 CPLD Register 0, Data Bit 2 CPLD Register 0, Data Bit 3
On Signal State
1 1 1 1
2.5.1 System LEDs TheTMS320VC5416 DSK has four system light emitting diodes (LEDs). These LEDs indicate various conditions on the DSK. These function of each LED is shown in the table below. Table 34: System LEDs Reference Designator
D6 D7 D8 D201
Color
Green Green Green Green
Function
USB Emulation in use. When External JTAG Emulator is used this LED is off. +5 Volt present RESET Active USB Active, Blinks during USB data transfer
On Signal State
1 1 1 1
2-44

2.6 Switches The TMS320VC5416 has two switches, a Reset switch, and a 4 position user DIP switch. 2.6.1 Reset Switch/Reset Logic There are three resets on the TMS320VC5416 DSK. The first reset is the power on reset. This circuit waits until power is within the specified range before releasing the power on reset pin to the TMS320VC5416. External sources which control the reset are push button S1, and the on board embedded USB JTAG emulator. 2.6.2 4 Position User DIP Switch The TMS320VC5416 DSK has a 4 position user DIP switch, S2. It is accessible via CPLD Register 0 at I/O location 0x0000. The function of each switch is shown in the table below. Table 35: S2 Switch Positions Position
1 2 3 4
Controlling Signal
CPLD Register 0, Data Bit 4 CPLD Register 0, Data Bit 5 CPLD Register 0, Data Bit 6 CPLD Register 0, Data Bit 7
On is a logic 1, Off is a logic 0.
2-45

2.7 J201, Universal Serial Bus (USB) Embedded JTAG Emulation Connector Connector J201 provides a Universal Serial Bus (USB) Interface to the embedded JTAG emulation logic on the DSK. This allows for code development and debug without the use of an external emulator. The signals on this connector are shown in the below. Table 36: J201, USB Connector Pin # 1 2 3 4 5 6 USB Signal Name USBVdd D+ DUSB Vss Shield Shield
2-46
Appendix A TMS320VC5416 DSK CPLD Equations
CPLD equations are installed in .pdf format from the CD-ROM for the DSK in the directory: C:\TI\docs\pdf\5416_dsk_vhdl.pdf
A-1
A-2
Appendix B TMS320VC5416 DSK Schematics
This appendix contains the schematics for the TMS320VC5416 DSK. The schematics were drawn in ORCAD. Schematics for the embedded USB JTAG controller are not included.
B-1
B-2
4 3 2 1
REVISIONS REV DESCRIPTION DATE APPROVED
NOTES, UNLESS OTHERWISE SPECIFIED:
1. NP = No Populate * Orginal 01-09-01

D
2. RESISTANCE VALUES ARE IN OHMS.
3. CAPACITANCE VALUES ARE IN MICROFARADS. B BETA 12-06-2001
PRODUCTION
03-18-2002
DWN CHK ENGR ENGR-MGR C 11 C NEXT ASSY APPLICATION 4

4
DATE DATE DATE DATE

A
REVISION STATUS OF SHEETS
REV
Spectrum Digital Incorporated

DATE
SH C 12 14 MFG C 5 6 7 C C USED ON RLSE DATE DATE 13 C C QA
REV
Title C5416 DSP Starter Kit Size A Date:

3
SH
10
REV
Document Number 506002 Wednesday, March 20, 2002

2
Rev C Sheet 1
1
SH
of
14
3.3V L15 1 C88 U16 3.3V R54 1 E/D OUT GND CLKIN DGND 1 U21A BRD_RST# 1 TP 97 X2/CLKIN CLKMD1 CLKMD2 CLKMD3 MSC IAQ 1.6V C69 0.1uF C85 0.1uF C68 0.1uF C71 0.1uF C84 0.1uF C92 0.1uF MP/MC 26 29 TP3 TP4 77 78 79 32 BRD_SETUP0 BRD_SETUP1 BRD_SETUP2 BRD_SETUP3 DGND TP10 RS X1 CLKOUT TOUT 94 82 DSP_CLK DSP_TOUT R62 33 98 96 TP TP12 TP11 16.000MHz 2 3 R53 33 10K VDD 4 0.1uF 220pF DGND C87 Ferrite Chip TP TP13 12 16 52 68 91 125 142 CVdd CVdd CVdd CVdd CVdd CVdd CVdd DVdd DVdd DVdd DVdd DVdd DVdd 4 33 56 75 130 112 U21D
1.6V
3.3V
3.3V
RN3F RN3G RN3H RN3E
6 7 8 5
A A A A
B B B B
11 10 9 12
10K 10K 10K 10K
1 3 15 34 37 50 70 90 111 126 CVss CVss CVss CVss CVss CVss CVss CVss CVss CVss
DVss DVss DVss DVss DVss DVss DVss DVss DVss TMS320VC5416-PGE
14 40 57 72 76 93 106 128 144 DGND
JP4
2 4 6 8
1 3 5 7
C94 0.1uF
C
HEADER 4X2
DGND DSP_BIO# TP5 DSP_INT0# DSP_INT1# DSP_INT2# DSP_INT3# EMU1/OFF EMU0 TDO 85 84 83 3.3V XF IACK 27 61
DSP_XF DSP_IACK# 3.3V C86 0.1uF C83 0.1uF C93 0.1uF C67 0.1uF C70 0.1uF C73 0.1uF
31 63 64 65 66 67 BIO NMI INT0 INT1 INT2 INT3
DGND
3.3V TMS320VC5416-PGE
RN2A RN2B RN2C RN2D RN2E RN2F 1 2 3 4 5 6 A A A A A A B B B B B B TRST TMS TCK TDI 16 15 14 13 12 11 87 89 88 86 DSP_TRST# DSP_TMS DSP_TCK DSP_TDI DSP_TDO DSP_EMU0 DSP_EMU1
10K 10K 10K 10K 10K 10K
R60 4.7K
R61 4.7K
DGND
3.3V
RN3A RN3B RN3C RN3D USER_SW0 USER_SW1 USER_SW2 USER_SW3
1 2 3 4
A A A A
B B B B
16 15 14 13
10K 10K 10K 10K
USER OPTION DIP SWITCHES
8 7 6 5
S2 SW DIP-4
DGND
1 2 3 4
C5416 CONTROL & POWER

Title C5416 DSP Starter Kit Size B Date:
4 3 2
Document Number 506002 Wednesday, March 20, 2002 Sheet

1
Rev C 2 of 14
B-3
11 33
VDD1 VDD2
R30
10K DGND TC55V16256FT
VSS1 VSS2
12 34
B-4
4 3 2 1
FLASH
U7 VCC C43 0.1uF DGND 37
D
3.3V
3.3V
3.3V
C61 0.1uF DGND U13 4 2 R4 SN74LVC1G32 FLASH_CE# FLASH_OE# BRD_RST# DGND AM29LV400B DGND VSS VSS 27 46 10K NC1 NC2 NC3 33 10 13 14 3.3V R89 RY/BY 15
DSP_ADDR0 DSP_ADDR1 DSP_ADDR2 DSP_ADDR3 DSP_ADDR4 DSP_ADDR5 DSP_ADDR6 DSP_ADDR7 DSP_ADDR8 DSP_ADDR9 DSP_ADDR10 DSP_ADDR11 DSP_ADDR12 DSP_ADDR13 DSP_ADDR14 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15/A-1 29 31 33 35 38 40 42 44 30 32 34 36 39 41 43 45 DSP_DATA0 DSP_DATA1 DSP_DATA2 DSP_DATA3 DSP_DATA4 DSP_DATA5 DSP_DATA6 DSP_DATA7 DSP_DATA8 DSP_DATA9 DSP_DATA10 DSP_DATA11 DSP_DATA12 DSP_DATA13 DSP_DATA14 DSP_DATA15
FLASH_WE#
ADDR15 ADDR16 ADDR17 ADDR18 ADDR19
25 24 23 22 21 20 19 18 8 7 6 5 4 3 2 1 48 17 16 9 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19
DSP_MSTRB#
47 26 28 11 12 BYTE CE OE WE RESET
DSP_ADDR[0..22] DSP_DATA[0..15]
3.3V
EMIF
R59 10K U21B 30 HOLD HOLDA HP_HOLDA# 28 3.3V 3.3V
HP_HOLD#
ASRAM
U12 DGND C42 0.1uF C72 0.1uF
D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 PS DS IS R/W MSTRB IOSTRB R48 33
64Kx16 and 256Kx16 Compatible
99 100 101 102 103 104 113 114 115 116 117 118 119 121 122 123 20 21 22 23 DSP_PS# DSP_DS# DSP_IS# DSP_R/W# DSP_MSTRB# DSP_IOSTRB# SRAM_WE# SRAM_RE# ADDR15 ADDR16 ADDR17 24 25 DSP_ADDR0 DSP_ADDR1 DSP_ADDR2 DSP_ADDR3 DSP_ADDR4 DSP_ADDR5 DSP_ADDR6 DSP_ADDR7 DSP_ADDR8 DSP_ADDR9 DSP_ADDR10 DSP_ADDR11 DSP_ADDR12 DSP_ADDR13 DSP_ADDR14 1 2 3 4 5 18 19 20 21 24 25 26 27 42 43 44 22 23 A0 A1 A2 A3 A4 A5 A6 A7 A8 A11 A12 A13 A14 A15 A16 A17 A9 A10 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 NC 6 17 41 40 39 CS WE OE BHE BLE 7 8 9 10 13 14 15 16 29 30 31 32 35 36 37 38 28
DSP_ADDR0 DSP_ADDR1 DSP_ADDR2 DSP_ADDR3 DSP_ADDR4 DSP_ADDR5 DSP_ADDR6 DSP_ADDR7 DSP_ADDR8 DSP_ADDR9 DSP_ADDR10 DSP_ADDR11 DSP_ADDR12 DSP_ADDR13 DSP_ADDR14 DSP_ADDR15 DSP_ADDR16 DSP_ADDR17 DSP_ADDR18 DSP_ADDR19 DSP_ADDR20 DSP_ADDR21 DSP_ADDR22 131 132 133 134 136 137 138 139 140 141 5 7 8 9 10 11 105 107 108 109 110 143 2 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 READY TMS320VC5416-PGE 19
DSP_DATA0 DSP_DATA1 DSP_DATA2 DSP_DATA3 DSP_DATA4 DSP_DATA5 DSP_DATA6 DSP_DATA7 DSP_DATA8 DSP_DATA9 DSP_DATA10 DSP_DATA11 DSP_DATA12 DSP_DATA13 DSP_DATA14 DSP_DATA15
DSP_DATA0 DSP_DATA1 DSP_DATA2 DSP_DATA3 DSP_DATA4 DSP_DATA5 DSP_DATA6 DSP_DATA7 DSP_DATA8 DSP_DATA9 DSP_DATA10 DSP_DATA11 DSP_DATA12 DSP_DATA13 DSP_DATA14 DSP_DATA15
ADDR18
512K X 16 Compatible
DSP_RDY
3.3V
C5416 EMIF & ASRAM/FLASH

Title C5416 DSP Starter Kit DGND Size B Date:
3 2

1
Rev C 3 of 14

4
5V
C63 0.1uF U14 VCC 1A 2A 3A 4A GND DGND 5V DGND C64 0.1uF U15 VCC DGND ADDR19 1A 2A 3A 4A GND 8 DGND
B
16 4 ADDR15 ADDR16 ADDR17 ADDR18 7 9 12 8
DGND
DM_PG0 DSP_ADDR15 DM_PG1 DSP_ADDR16 DM_PG2 DSP_ADDR17 DM_PG3 DSP_ADDR18 1B1 1B2 2B1 2B2 3B1 3B2 4B1 4B2 S OE SN74CBT3257 DSP_DS# R57 33 1 15
2 3 5 6 11 10 14 13
16 4 7 9 12
DM_PG4 DSP_ADDR19 1B1 1B2 2B1 2B2 3B1 3B2 4B1 4B2 S OE SN74CBT3257
2 3 5 6 11 10 14 13 1 15 R50 33
DGND
MEMORY ADDRESSING
4 3 2

1
Rev C 4 of 14
B-5
B-6
4 3 2 1
DSP_DATA[0..15] BDSP_ADDR[0..22] 3.3V U5 42 31 Vcc Vcc 2 3 5 6 8 9 11 12 13 14 16 17 19 20 22 23 BDSP_DATA0 BDSP_DATA1 BDSP_DATA2 BDSP_DATA3 BDSP_DATA4 BDSP_DATA5 BDSP_DATA6 BDSP_DATA7 BDSP_DATA8 BDSP_DATA9 BDSP_DATA10 BDSP_DATA11 BDSP_DATA12 BDSP_DATA13 BDSP_DATA14 BDSP_DATA15 Vcc Vcc BDSP_ADDR0 BDSP_ADDR1 BDSP_ADDR2 BDSP_ADDR3 BDSP_ADDR4 BDSP_ADDR5 BDSP_ADDR6 BDSP_ADDR7 BDSP_ADDR8 BDSP_ADDR9 BDSP_ADDR10 BDSP_ADDR11 BDSP_ADDR12 BDSP_ADDR13 BDSP_ADDR14 BDSP_ADDR15 DSP_DATA0 DSP_DATA1 DSP_DATA2 DSP_DATA3 DSP_DATA4 DSP_DATA5 DSP_DATA6 DSP_DATA7 DSP_DATA8 DSP_DATA9 DSP_DATA10 DSP_DATA11 DSP_DATA12 DSP_DATA13 DSP_DATA14 DSP_DATA15 47 46 44 43 41 40 38 37 36 35 33 32 30 29 27 26 1A1 1A2 1A3 1A4 1A5 1A6 1A7 1A8 2A1 2A2 2A3 2A4 2A5 2A6 2A7 2A8 1B1 1B2 1B3 1B4 1B5 1B6 1B7 1B8 2B1 2B2 2B3 2B4 2B5 2B6 2B7 2B8 DSP_DATA_OE# DSP_DATA_DIR 1OE 1DIR 2OE 2DIR
C
BDSP_DATA[0..31]
DSP_ADDR[0..22] 3.3V U11 7 18

D
3.3V
3.3V
DSP_ADDR0 DSP_ADDR1 DSP_ADDR2 DSP_ADDR3 DSP_ADDR4 DSP_ADDR5 DSP_ADDR6 DSP_ADDR7 DSP_ADDR8 DSP_ADDR9 DSP_ADDR10 DSP_ADDR11 DSP_ADDR12 DSP_ADDR13 DSP_ADDR14
ADDR15
DC_CNTL_OE#
42 31 47 46 44 43 41 40 38 37 36 35 33 32 30 29 27 26 1 48 25 24 45 39 Vcc Vcc 1A1 1A2 1A3 1A4 2A1 2A2 2A3 2A4 3A1 3A2 3A3 3A4 4A1 4A2 4A3 4A4 1OE 2OE 3OE 4OE GND GND 48 1 25 24 SN74LVTH16244 DGND SN74LVTH16245 4 10 15 21 GND GND GND GND GND GND GND GND DGND DGND 28 34 39 45 Vcc Vcc 1Y1 1Y2 1Y3 1Y4 2Y1 2Y2 2Y3 2Y4 3Y1 3Y2 3Y3 3Y4 4Y1 4Y2 4Y3 4Y4 GND GND GND GND GND GND
7 18 2 3 5 6 8 9 11 12 13 14 16 17 19 20 22 23 4 10 15 21 28 34
DGND
3.3V U10
3.3V
ADDR16 ADDR17 ADDR18 ADDR19 DSP_ADDR20 DSP_ADDR21 DSP_ADDR22 3.3V 7 22 Vcc Vcc Vcc Vcc 50 35 U6 3.3V
BDSP_ADDR16 BDSP_ADDR17 BDSP_ADDR18 BDSP_ADDR19 BDSP_ADDR20 BDSP_ADDR21 BDSP_ADDR22
3.3V
DSP_XF DSP_TOUT DSP_CLK R47 R46 33 33
R2 1 TP TP14
10K
DC_RDY DC_BIO#
42 31 47 46 44 43 41 40 38 37 36 35 33 32 30 29 27 26 1 48 25 24 45 39 Vcc Vcc 1A1 1A2 1A3 1A4 2A1 2A2 2A3 2A4 3A1 3A2 3A3 3A4 4A1 4A2 4A3 4A4 1OE 2OE 3OE 4OE GND GND DC_XF DC_TOUT DC_CLK HP_CLK DSP_RDY DSP_BIO# SN74LVTH16244 BDSP_DATA0 BDSP_DATA1 BDSP_DATA2 BDSP_DATA3 BDSP_DATA4 BDSP_DATA5 BDSP_DATA6 BDSP_DATA7 BDSP_DATA8 BDSP_DATA9 BDSP_DATA10 BDSP_DATA11 BDSP_DATA12 BDSP_DATA13 BDSP_DATA14 BDSP_DATA15 5 6 8 9 10 12 13 14 15 16 17 19 20 21 23 24 1A1 1A2 1A3 1A4 1A5 1A6 1A7 1A8 2A1 2A2 2A3 2A4 2A5 2A6 2A7 2A8 3 26 2 27 1 28 1CEAB 2CEAB 1LEAB 2LEAB 1OEAB 2OEAB 1CEBA 2CEBA 1LEBA 2LEBA 1OEBA 2OEBA 1B1 1B2 1B3 1B4 1B5 1B6 1B7 1B8 2B1 2B2 2B3 2B4 2B5 2B6 2B7 2B8 DB_ABCE# DB_ABLE# DB_ABOE# DGND 52 51 49 48 47 45 44 43 42 41 40 38 37 36 34 33 54 31 55 30 56 29 Vcc Vcc 1Y1 1Y2 1Y3 1Y4 2Y1 2Y2 2Y3 2Y4 3Y1 3Y2 3Y3 3Y4 4Y1 4Y2 4Y3 4Y4 GND GND GND GND GND GND
7 18 2 3 5 6 8 9 11 12 13 14 16 17 19 20 22 23 4 10 15 21 28 34
BDSP_DATA16 BDSP_DATA17 BDSP_DATA18 BDSP_DATA19 BDSP_DATA20 BDSP_DATA21 BDSP_DATA22 BDSP_DATA23 BDSP_DATA24 BDSP_DATA25 BDSP_DATA26 BDSP_DATA27 BDSP_DATA28 BDSP_DATA29 BDSP_DATA30 BDSP_DATA31 DB_BACE# DB_BALE# DB_BAOE#
DGND
3.3V C60 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF C65 C39 C41 C62 C66 C38 DGND
4 11 18 25
GND GND GND GND
GND GND GND GND SN74LVTH16543
32 39 46 53 DGND
BUFFERS
3 2
C17
C36
C18
C40
C37
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
DGND

1
Rev C 5 of 14

4
3.3V DC_RE# B A B A B A B A B A 5 RN5E 4 RN5D 3 RN5C 5 RN1E 6 RN1F 3.3V 3.3V R70 10K U18 BRD_RST# BOARD_RESET 143 3.3V
Reset Button
R71 10K S1 3.3V R98 150 3.3V R97 150
11 10K DC_WE# 12 10K DC_OE# 14 10K FLASH_CE# 13 10K DSP_DATA_OE# 12 10K
USER LEDS
3.3V R96 150 3.3V R95 150
SW PUSHBUTTON DGND USB_DSP_RST# DC_RESET# MAN_RST# DC_RESET RESET_STROBE BSP2_SEL DB_MEM_SEL 83 106 BSP2_SEL BDSP_ADDR[0..22] 97 30 D12 Green
DC_DET# DB_P_RST# EMU_STS
16 134 133 14 15 BUTTON_RESET DC_DET DC_VCC_BAD EMU_SEL USB_DSP_RESET
VCCINT VCCINT VCCINT VCCINT VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO D11 Green
51 123 58 130 24 76 95 115 73 50 144
D10 Green
D9 Green USER_LED1# USER_LED2# USER_LED3# USER_LED4# TP6 TP7 TP8 TP9
BDSP_ADDR0 142 BDSP_ADDR1 137 BDSP_ADDR2 136 BDSP_ADDR14 141 BDSP_ADDR15 138 BDSP_ADDR22 31 DSP_ADDR0 DSP_ADDR1 DSP_ADDR2 DSP_ADDR14 DSP_ADDR15 DSP_ADDR22 DSP_DATA_DIR DSP_DATA_OE DB_BAOE DB_BALE DB_BACE DB_ABOE DB_ABLE DB_ABCE 71 42 55 56 44 39 41 37 DSP_DATA_DIR DSP_DATA_OE# DB_BAOE# DB_BALE# DB_BACE# DB_ABOE# DB_ABLE# DB_ABCE#
BDSP_DATA[0..31]
BDSP_DATA0 93 BDSP_DATA1 79 BDSP_DATA2 63 BDSP_DATA3 65 BDSP_DATA4 100 BDSP_DATA5 80 BDSP_DATA6 78 BDSP_DATA7 109 DSP_DATA0 DSP_DATA1 DSP_DATA2 DSP_DATA3 DSP_DATA4 DSP_DATA5 DSP_DATA6 DSP_DATA7
DM_PG0 DM_PG1 DM_PG2 DM_PG3 DM_PG4 DM_PAGE0 DM_PAGE1 DM_PAGE2 DM_PAGE3 DM_PAGE4 DC_RE# DC_WE# DC_OE#
98 82 72 68 91
DC_IO0 DC_IO1 DB_IO2 DC_IO3 DC_PS DC_M_STRB DC_IS DC_DS DC_IO_STRB
96 81 62 60 32 53 86 54 45 DC_STAT0 DC_STAT1 DC_CNTL0 DC_CNTL1 DC_PS# DC_MSTB# DC_IS# DC_DS# DC_IOSTRB#
3.3V
R67 10K R58 33 R49 33 FLASH_CE# FLASH_WE# FLASH_OE# SRAM_WE# SRAM_RE# PWB_VER0 PWB_VER1 PWB_VER2 DC_CNTL_OE# R80 33
R68 10K
R69 10K
DSP_PS# DSP_DS# DSP_IS# DSP_R/W# DSP_MSTRB# DSP_IOSTRB# DSP_PS DSP_DS DSP_IS DSP_RW DSP_M_STROBE DSP_IO_STROBE PWB_VER0 PWB_VER1 PWB_VER2 RSVD 119 102 5 6 USER_SW0 USER_SW1 USER_SW2 USER_SW3 USER_SWITCH0 USER_SWITCH1 USER_SWITCH2 USER_SWITCH3 USER_LED0 USER_LED1 USER_LED2 USER_LED3
11 10 140 139 9 128
DC_RE DC_WE DC_OE FLASH_CE FLASH_WE FLASH_OE MEM_WE MEM_RE
87 74 69 40 28 61 38 25
USER_LED1# USER_LED2# USER_LED3# USER_LED4# 3.3V 10K 11 10K 10 10K 9 B A B A B A 6 RN5F 7 RN5G 8 RN5H
8 132 131 18 101 88 67 70
R82 NO-POP
R83 33
3.3V
JP1 R103 100 ISR_TCK ISR_TMS ISR_TDI ISR_TD0 89 20 4 104
CODEC_CLK CODEC_BITCLK CODEC_FS CODEC_MC CODEC_MD CODEC_ML CODEC_CLK CODEC_BCLK CODEC_FS CODEC_MC CODEC_MD CODEC_ML CODEC_SYSCLK
125 111 29 116 7 117 107
DGND
CODEC_SYSCLK
1 2 3 4 5 6 7 8 9 10 TCK TMS TDI TDO c5416_ddb
R5
GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND
127 126 13 77 59 33 135 3 17 105 26 129 124 52 114 94 57 64 85 DGND 3.3V C58 0.1uF C80 0.1uF C78 0.1uF C77 0.1uF C76 0.1uF C89 0.1uF C79 0.1uF C59 0.1uF
HEADER 5x2
DGND
CPLD
Title C5416 DSP Starter Kit DGND Size B Date: Document Number 506002 Wednesday, March 20, 2002 Sheet 6 of 14 Rev C
B-7
B-8
4 3 2 1
3.3V_DB P1 P2
5V
12V#
12V
3.3V_DB
5V
BDSP_ADDR[0..22]
BDSP_ADDR19 BDSP_ADDR18 BDSP_ADDR17 BDSP_ADDR16 BDSP_ADDR15 BDSP_ADDR14 BDSP_ADDR13 BDSP_ADDR12

D
DC_A19 DC_A18 DC_A17 DC_A16 DC_A15 DC_A14 DC_A13 DC_A12 DC_A11 DC_A10 DC_A9 DC_A8 DC_A7 DC_A6 DC_A5 DC_A4 DC_BCLKX0 DC_BFSX0 DC_BDX0 DC_BCLKR0 DC_BFSR0 DC_BDR0 DC_BCLKX1 DC_BFSX1 DC_BDX1 5V 3 4 Vin Vin EN GND RESET TPS76733QD DGND DC_DET# 3.3V DB_P_RST# DGND DGND 8 C103 2 1 0.1uF U31 Vout Vout SENSE 5 6 7
+
BDSP_ADDR11 BDSP_ADDR10 BDSP_ADDR9 BDSP_ADDR8 BDSP_ADDR7 BDSP_ADDR6 BDSP_ADDR5 BDSP_ADDR4 DC_A3 DC_A2 DC_A1 DC_A0 DC_A21 DC_A20
BDSP_ADDR3 BDSP_ADDR2 BDSP_ADDR1 BDSP_ADDR0 BDSP_ADDR21 BDSP_ADDR20
3.3V DAUGHTERBOARD VOLTAGE

C
BDSP_DATA[0..31]
3.3V_DB
BDSP_DATA31 BDSP_DATA30 BDSP_DATA29 BDSP_DATA28 BDSP_DATA27 BDSP_DATA26 BDSP_DATA25 BDSP_DATA24 DC_D31 DC_D30 DC_D29 DC_D28 DC_D27 DC_D26 DC_D25 DC_D24 DC_BCLKR1 DC_BFSR1 DC_BDR1 DC_TOUT DC_INT1# DC_XF DC_BIO# DC_INT0# DC_IOSTRB# DC_RESET# DC_D23 DC_D22 DC_D21 DC_D20 DC_D19 DC_D18 DC_D17 DC_D16
CT17 10uF
BDSP_DATA23 BDSP_DATA22 BDSP_DATA21 BDSP_DATA20 BDSP_DATA19 BDSP_DATA18 BDSP_DATA17 BDSP_DATA16
BDSP_DATA15 BDSP_DATA14 BDSP_DATA13 BDSP_DATA12 BDSP_DATA11 BDSP_DATA10 BDSP_DATA9 BDSP_DATA8 DC_D15 DC_D14 DC_D13 DC_D12 DC_D11 DC_D10 DC_D9 DC_D8 DC_D7 DC_D6 DC_D5 DC_D4 DC_D3 DC_D2 DC_D1 DC_D0 DC_CNTL1 DC_CNTL0 DC_STAT1 DC_STAT0 DC_INT2# DC_INT3# DC_PS# DC_IS#
RN1A RN1B RN1C RN1D RN1G RN1H
1 2 3 4 7 8
A A A A A A
B B B B B B
16 15 14 13 10 9
10K 10K 10K 10K 10K 10K
DC_CNTL1 DC_CNTL0 DC_STAT1 DC_STAT0 DC_DET#
BDSP_DATA7 BDSP_DATA6 BDSP_DATA5 BDSP_DATA4 BDSP_DATA3 BDSP_DATA2 BDSP_DATA1 BDSP_DATA0
3.3V DC_DET# DC_CLK
R3
10K DC_RDY
DC_RE# DC_WE# DC_OE# DC_RDY DC_MSTB# DC_DS#
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80
Memory/Peripherals Header
SFM-140-L2-S-D-LC DGND

Title C5416 DSP Starter Kit Size B Date: Document Number 506002 Wednesday, March 20, 2002
3 2
Rev C Sheet
1
of
14

4
5V 3.3V_DB R51 NO-POP HP_BCLKX2 HP_BCLKR2 HP_BFSX2 HP_BFSR2 HP_BDX2 HP_BDR2 HPI_EN HPI16 R52 10K R63 33 HP_CLK
3.3V
P3
DGND
DGND
HRW HCNTL0 HAS# HCS# HCNTL1 HBIL HDS2 HDS1 3.3V R72 10K HPI_EN HPI16 92 80 HPIENA/Vdd HPI16 HR/W HCNTL0 HAS HCS HCNTL1 HBIL HDS2 HDS1 HRDY HINT BCLKR1 BFSR1 BDR1 BCLKX1 BFSX1 BDX1 BCLKR2 BFSR2 BDR2 BCLKX2 BFSX2 BDX2 42 44 47 49 54 60 38 36 35 71 73 74 HD0 HD1 HD2 HD3 HD4 HD5 HD6 HD7 TMS320VC5416-PGE BCLKR0 BFSR0 BDR0 BCLKX0 BFSX0 BDX0 41 43 45 48 53 59 U21C HRDY HINT# HPI16 HRW HCNTL0 HAS# HCS# HCNTL1 HBIL HDS2 HDS1 HRDY HINT# 18 39 13 17 46 62 129 127 55 51
DSP_BCLKR0 DSP_BFSR0 DSP_BDR0 DSP_BCLKX0 DSP_BFSX0 DSP_BDX0 DSP_BCLKR1 DSP_BFSR1 DSP_BDR1 DSP_BCLKX1 DSP_BFSX1 DSP_BDX1 DSP_BCLKR2 DSP_BFSR2 DSP_BDR2 DSP_BCLKX2 DSP_BFSX2 DSP_BDX2
HD[0..7]
HD0 HD1 HD2 HD3 HD4 HD5 HD6 HD7 58 69 81 95 120 124 135 6
HD7 HD6 HD5 HD4 HD3 HD2 HD1 HD0
HP_HOLDA# HP_HOLD# DSP_IACK# BRD_RST#
C5416 HPI I/F & McBSPs

4 3 2
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80

1
Rev C 8 of 14
B-9
1.6K
B-10
4 3 2 1
DSP McBSP0
4.1V_CBT1
U23 Vcc 3 4 7 8 11 1A1 1A2 1A3 1A4 1A5 4.1V_CBT1 C98 0.1uF U25 DC_BDX0 VCC 1A 2A 3A 4A GND SN74CBT3257 DGND 4.1V_CBT1 DGND S OE 1 15 DSP_BCLKR2 DSP_BCLKX2 DSP_BFSR2 DGND 8 DSP_BFSX2 12 9 7 4 DGND 16 CODEC_BITCLK HP_BCLKR2 14 17 18 21 22 2A1 2A2 2A3 2A4 2A5 2OE GND SN74CBTD3384 DGND 12 2 3 5 6 11 10 14 13 HP_BCLKX2 CODEC_FS HP_BFSR2 HP_BFSX2 1B1 1B2 2B1 2B2 3B1 3B2 4B1 4B2 2B1 2B2 2B3 2B4 2B5 13 15 16 19 20 23 1OE 1B1 1B2 1B3 1B4 1B5 DC_BCLKR0 DC_BFSR0 DC_BDR0 DC_BCLKX0 DC_BFSX0 1 2 5 6 9 10 24
C91 0.1uF
DSP McBSP2
DSP_BCLKR0 DSP_BFSR0 DSP_BDR0 DSP_BCLKX0 DSP_BFSX0
DSP_BDX0
C99 0.1uF
DSP McBSP1
DGND 16 VCC 1A 2A 3A 12 8 DGND BSP2_SEL 15 16 19 20 23 DC_BDX1 DC_INT0# DC_INT1# DC_INT2# DC_INT3# 12 DGND D5 LM4040DCIM3-4.1 4A GND 4 7 9 DSP_BDX2 DSP_BDR2 U27 Vcc 24 C100 0.1uF 4.1V_CBT1
U26 1B1 1B2 2B1 2B2 3B1 3B2 4B1 4B2 S OE SN74CBT3257 DGND 2 3 5 6 11 10 14 13 1 15
B
CODEC_DIN HP_BDX2 CODEC_DOUT HP_BDR2
DSP_BCLKR1 DSP_BFSR1 DSP_BDR1 DSP_BCLKX1 DSP_BFSX1 1A1 1A2 1A3 1A4 1A5 1OE 1B1 1B2 1B3 1B4 1B5 1 14 17 18 21 22 2A1 2A2 2A3 2A4 2A5 2OE GND SN74CBTD3384 2B1 2B2 2B3 2B4 2B5 13 DGND
3 4 7 8 11 DC_BCLKR1 DC_BFSR1 DC_BDR1 DC_BCLKX1 DC_BFSX1
2 5 6 9 10
DSP_BDX1 DSP_INT0# DSP_INT1# DSP_INT2# DSP_INT3#
CBT VOLTAGE DIVIDER

5V R94 4.1V_CBT1
DGND
McBSPS Buffers
3 2
Rev C Sheet
1
of
14

4
EXTERNAL POWER PLUG +3.3V & +1.6V DIGITAL VOLTAGE REGULATOR
USB-1.6V JP2 1 2
+
5V_IN U24 R90 JP3

+ + +
5V 0 CT14 47uF R78 33 3 1GND 2RESET 22 10uF 0.1uF 4 1EN 1OUT 1OUT 1FB/SENSE 23 24 25 CT15 C101 5 6 1IN 1IN 1RESET 28
5V
CT25 10uF
HEADER 2x1 1.6V

D
J6
3 2 1 DGND HEADER 2x1 0.1uF 11 12 2IN 2IN 2EN 2OUT 2OUT 2SENSE 2GND 10 R101 9 150 0.1uF D7 Green Power-On DGND C95 R79 33 17 18 19
+
DGND R66 R76 10.7K, 1% R77
0
+
RASM712 1 2 CT16 C102 47uF
SWITCHCRAFT RAPC712 PLUG
CT13 10uF 30.1K, 1% 3.3V DGND
12V#
12V
DGND
J5
+5 GND -12 +12 DGND DGND DGND 1 2 7 8 13 14 NC NC NC NC NC NC TPS767D301
4 3 2 1
CT11 10uF
CT12 47uF
DGND
4-pin Molex
ALTERNATE EXTERNAL POWER

5V
R104-R107, 1206 BODY
NC NC NC NC NC NC
15 16 20 21 26 27
DGND
C
(DO NOT POPULATE)
R246 0 PONRSn R247 0 R107 100 1.6V 5V R106 100 3.3V C105 0.1uF DGND R84 93.1K, 1% R104 100 U28 DGND 1 2 3 7 R92 732K, 1% R105 100 R81 1K 3 MMBD4148 MAN_RST# R249
OPTIONAL
DSP CORE & I/O DIFFERENTIAL VOLTAGE PROTECTION

1.6V
3.3V
VDD SENSE1 SENSE2 RESET SENSE3 RESET MR GND TPS3307-18D
8 6 5 4 DGND R102 1K
BRD_RST BRD_RST#
B
D1 1 MMBD4148 0 MMBD4148 3 1 3 1
D2
D3
D17 DGND DGND
MMBD4148
D8 Red Reset
DAUGHTERCARD STANDOFF GROUNDING

M1 125_PH M2 125_PH M3 125_PH M4 125_PH KEEP TRACES A MINIMUM OF 0.070 INCHES FROM THESE HOLES.
DGND
INPUT POWER
Title C5416 DSP Starter Kit DGND Size B Date: Document Number 506002 Wednesday, March 20, 2002 Sheet 10 of 14 Rev C
B-11
B-12
4 3 2 1
3.3V 3.3V J7 2 4 XDS_TRST# R91 1K

D
DSP JTAG HEADER
0 XDS_EMU1 4.1V_CBT3 TSW-107-14-G-D-006
XDS_TMS XDS_TDI XDS_TVD XDS_TDO XDS_TCK R99 XDS_EMU0 1 3 5 7 9 11 13 8 10 12 14
DGND
JTAG MULTIPLEXERS
0.1uF U29 VCC 1A 2A 3A 4A GND 8 DGND 12 9 7 DSP_TDI DSP_TCK DSP_TMS 4 DSP_TDO 16 DGND
C96
T_TDO T_TDI T_TCK T_TCK_RET T_TMS 1 15 S OE SN74CBT3257 R85 33 R65 0
XDS_TDO TBC_TDO XDS_TDI TBC_TDI XDS_TCK TBC_CLK XDS_TMS TBC_TMS 2 3 5 6 11 10 14 13 1B1 1B2 2B1 2B2 3B1 3B2 4B1 4B2
DGND
4.1V_CBT3
C97 3.3V U30 VCC 1A 2A 3A 4A NP

Not Installed
0.1uF
3.3V R100 150 16 4 7 9 12 1 15 S OE 8 GND SN74CBT3257 DGND DSP_EMU0 DSP_EMU1 DSP_TRST# D6 Green USB EMBEDDED EMU
B
T_EMU0 T_EMU1 T_TRSTn
XDS_EMU0 TBC_EMU0 XDS_EMU1 TBC_EMU1 XDS_TRST# TBC_TRST#
2 3 5 6 11 10 14 13
1B1 1B2 2B1 2B2 3B1 3B2 4B1 4B2
EMU_STS R86
EMU_STS BRD_RST
R87 33
DGND
DGND
CBT VOLTAGE DIVIDER

5V R93 1.6K 4.1V_CBT3
D4 LM4040DCIM3-4.1
Emulation Interface
Title C5416 DSP Starter Kit DGND Size B Date:
3 2

1
Rev C 11 of 14

4
Analog CODEC_SYSCLK CODEC_SYSCLK 5V 5V USB_1.6V 3.3V PONRSn PONRSn DGND DGND USB_DSP_RST# USB_DSP_RST# T_TCK_RET GND DGND USB/Emulation T_TCK_RET 5V 3.3V 5V BRD_RST# CODEC_CLK CODEC_BITCLK CODEC_FS CODEC_DIN CODEC_DOUT CODEC_MC CODEC_MD CODEC_ML Analog T_TRSTn T_TCK T_TMS T_TDI T_TDO T_EMU0 T_EMU1 USB/Emulation BRD_RST# CODEC_CLK CODEC_BITCLK CODEC_FS CODEC_DIN CODEC_DOUT CODEC_MC CODEC_MD CODEC_ML USB-1.6V
T_TRSTn T_TCK T_TMS T_TDI T_TDO T_EMU0 T_EMU1
DGND
Hierarcharical Blocks
4 3 2

1
Rev C 12 of 14
B-13
MIC IN
4
L1 C20 2 1 7 + TLV2444 R9 10K, 1% 5 TLV2444 VMID_AUDIO R37 6 10K, 1% + 3 AGND Ferrite Chip R8 10K, 1% C19 220pF AGND R34 C2 NU AGND R38 10K, 1% R16 10K, 1% 10K, 1% C48 47pF, NPO VMID_AUDIO 1uF R10 10K, 1% U2B U2A
Mic In
R108 0
11
11
B-14
4 3 2 1
3.3VA R6 1K C22 C47

+
47pF, NPO 47pF, NPO

D
R7 5.11K, 1% R35 3.3VA C21 AGND 0.1uF R33 200K 10K, 1%
CT2 10uF
R11
100K, 1%
J1
4 2 1
U3B C5 6 7 + TLV2444 C49 0.01uF AGND R39 10 VMID_AUDIO 10K, 1% R12 9 10K, 1% + TLV2444 5 R17 VMID_AUDIO 10K, 1% 1uF R14 10K, 1% U3C 8 R40 301, 1% LINE_MIC_IN_L
C7
LINE IN
LINE_IN_L C6 220pF R36 LINE_IN_R R19 3.3VA C23 U3A AGND 1 TLV2444 C8 2 + VMID_AUDIO 3 R18 AGND VMID_AUDIO 10K, 1% 1uF R20 10K, 1% 0.1uF 10K, 1% C9 220pF
NU L2
J2
Ferrite Chip L3
Line In
4 2 1
10K, 1%
C50 R41
47pF, NPO 10K, 1%
3.5 MM AUDIO JACK
R109 0
Ferrite Chip C10
NU
U3D R13 R15 10K, 1% 10K, 1% 13 12 + TLV2444 C51 0.01uF AGND 14 R42 301, 1% LINE_MIC_IN_R
AGND
3.3VA U2D U2C 9 8 VMID_AUDIO AGND + TLV2444 10 C45 0.1uF C46 1uF 13 12 + TLV2444 14 R32 10K, 1%
INSTALL FOR TABLE
TOP OPERATION
R31 10K, 1%
LINE IN & MIC IN

3 2
ASHIELD AGND
R1
AGND
Rev C Sheet
1
13
of
14

4
+5V & +5VA POWER

5V L8 3 4 Vin Vin
+
5VA C44
+ +
U1 CT7 47uF 2 EN 0.1uF RESET AGND AGND R21 100 1% Ferrite Chip L5 R26 100 1% Ferrite Chip C30 NU 8 NU L4 0.1uF 0.1uF 0.1uF C11 GND TPS77533D AGND 1 Vout Vout SENSE CT1 47uF CT9 10uF C1 C25 C52 C55 5 6 7
3.3VA
5V Ferrite Chip 0.01uF L9 Ferrite Chip DGND AGND
DGND
C12 NU LINE_L LINE_R
LINE OUT
J3 3 4 2 1 R110 3.5 MM AUDIO JACK C14 NU 0 Line Out
3.3V L13 3.3VA Ferrite Chip DGND 3.3VA R23 3.83K, 1% C27 220pF C32 0.1uF C54 AGND 1 OPA2340 U9 VDD R44 R29 C33 220pF U4B 10uF 6 5 C28 0.1uF AGND R45 30.1K, 1% AGND + OPA2340 C57 10pF C16 C35 NU NU R111 0
B
C53
0.1uF R43 30.1K, 1%
AGND
SPEAKER/HEADPHONE OUT
C
8
U4A
U8 R22 2 + 3 Vcom C26 2200pF 3.83K, 1% R24 15K, 1% 4 6 3 5 VrefL VinL VinR VrefR AVCC AVCC AVCC 1 2 24
10pF
AGND C34 NU 3.3VA 6 10K 1% 10K 1% 8 4 3 2 VinL VinR VoutL VoutR BYBASS GND SHTDWN 1 5 7 CT6
+
C15 NU J4 CT5
+
LINE_MIC_IN_L LINE_MIC_IN_R
68uF
L6 Ferrite Chip SPEAK_R 3
CT3 10uF VoutL VoutR Vcom

+ CT8
CT4 10uF 19 20 21 R28 3.83K, 1% R25 Vcom C31 2200pF AGND AGND 3.83K, 1% R27 15K, 1% Vcom C29 1uF C24 AGND 1uF AGND
3.3V
L14
AGND
68uF C56 1uF AGND 7 AGND TPA302 AGND
Ferrite Chip L7
4 SPEAK_L 2 1 Line Out

3.5 MM AUDIO JACK
C75 16 13 ZFLG DGND PCM3002E AGND AGND DGND 33 22 23
0.1
3.3V
Ferrite Chip
14 7 9 11 10 15 12 18 17 8 VDD RST SYSCLK BCLKIN LRCIN DIN DOUT MC MD ML
DGND
R55 10K
U17
VDD
E/D OUT
R56
GND
12.288MHz
DGND
CODEC_CLK
BRD_RST# CODEC_SYSCLK CODEC_BITCLK CODEC_FS CODEC_DIN CODEC_DOUT CODEC_MC CODEC_MD CODEC_ML
ASHIELD
AUDIO CODEC/OUTPUT
4 3 2

1
Rev C 14 of 14
B-15
B-16
Appendix C TMS320VC5416 DSK List of materials
This appendix contains the list of materials for the TMS320VC5416 DSK.
C-1

Table 1: TMS320VC5416 List of Materials
Item
1 2 3 4 5 6 7 8 9 10 11
Qty
1 1 1 1 1 1 1 1 2 1 2
Title
PWB,TMS320VC5416 USB DSK LOGIC,TMS320VC5416 USB DSK ASSY,EMBEDDED USB EMULATOR FPGA IC,PQFP,TMS320VC5416 PGE-160 IC,TSOP44,SRAM,64K x 16,12nS IC,TSOP48,FLASH,70nS IC,TSSOP48,3.3V,16-BIT TRANSCEIVER IC,TSSOP48,3.3V,16-BIT BUFFER/DRIVER IC,TSSOP56,3.3V,16-BIT TRANSCEIVER IC,TSSOP24,10-BIT FET BUS SWITCH,74CBTS3384 IC,MSOP8,OP AMP IC,QSOP16,QUAD 2:1 MULTIPLEXER / DEMULTIPLEXER IC,SSOP24,STEREO AUDIO CODEC IC,SO8,STEREO AUDIO POWER AMPLIFIER,300mW IC,TSSOP14,OP AMP, LOW VOLTAGE IC,SOIC,3.3V,1A LOWDROPOUT VOLTAGE REGULATOR,TPS76733 IC,SOIC,3.3V,500mA LOW-DROPOUT VOLTAGE REGULATOR,TPS77533 IC,SSOP28,DUAL LOWDROPOUT VOLTAGE REGULATOR IC,SO8,TRIPLE SUPERVISORY CIRCUIT,3.3V IC,SOT23-5,SINGLE CMOS OR GATE OSC,SMT,12.288 MHZ OSC,SMT,16 MHZ
Mfr Name
SPECTRUM DIGITAL, INC. SPECTRUM DIGITAL, INC. SPECTRUM DIGITAL, INC. ALTERA TEXAS INSTRUMENTS ISSI ADVANCED MICRO DEVICES, INC TEXAS INSTRUMENTS TEXAS INSTRUMENTS TEXAS INSTRUMENTS TEXAS INSTRUMENTS
PWB Ref #
Mfr P/N
U18 U21 U12 U7 U11 U5,U10 U6 U23,U27
EPM3128ATC144-10 TMS320VC5416PGE-160 IS61LV6416-12T AM29LV400BT-70EC SN74LVTH16245ADGGR SN74LVTH16244ADGGR SN74LVTH16543DGGR SN74CBTS3384PW
12 13
1 6
BURR-BROWN CORPORATION QUALITY SEMICONDUCTOR INC. BURR-BROWN CORPORATION TEXAS INSTRUMENTS
U4 U14,U15,U25,U26, U29,U30 U8 U9
OPA2340EA/250 QS3257Q
14 15
1 1
PCM3002E TPA302D
16 17
2 1
TEXAS INSTRUMENTS TEXAS INSTRUMENTS
U2,U3 U31
TLV2444CPWR TPS76733QD
18
TEXAS INSTRUMENTS
U1
TPS77533D
19
TEXAS INSTRUMENTS
U24
TPS767D301PWP
20 21 22 23
1 1 1 1
TEXAS INSTRUMENTS TEXAS INSTRUMENTS CTS ELECTRONICS CORPORATION CTS ELECTRONICS CORPORATION
U28 U13 U17 U16
TPS3307-18D SN74LVC1632DBBK CB3LV-3C-12.288T CB3LV-3C-16.000T
C-2

Item
24 25 26 27 28
Qty
2 4 1 6 12
Title
DIODE,SOT23, REFERENCE,4.1V DIODE,SOT23, SWITCHING LED,SMT 1206,YELLOW LED,SMT 1206,GREEN FERRITE BEAD,SMT 0805,600 OHMS CAP,CER,SMT 0603,10pF,50V, +/-.5pF,NPO CAP,CER,SMT 0603,47pF,50V, +/-5%,NPO CAP,CER,SMT 0603,2200pF,50V, +/-10%,X7R CAP,CER,SMT 0603,220pF,50V, +/-5%,NPO CAP,CER,SMT 0603,.01uF,50V, +/-10%,X7R CAP,CER,SMT 0603,.1uF,16V, +/-10%,X7R
Mfr Name
NATIONAL SEMICONDUCTOR ZETEX INC. LUMEX, INC. LITEON STEWARD
PWB Ref #
D4,D5 D1,D2,D3,D17 D8 D6,D7,D9,D10, D11,D12 L1,L2,L3,L4,L5,L6, L7,L8,L9,L13,L14, L15 C54,C57
Mfr P/N
LM4040CIM3-4.1 BAS16TA SML-LX1206YC-TR LTST-C150GKT HZ0805E601R-00
29
PANASONIC
ECU-V1H100DCV
30
PANASONIC
C22,C47,C48,C50
ECU-V1H470JCV
31
PANASONIC
C26,C31
ECUV1H222KBV
32
PANASONIC
C6,C9,C19,C27, C33,C87 C44,C49,C51,C104
ECU-V1H221JCV
33
AVX CORPORATION
06035C103KAT2A
34
63
PANASONIC
C1,C17,C18,C21, C23,C25,C28,C32, C36,C37,C38,C39, C40,C41,C42,C43, C45,C52,C53,C55, C58,C59,C60,C61, C62,C63,C64,C65, C66,C67,C68,C69, C70,C71,C72,C73, C74,C75,C76,C77, C78,C79,C80,C83, C84,C85,C86,C88, C89,C91,C92,C93, C94,C95,C96,C97, C98,C99,C100, C101,C102,C103, C105 C5,C8,C20,C24, C29,C46,C56 CT2,CT3,CT4,CT8, CT9,CT11,CT13, CT15,CT17,CT23, CT24,CT25 CT5,CT6 CT1,CT7,CT12, CT14,CT16 R104,R105,R106, R107 R21,R26,R103
ECJ-1VB1C104K
35
CAP,CER,SMT 0603,1uF,6.3V,X5R, +/-10% CAP,TANT,TEH SERIES,SMT 1206,10uF,6.3V CAP,TANT,SMT 2816,68uF,6.3V CAP,TANT,SMT 2816,47uF,10V RES,SMT,1206 120 OHM, 5%, 1/4 WATT RES,SMT 0603,100 OHM,1%,1/16 WATT
PANASONIC
ECJ-1VB0J105K
36
12
PANASONIC
ECS-TOJY106R
37 38 39 40
2 5 4 3
PANASONIC PANASONIC PANASONIC ROHM CORPORATION
ECS-T0JY106R ECS-T1AD476R ERJ-8GEYJ121V MCR03F1000EZP
C-3

Item
41
Qty
22
Title
RES,SMT 0603,10K OHM,1%,1/16 WATT
Mfr Name
PWB Ref #
R8,R9,R10,R12, R13,R14,R15,R16, R17,R18,R19,R20, R29,R31,R32,R34, R35,R36,R37,R38, R39,R41,R44 R11 R76 R43,R45 R40,R42 R22,R23,R25,R28 R77 R7 R24,R27 R92 R84 R5,R65,R86,R99, R108,R109,R110, R111 R6,R81,R91,R102 R2,R3,R4,R30, R51,R54,R55,R59, R67,R68,R69,R70, R71,R72 R93,R94 R95,R96,R97,R98, R100,R101 R46,R47,R48,R49, R50,R52,R53,R56, R57,R58,R62,R63, R78,R79,R82,R83, R85,R87,R89 R60,R61 R29,R44 R1,R66,R90 R33
Mfr P/N
RK73H1J1002F
KOA SPEER ELECTRONICS, INC.
42 43 44 45 46 47 48 49 50 51 52
1 1 2 2 4 1 1 2 1 1 8
RES,SMT 0603,100K OHM,1%,1/10 WATT RES,SMT 0603,10.7K OHM,1%,1/16 WATT RES,SMT 0603,200K OHM,1%,1/10 WATT RES,SMT 0603,301 OHM,1%,1/16 WATT RES,SMT 0603,3.83K OHM,1%,1/10 WAT RES,SMT 0603,30.1K OHM,1%,1/10 WATT RES,SMT 0603,5.11K OHM,1%,1/10 WATT RES,SMT 0603,15K OHM,1%,1/16 WAT RES,SMT 0603,732K OHM,1%,1/10 WATT RES,SMT 0603,93.1K OHM,1%,1/10 WATT RES,SMT 0603,0 OHM, 1/10 WATT RES,SMT 0603,1K OHM,5%,1/16 WATT RES,SMT 0603,10K OHM,5%,1/16 WATT
ROHM CORPORATION PANASONIC PANASONIC PANASONIC PANASONIC PANASONIC PANASONIC PANASONIC PANASONIC PANASONIC KOA SPEER ELECTRONICS, INC. KOA SPEER ELECTRONICS, INC. KOA SPEER ELECTRONICS, INC. PANASONIC PANASONIC KOA SPEER ELECTRONICS, INC.
MCR03F1003EZP ERJ-3EKF1072V ERJ-3EKF2003V ERJ-3EKF3010V ERJ-3EKF3831V ERJ-3EKF3012V ERJ-3EKF5111V ERJ-3EKF1502V ERJ-3EKF7323V ERJ-3EKF9312V RM73Z1J000
53 54
4 14
RM73B1JT102J RM73B1JT103J
55 56 57
2 6 19
RES,SMT 0603,1.6K OHM,5%,1/16 WATT RES,SMT 0603,150 OHM,5%,1/16 WATT RES,SMT 0603,33 OHM,5%,1/16 WATT
ERJ-3GEYJ162V ERJ-3GEYJ151V RM73B1JT33RJ
58 59 60 61
2 2 3 1
RES,SMT 0603,4.7K OHM,5%,1/16 WATT RES,SMT 0603,20K OHM,5%,1/16 WATT RES,SMT 1206,0 OHM, 1/8 WATT POT,SMT,5mm SQ.,200K,1/4 WATT, SINGLE TURN RES,NETWORK,SMT, 16 PIN,8 RES,10K OHM,5%,1/16 WATT
KOA SPEER ELECTRONICS, INC. KOA SPEER ELECTRONICS, INC. XICON PASSIVE COMPONENTS BOURNS CTS ELECTRONICS CORPORATION
RM73B1JT472J RM73B1JT203J 263-0 3314J-1-204
62
RN1,RN2,RN3, RN4,RN5
742163103J
C-4

Item
63
Qty
1
Title
SWITCH,SMT, PUSHBUTTON, MOMENTARY,.25 SQ. SWITCH,DIP,SMT, 4 POSITION HEADER,4 X 2, VERTICAL,PIN HEADER,5 X 2, VERTICAL,PIN HEADER,7 X 2, VERTICAL,PIN CONN,JACK,RIGHT ANGLE,POWER,2.5mm CONN,SMT, VERTICAL, RECEPTACLE,40X2 CONN,SMT,JACK, STEREO,4 POS.,3.6mm BUMPER, CYLINDRICAL,SELFSTICK,BLACK,.88 DIA.
Mfr Name
C&K/UNIMAX, INC. CTS ELECTRONICS CORPORATION SPECTRUM DIGITAL INC. SPECTRUM DIGITAL INC. SPECTRUM DIGITAL INC. SWITCHCRAFT
PWB Ref #
S1
Mfr P/N
KT11P2JM
64 65 66 67 68 69
1 1 1 1 1 3
S2 JP4 JP1 J7 J6 P1,P2,P3
193-MS
RASM712 104652-8
AMP INCORPORATED KYCON CABLE & CONNECTOR, INC. 3M ELECTRONIC PRODUCTS DIV. J1,J2,J3,J4 ST-3500-4N SJ-5009(BLACK)
70 71
4 4
C-5
C-6
Appendix D TMS320VC5416 DSK Mechanical Information
This appendix contains the mechanical information about the TMS320VC5416 DSK produced by Spectrum Digital.
D-1
D-2
THIS DRAWING IS NOT TO SCALE
Printed in U.S.A., March 2002 506005-0001 Rev. A

Manual Osciloscópio TMS320VC5416 PDF

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TMS320VC5416 DSK Technical Reference

DSP Development Systems

TMS320VC5416 DSK Technical Reference

506005-0001 Rev. A March 2002

Copyright 2002 Spectrum Digital, Inc.

1-2 1-2 1-3 2-1

Table 1: Hardware History Revision B C Beta Release Production Release History

Table 2: Manual History Revision A Beta Release History

Chapter 1 Introduction to the TMS320VC5416 DSK

Spectrum Digital, Inc

TMS320VC5416 DSK Module Technical Reference

Spectrum Digital, Inc

Embedded USB JTAG Controller

JTAG DATA SRAM 64K x 16 ADDRESS

McBSP Flash ROM 256K x 16 McBSP User Switch

McBSP HPI -IO

STEREO CODEC User LEDs DATA

Figure 1-1, BLOCK DIAGRAM, TMS320VC5416 DSK

Spectrum Digital, Inc

TMS320VC5416 DSK Module Technical Reference

Chapter 2 Operation of the TMS320VC5416 DSK

Spectrum Digital, Inc

TMS320VC5416 DSK Module Technical Reference

Spectrum Digital, Inc

Spectrum Digital, Inc

TMS320VC5416 DSK Module Technical Reference

Spectrum Digital, Inc

MP/MC OVLY MP/MC Pin R/W-0

DROM CLKOFF SMUL R/W-0 R/W-0 R/W-0

Spectrum Digital, Inc

TMS320VC5416 DSK Module Technical Reference

Spectrum Digital, Inc

Spectrum Digital, Inc

On-Chip (DARAM4-7 (MP/MC=0) External 01FFFF (MP/MC=1) Page 1 XPC=1

On-Chip (SARAM0-3 (MP/MC=0) External 02FFFF (MP/MC=1) Page 2 XPC=2

On-Chip (SARAM4-7 (MP/MC=0) External 03FFFF (MP/MC=1) Page 3 XPC=3

On-Chip DARAM0-3 (OVLY=1 External 7FFFFF (OVLY=0) 7F8000 External 7FFFFF

External 04FFFF Page 4 XPC=4

Page 127 XPC=7Fh

Figure 2-3, TMS320VC5416 DSK Program Space

TMS320VC5416 DSK Module Technical Reference

Spectrum Digital, Inc

Figure 2-4, TMS320VC5416 DSK Data Space

Spectrum Digital, Inc

Figure 2-5, TMS320C5416 I/O Space

TMS320VC5416 DSK Module Technical Reference

Spectrum Digital, Inc

Note: R indicates Read Only, R/W indicate Read and Writable

Spectrum Digital, Inc

TMS320VC5416 DSK Module Technical Reference

Spectrum Digital, Inc

Spectrum Digital, Inc

TMS320VC5416 DSK Module Technical Reference

Spectrum Digital, Inc

Descriptions appearing in bold are defaults.

Spectrum Digital, Inc

TMS320VC5416 DSK Module Technical Reference

Spectrum Digital, Inc

Spectrum Digital, Inc

TMS320VC5416 DSK Module Technical Reference

Spectrum Digital, Inc

Spectrum Digital, Inc