Lecture 6

8.
1 Basic Design Steps of Synchronous Sequential Circuits

Finite State Machines (FSMs) State Diagram State Table State Assignment
TNE027 Digital Communication Electronics, Lecture 6
Moore Type: The outputs depend only on the state of the circuit. Mealy Type: The outputs depend on both the state and the primary inputs of the circuit.
Combinational circuit
Flip-flops
Combinational circuit
Clock
Figure 8.1
The general form of a sequential circuit

TNE027 Digital Communication Electronics, Lecture 6 2
Moore State Diagram

Reset
Z
Z
= 1 Bz = 0
= 0
Az = 0
Z
= 0
Z
= 0
= 1
Cz = 1
= 1
Figure 8.3
State diagram of a simple sequential circuit

Moore State Table
Present state A B C
Next state
Z= 0
A A A
Z= 1
B C C
Output ] 0 0 1
Figure 8.4
State table
4
Moore State Assignment
Present state \ \ 2 1 A B C 00 01 10 11
Next state Z = 0 < < 2 1 00 00 00 GG Z = 1 < < 2 1 01 10 10 GG Output ] 0 0 1 G
Figure 8.6
A State-assigned table
5
\ \
2 1 00 01 0 0 11 d d 10 0
<
Ignoring dont cares
Using dont cares
0 1
0 1
Z\
1 2
<
Z\
1 2
\ \ Z
2 1 00 01 0 1 11 d d 10 0
<
0 1
0 0
Z\
1 2
Z\
1 2
<
= =
Z\ Z
+ Z\ 1 2 ( \ + \ ) 1 2
\ \
1 0 1 0
]
2 0 1
0 1
\ \
1 2
Figure 8.7 Derivation of logic expressions TNE027 Digital Communication Electronics, Lecture 6
<
2
]
Q Q
< Z
Q Q
&ORFN 5HVHWQ
Figure 8.8 Sequential circuit TNE027 Digital Communication Electronics, Lecture 6
Alternative State Assignment
Present state y2 y1 A B C 00 01 11 10
Next state w= 0 Y 2 Y1 00 00 00 dd w= 1 Y2 Y1 01 11 11 dd Output z 0 0 1 d
Figure 8.16
Improved state assignment

8
<
\ 2
Q Q
< 1 Z
\ 1
Q Q
&ORFN
5HVHWQ
Figure 8.17
Final circuit for the improved state assignment

One-Hot State Assignment
Present state \3\2\1 A B C 001 010 100
Nextstate Z= 0 <3 <2 <1 001 001 001 Z= 1 <3 < 2 <1 010 100 100 Output ] 0 0 1
Figure 8.20
One-hot state assignment

10
Mealy State Diagram
Reset
Z
= 1 ] = 0 B = 0 ] = 0
Z
= 0 ] = 0
= 1 ] = 1
Figure 8.23
State diagram
11
Mealy State Table
Present state A B
Next state Z= 0 A A Z= 1 B B
Output ] Z= 0 0 0 Z= 1 0 1
Figure 8.24
State table
12
Mealy State Assignment

Present state \ A B 0 1 Next state Z= 0 < 0 0 Z= 1 < 1 1 ] 0 0 Output Z= 0 Z= 1 ] 0 1
Figure 8.25
State-assigned table
13
Q
Q
&ORFN
5HVHWQ
(a) Circuit
W &ORFN
10
1 0 1 0 1 0 1 0 (b) Timing diagram Figure 8.26 FSM implementation TNE027 Digital Communication Electronics, Lecture 6 14
8.4 Design of Finite State Machines using CAD Tools

Draw state diagrams using a graphical tool VHDL code for Moore-type FSMs Two styles of code Specifying the state assignment in VHDL code Specification of Mealy FSMs using VHDL
VHDL code for Moore-type FSMs

USE ieee.std_logic_1164.all ; ENTITY simple IS PORT ( Clock, Resetn, w z END simple ; : IN STD_LOGIC ; : OUT STD_LOGIC ) ;
ARCHITECTURE Behavior OF simple IS TYPE State_type IS (A, B, C) ; TYPE SIGNAL y : State_type ; BEGIN Create a user-defined PROCESS ( Resetn, Clock ) BEGIN signal type IF Resetn = 0 THEN y <= A ; ELSIF (ClockEVENT AND Clock = 1) THEN cont ...
Figure 8.29a
VHDL code for a simple FSM

16
CASE y IS WHEN A => IF w = 0 THEN y <= A ; ELSE y <= B ; END IF ; WHEN B => IF w = 0 THEN y <= A ; ELSE y <= C ; END IF ; WHEN C => IF w = 0 THEN y <= A ; ELSE y <= C ; END IF ; END CASE ; END IF ; END PROCESS ; z <= 1 WHEN y = C ELSE 0 ; END Behavior ;
Figure 8.29b VHDL code for a simple FSM (cont) 17
(ENTITY declaration not shown) ARCHITECTURE Behavior OF simple IS TYPE State_type IS (A, B, C) ; SIGNAL y_present, y_next : State_type ; BEGIN PROCESS ( w, y_present ) BEGIN CASE y_present IS WHEN A => IF w = '0' THEN y_next <= A ; ELSE y_next <= B ; END IF ; WHEN B => IF w = '0' THEN y_next <= A ; ELSE y_next <= C ; END IF ;
An alternative style of VHDL code for FSMs: The first process describes the state table as a combnational circuit. The second process introduces flipflops into the circuit.
SIGNAL y_present, y_next: State_type;

Figure 8.33a Alternative style of code for an FSM 18
WHEN C => IF w = 0 THEN y_next <= A ; ELSE y_next <= C ; END IF ; END CASE ; END PROCESS ; PROCESS (Clock, Resetn) BEGIN IF Resetn = 0 THEN y_present <= A ; ELSIF (ClockEVENT AND Clock = 1) THEN y_present <= y_next ; END IF ; END PROCESS ; z <= 1 WHEN y_present = C ELSE 0 ; END Behavior ;
Figure 8.33b
Alternative style of code for an FSM (cont)

Manual State Assignment

There is no standardized way. For Alteras MAX +plusII, the attribute feature is used. The user-defined attribute can be used to associate some desired type of information with an object in VHDL code.
(ENTITY declaration not shown) ARCHITECTURE Behavior OF simple IS TYPE State_TYPE IS (A, B, C) ; ATTRIBUTE ENUM_ENCODING ATTRIBUTE ENUM_ENCODING OF State_type SIGNAL y_present, y_next : State_type ; BEGIN ...
Figure 8.34
: STRING ; : TYPE IS "00 01 11" ;
The ENUM_ENCODING attribute is specific to MAX+plusII.

A user-defined attribute for manual state assignment
10
LIBRARY ieee ;
USE ieee.std_logic_1164.all ; ENTITY simple IS PORT ( Clock, Resetn, w z END simple ;
Using constants for manual state assignment

: IN STD_LOGIC ; : OUT STD_LOGIC ) ;
CONSTANT declaration
ARCHITECTURE Behavior OF simple IS SIGNAL y_present, y_next : STD_LOGIC_VECTOR(1 DOWNTO 0); CONSTANT A : STD_LOGIC_VECTOR(1 DOWNTO 0) := "00" ; CONSTANT B : STD_LOGIC_VECTOR(1 DOWNTO 0) := "01" ; CONSTANT C : STD_LOGIC_VECTOR(1 DOWNTO 0) := "11" ; BEGIN PROCESS ( w, y_present ) This code works with BEGIN any CAD systems. CASE y_present IS WHEN A => IF w = 0 THEN y_next <= A ; ELSE y_next <= B ; END IF ; cont
Figure 8.35a
Using constants for manual state assignment

21
WHEN B => IF w = 0 THEN y_next <= A ; ELSE y_next <= C ; END IF ; WHEN C => IF w = 0 THEN y_next <= A ; ELSE y_next <= C ; WHEN OTHERS => END IF ; WHEN OTHERS => y_next <=A; y_next <= A ; END CASE ; This is required because END PROCESS ; PROCESS ( Clock, Resetn ) unused state, i.e., BEGIN y_present = 10. IF Resetn = 0 THEN y_present <= A ; ELSIF (ClockEVENT AND Clock = 1) THEN y_present <= y_next ; END IF ; Figure 8.35b Using END PROCESS ; constants for manual z <= 1 WHEN y_present = C ELSE 0 ; state assignment (cont) END Behavior ;
the FSM might enter the
22
11
LIBRARY ieee ; USE ieee.std_logic_1164.all ; ENTITY mealy IS PORT ( Clock, Resetn, w z END mealy ;
Specification of Mealy FSMs

: IN STD_LOGIC ; : OUT STD_LOGIC ) ;
ARCHITECTURE Behavior OF mealy IS TYPE State_type IS (A, B) ; SIGNAL y : State_type ; BEGIN PROCESS ( Resetn, Clock ) BEGIN IF Resetn = 0 THEN y <= A ; ELSIF (ClockEVENT AND Clock = 1) THEN CASE y IS WHEN A => IF w = 0 THEN y <= A ; ELSE y <= B ; END IF ; cont
Figure 8.36 VHDL code for a Mealy TNE027 Digital Communication Electronics, Lecture 6
machine
23
WHEN B => IF w = 0 THEN y <= A ; ELSE y <= B ; END IF ; END CASE ; END IF ; END PROCESS ; PROCESS ( y, w ) BEGIN CASE y IS WHEN A => z <= 0 ; WHEN B => z <= w ; END CASE ; END PROCESS ; END Behavior ;
Figure 8.36b
Combinational circuit for the output The output signal z depends on both the state and the primary input.
VHDL code for a Mealy machine (cont)

12
8.5 Serial Adder Example

$ D
Shift register Adder FSM Shift register

E
Shift register
Sum = A + B
% &ORFN
Figure 8.39
Block diagram of a serial adder

State diagram for the Mealy-type serial adder FSM

Reset
( DE V)
11 0 00 0 01 1 10 1 01 0 10 0 11 1
G 00 1 G: carry-in = 0 H: carry-in = 1
Figure 8.40
State diagram for the serial adder

13
D E
Full adder
V < FDUU\RXW &ORFN 5HVHW D Q Q \
Figure 8.43
Circuit for the adder FSM

27
State diagram for the Moore-type serial adder FSM

Reset
00
G0 V = 0 00 00
11
H0 V = 0
01 10
01 10
11
11
01 10
01 10
G1 V = 1
00
H1 V = 1
11
Figure 8.44
State diagram for the Moore-type serial adder FSM

14
6XPELW
<
1
V
D
E
Full adder
&DUU\RXW
<
D
&ORFN
5HVHW
Figure 8.47
Circuit for the Moore-type serial adder FSM

8-bit serial adder

D 7 D 0
1 0 0 0 D3 D 2 D1 D 0 L E Counter Q3 Q2 Q 1 Q0
0 1
L w E
E 7
E 0
Adder FSM
5XQ
0 1
L w E
0 L w E
&ORFN 5HVHW 6XP 6XP
Figure 8.50a
Synthesized serial adder

30
15
LIBRARY ieee ; USE ieee.std_logic_1164.all ; -- left-to-right shift register with parallel load and enable ENTITY shiftrne IS GENERIC ( N : INTEGER := 4 ) ; PORT ( R : IN STD_LOGIC_VECTOR(N-1 DOWNTO 0) ; L, E, w : IN STD_LOGIC ; Clock : IN STD_LOGIC ; Q : BUFFER STD_LOGIC_VECTOR(N-1 DOWNTO 0) ) ; END shiftrne ; ARCHITECTURE Behavior OF shiftrne IS BEGIN PROCESS BEGIN cont
Figure 8.48a
Code for a left-to-right shift register with an enable input

WAIT UNTIL Clock'EVENT AND Clock = '1' ; IF E = '1' THEN IF L = '1' THEN Q <= R ; ELSE Genbits: FOR i IN 0 TO N-2 LOOP Q(i) <= Q(i+1) ; END LOOP ; Q(N-1) <= w ; END IF ; END IF ; END PROCESS ; END Behavior ;
Figure 8.48b
Code for a left-to-right shift register with an enable input (cont)

16
LIBRARY ieee ; USE ieee.std_logic_1164.all ; ENTITY serial IS GENERIC ( length : INTEGER := 8 ) ; PORT ( Clock : IN STD_LOGIC ; Reset : IN STD_LOGIC ; A, B : IN STD_LOGIC_VECTOR(length-1 DOWNTO 0) ; Sum : BUFFER STD_LOGIC_VECTOR(length-1 DOWNTO 0) ); END serial ; ARCHITECTURE Behavior OF serial IS COMPONENT shiftrne GENERIC ( N : INTEGER := 4 ) ; PORT ( R : IN STD_LOGIC_VECTOR(N-1 DOWNTO 0) ; L, E, w : IN STD_LOGIC ; Clock : IN STD_LOGIC ; Q : BUFFER STD_LOGIC_VECTOR(N-1 DOWNTO 0) ) ; END COMPONENT ; SIGNAL QA, QB, Null_in : STD_LOGIC_VECTOR(length-1 DOWNTO 0) ; SIGNAL s, Low, High, Run : STD_LOGIC ; SIGNAL Count : INTEGER RANGE 0 TO length ; TYPE State_type IS (G, H) ; SIGNAL y : State_type ;
Figure 8.49a
VHDL code for the serial adder
cont
BEGIN Low <= 0 ; High <= 1 ; ShiftA: shiftrne GENERIC MAP (N => length) PORT MAP ( A, Reset, High, Low, Clock, QA ) ; ShiftB: shiftrne GENERIC MAP (N => length) PORT MAP ( B, Reset, High, Low, Clock, QB ) ; AdderFSM: PROCESS ( Reset, Clock ) BEGIN Serial adder IF Reset = 1 THEN y <= G ; ELSIF ClockEVENT AND Clock = 1 THEN CASE y IS WHEN G => IF QA(0) = 1 AND QB(0) = 1 THEN y <= H ; ELSE y <= G ; END IF ; WHEN H => IF QA(0) = 0 AND QB(0) = 0 THEN y <= G ; ELSE y <= H ; END IF ; END CASE ; END IF ; Figure 8.49b VHDL code for END PROCESS AdderFSM ;
the serial adder (cont)
cont
17
WITH y SELECT s <= QA(0) XOR QB(0) WHEN G, NOT ( QA(0) XOR QB(0) ) WHEN H ; Null_in <= (OTHERS => 0) ; ShiftSum: shiftrne GENERIC MAP ( N => length ) PORT MAP ( Null_in, Reset, Run, s, Clock, Sum ) ; Stop: PROCESS BEGIN WAIT UNTIL (ClockEVENT AND Clock = 1) ; IF Reset = 1 THEN Count <= length ; Down counter ELSIF Run = 1 THEN Count <= Count -1 ; END IF ; END PROCESS ; Run <= 0 WHEN Count = 0 ELSE 1 ; -- stops counter and ShiftSum END Behavior ;
Figure 8.49c
VHDL code for the serial adder (cont)

Serial/parallel multiplier using carry-save adders

Multiplier Bn-1 Bn-2 ...B0 Bn-1 Bn-2 ...B0 shift & An-1 & ... An-2 Multiplicant An-1 An-2 ...A0 ... & A0
FA D
FA D
FA D
36
18
Serial/parallel multiplier with fixed coefficients

Multiplicant A4 A3 A2 A1A0 = 01011 Bn-1 Bn-2 ...B0 shift 0 1 0 1 1
FA D
FA D
37
8.10 Algorithmic State Machine (ASM) Charts

State Box Decision Box Conditional Output Box ASM chart implied timing information (Section 10.2.2)
38
19
State name Output signals or actions (Moore type) 0 (False) Condition expression 1 (True)
(a) State box
(b) Decision box
Conditional outputs or actions (Mealy type)
(c) Conditional output box

Figure 8.86 Elements used in ASM TNE027 Digital Communication Electronics, Lecture 6
charts
39
Reset
1 B
1 C
]
Figure 8.87 ASM chart for a simple FSM

40
20
Reset
0
Z
B
]
0
Z
Figure 8.88
ASM chart for the FSM in Figure 8.23

41
Bit counter
S1 Load A
Reset
Pseudo code
% = 0; while $ 0 do if D 0 = 1 then % = % + 1; End if; Right-shift $ ; End while;
B 0 0 0 s 1 S2 Shift right A S3 Done s 1
ASM block for state S2
B B + 1
A = 0? 0 0
In state S2, all the decisions for changing the state and operations to be performed are made ready by the combinational circuit. The changes only occur on the next clock edge.
counter
42
Figure 10.10 ASM chart for the bit TNE027 Digital Communication Electronics, Lecture 6
21
Figure 10.14
Simulation results for the bit-counting circuit
43
Data path for the bit counter

Data
Q
0
log2Q
0 LA EA Clock
w L E
Shift
LB EB
L E
Counter
A
Q
log2Q
Figure 10.11
Data path for the bit counter

44
22
ASM chart for the bit counter control circuit

S1
Reset
LB , EB EA 0 1 LA 0 s 1 S2 EA S3 Done 0 s 1
1 EB
]
0 0
Figure 10.12
ASM chart for the bit counter control circuit

LIBRARY ieee ; USE ieee.std_logic_1164.all ; LIBRARY work ; USE work.components.shiftrne ; ENTITY bitcount IS PORT( Clock, Resetn LA, s Data B Done END bitcount ;
: IN : IN : IN : BUFFER : OUT
STD_LOGIC ; STD_LOGIC ; STD_LOGIC_VECTOR(7 DOWNTO 0) ; INTEGER RANGE 0 to 8 ; STD_LOGIC ) ;
ARCHITECTURE Behavior OF bitcount IS TYPE State_type IS ( S1, S2, S3 ) ; SIGNAL y : State_type ; SIGNAL A : STD_LOGIC_VECTOR(7 DOWNTO 0) ; SIGNAL z, EA, LB, EB, low : STD_LOGIC ; BEGIN FSM_transitions: PROCESS ( Resetn, Clock ) BEGIN Figure 10.13a VHDL code for the bitIF Resetn = 0 THEN y <= S1 ; counting circuit
cont TNE027 Digital Communication Electronics, Lecture 6 46
23
ELSIF (ClockEVENT AND Clock = 1) THEN CASE y IS WHEN S1 => IF s = 0 THEN y <= S1 ; ELSE y <= S2 ; END IF ; WHEN S2 => IF z = 0 THEN y <= S2 ; ELSE y <= S3 ; END IF ; WHEN S3 => IF s = 1 THEN y <= S3 ; ELSE y <= S1 ; END IF ; END CASE ; END IF ; Figure 10.13b VHDL code for END PROCESS ; the bit-counting circuit (cont) FSM_outputs: PROCESS ( y, s, A(0), z ) BEGIN EA <= 0 ; LB <= 0 ; EB <= 0 ; Done <= 0 ; CASE y IS WHEN S1 => LB <= 1 ; EB <= 1 ; IF s = 0 AND LA = 1 THEN EA <= 1 ; ELSE EA <= 0 ; END IF ; WHEN S2 => EA <= 1 ; IF A(0) = 1 THEN EB <= 1 ; ELSE EB <= 0 ; END IF ;
cont TNE027 Digital Communication Electronics, Lecture 6 47
WHEN S3 => Done <= 1 ; END CASE ; END PROCESS ; -- The datapath circuit is described below upcount: PROCESS ( Resetn, Clock ) BEGIN IF Resetn = 0 THEN B <= 0 ; ELSIF (ClockEVENT AND Clock = 1) THEN IF EB = 1 THEN IF LB = 1 THEN B <= 0 ; ELSE B <= B + 1 ; END IF ; END IF ; END IF; Figure 10.13c VHDL code for the END PROCESS; bit-counting circuit (cont) low <= 0 ; ShiftA: shiftrne GENERIC MAP ( N => 8 ) PORT MAP ( Data, LA, EA, low, Clock, A ) ; z <= 1 WHEN A = "00000000" ELSE 0 ; END Behavior ;
24

Lecture 6

Загружено:

Сведения о документе

Авторское право

Доступные форматы

Поделиться этим документом

Поделиться или встроить документ

Параметры публикации

Этот документ был вам полезен?

Это неприемлемый материал?

Авторское право:

Доступные форматы

Lecture 6

Загружено:

Авторское право:

Доступные форматы

8.

1 Basic Design Steps of Synchronous Sequential Circuits

TNE027 Digital Communication Electronics, Lecture 6

The general form of a sequential circuit

Moore State Diagram

State diagram of a simple sequential circuit

Moore State Table

TNE027 Digital Communication Electronics, Lecture 6

Moore State Assignment

Next state Z = 0 < < 2 1 00 00 00 GG Z = 1 < < 2 1 01 10 10 GG Output ] 0 0 1 G

TNE027 Digital Communication Electronics, Lecture 6

Ignoring dont cares

Using dont cares

Figure 8.8 Sequential circuit TNE027 Digital Communication Electronics, Lecture 6

Alternative State Assignment

Next state w= 0 Y 2 Y1 00 00 00 dd w= 1 Y2 Y1 01 11 11 dd Output z 0 0 1 d

Improved state assignment

TNE027 Digital Communication Electronics, Lecture 6

Final circuit for the improved state assignment

One-Hot State Assignment

Present state \3\2\1 A B C 001 010 100

One-hot state assignment

TNE027 Digital Communication Electronics, Lecture 6

Mealy State Diagram

TNE027 Digital Communication Electronics, Lecture 6

Mealy State Table

TNE027 Digital Communication Electronics, Lecture 6

Mealy State Assignment

TNE027 Digital Communication Electronics, Lecture 6

8.4 Design of Finite State Machines using CAD Tools

VHDL code for Moore-type FSMs

VHDL code for a simple FSM

TNE027 Digital Communication Electronics, Lecture 6

Figure 8.29b VHDL code for a simple FSM (cont) 17

SIGNAL y_present, y_next: State_type;

TNE027 Digital Communication Electronics, Lecture 6

Alternative style of code for an FSM (cont)

Manual State Assignment

: STRING ; : TYPE IS "00 01 11" ;

The ENUM_ENCODING attribute is specific to MAX+plusII.

Using constants for manual state assignment

Using constants for manual state assignment

TNE027 Digital Communication Electronics, Lecture 6

the FSM might enter the

Specification of Mealy FSMs

VHDL code for a Mealy machine (cont)

8.5 Serial Adder Example

Shift register Adder FSM Shift register

Block diagram of a serial adder

State diagram for the Mealy-type serial adder FSM

State diagram for the serial adder

V < FDUU\RXW &ORFN 5HVHW D Q Q \

Circuit for the adder FSM

TNE027 Digital Communication Electronics, Lecture 6

State diagram for the Moore-type serial adder FSM

State diagram for the Moore-type serial adder FSM

Circuit for the Moore-type serial adder FSM

8-bit serial adder

&ORFN 5HVHW 6XP  6XP 

Synthesized serial adder

TNE027 Digital Communication Electronics, Lecture 6

Code for a left-to-right shift register with an enable input

Code for a left-to-right shift register with an enable input (cont)

VHDL code for the serial adder

V < FDUU\RXW &ORFN 5HVHW D Q Q \

&ORFN 5HVHW 6XP 6XP