Y. C.

Lemard

COMPUTER SCIENCE - UNIT ONE MODULE 1 - COMPUTER ORGANISATION

THE PROCESSOR
It has several subunits but we are concerned principally with the Control unit Arithmetic logic unit and Registers

Components
Control Unit - Se uentially accesses and decodes program instructions - Coordinates the !low o! data in and out o! the ALU" registers" RA#" storage and input and output devices. Arithmetic$Logic Unit - per!orms mathematical operations - ma%es logical comparisons - stores current data $ results Registers - a small number o! very high speed special-purpose memory units !ound in the C&U capable o! temporarily storing a single piece o! data$instruction$address. 'he register holds one unit o! program instruction or data" immediately be!ore or during processing by the C&U. So the register is the storage unit inside the processor. 'he register is where the data is actually stored while it is being processed. Registers are speciali(ed to )ust one tas% i.e. a particular register stores )ust one piece o! data. *+amples o! registers , #emory data register #-R . stores the current piece o! data #emory address register #AR . stores the address o! the place o! memory to loo% !or the ne+t item o! data needed Instruction register $ program counter &C . stores the current statement in the program being e+ecuted.
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Accumulator - stores the results o! calculations 0in the ALU1

&rocessors are di!!erentiated by ,/. their instruction set , the set o! basic instructions that a particular microprocessor can understand and e+ecute. &rocessors can be CISC or RISC. CISC . comple+ instruction set computer , the instructions are comple+ i.e. a single instruction results in several operations being done by the processor e.g. #UL' . load the data into the register !rom memory" multiply them and place the result bac% into the appropriate register. 'his is at least three steps but it is accomplished by one instruction %nown to the processor. CISC computers use less memory space and are slower to e+ecute" but they can carryout more comple+ operations without the intervention o! so!tware. RISC . reduced instruction set , this is a newer approach in which every instruction is a simple one step operation. A RISC processor would not recogni(e #UL'. It is more li%ely to have L2A-" &R2-" and S'2R* which is used to per!orm the same multiplication. 'he set o! instructions is there!ore simpler" barer" more basic. RISC processors are !aster but memory gets !illed up easier. 'he operating system has a heavier wor%load in a RISC machine.

3.

instruction types 'here are generally three types o! instructions , - -ata manipulation . these include o Arithmetic operations such as add" subtract" multiply" divide" increment and decrement o Logical operations such as A4-" 2R" 42' and 5-2R o Compare" shi!t - Control . these include o 'esting and branching Conditional 6U#& . I7" loops Unconditional 6U#& - subroutine calls" returns

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Input$output . these include o -ata trans!er operations such as move" load" store #oving data !rom memory to secondary storage #oving data between registers or !rom register to memory

! Instruction "or#$t *very computer program has to be translated to machine language be!ore it can be e+ecuted. *ach statement in this program is called a machine code instruction. Instructions have 3 main parts , - the operation code 0the !unction that is to be done1 - the operand 0consists o! the address or the data to be operated on1 'he operation code tells the control unit what to do with the rest o! the 8data9. 'he e+act !ormat o! the statements in the machine language version 0ob)ect code1 o! the program will vary depending on the type o! processor which will carry out the instruction. *.g. o! a machine code instruction < < / / < < < < < < / < / < < <

Lets9 suppose that in this processor o! the /: bits the op-code is the !irst ; bits and the rest o! the instruction is the operand. An instruction may be con!igured in one o! several ways , a1 (ero address instructions , the entire machine code is the operation$instruction. 'his is possible with instructions such as CLC . clear R'S . return ASL . shi!t le!t one bit 'hey re uire no additional in!ormation. #ost machine code instructions have the two basic parts 0at least1 however. 'here are several schemes o! addressing called .
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A%%ressin& #o%es
Note that while our discussion below relate to a one address machine code (if the operation needs a second operand it can be found in the accumulator); lots of operators require 2 operands. The instruction code can therefore be a two-address instruction in which the operand specifies where both pieces of data can be found so that the operand is really two addresses. In this schema one address is usually in memory and the other a register. The following list is far from exhausti e. b1 i##e%i$te $%%ressin& . in immediate addressing the operand is not an address" it is the actual data to be used. < < / / < < < < < < / < / < < <

'his could there!ore mean add <<<<<</</<<< to the contents o! the accumulator c1 %irect $%%ressin& . in direct addressing" the operand is the address in memory where the data to be used is located. 'his means that one or more e+tra access o! memory is re uired be!ore the operation can be completed. < < / / < < < < < < / < / < < <

'his could there!ore mean add whatever is stored in memory location <<<<<</</<<< to the contents o! the accumulator d1 in%irect $%%ressin& . in indirect addressing the operand is the address o! the location where the address o! the data can be !ound. Ram will !irst have to be accessed at that address to pic% up the address o! the data> then the data location is !ound and that data is read into the processor.

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'his could mean go to <<<<<</</<<< and there you will !ind the address o! the data that is to be added to the contents o! the accumulator in%e'e% $%%ressin& . in inde+ addressing the re uired address is !ound by adding the operand to the contents o! a special address register or inde+ register. 'he operand is there!ore regarded as an o!!set !rom that base address. 'his method is actually used to process arrays. / < < < < < < / < / < < <

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Address register In this case the operand <<<<<</</<<< is to be added to <<<<</<<<//< in order to obtain the address o! the actual data to be used

!ome boo"s may also mention register addressing. In this mode the the operand is the name of the register that holds the data

All o! this o! course assumes "i'e% (en&th $%%ressin&. Some processors use )$ri$*(e (en&th $%%ressin&. 'hat means that the number o! bits used !or the operation code vs the operand can vary !rom instruction to instruction. ?e9ll leave the details !or our !irst year university computer science course.

4ote that one single machine may use more than one addressing mode. In such cases a mechanism is needed to indicate to the processor !or each instruction how it should
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be interpreted. 2ne way is to use one or more bits in the instruction code to indicate the addressing mode

The instruction si#e . the number o! bits or bytes in one instruction !or a particular machine. 'his is naturally related to the word si(e o! the processor. Recall that the word si(e is the number o! bits that the processor can handle at one time. 'his in turn is the si(e o! each memory location in RA#. 'he instruction si(e there!ore can be in multiples o! words.

'he address range o! an instruction is the range o! possible memory locations which may be speci!ied in the instruction" usually stated as < to 3 power o! the number o! bits used !or the memory address.

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2ther Important &rocessor Concepts

C$che #e#ory . 'he processor is the !astest element in a computer system. 2!ten it is idly waiting on data or instructions. Cache is one way to provide ready access to data !or the processor. Ay locating it near to or inside the processor and storing the most !re uently used pieces o! data in it" the processor9s wait time is reduced

The c(oc+ - is a simple electronic mechanism inside the processor which regularly produces a pulse o! electricity used to synchroni(e operations in the processor. 'he c(oc+ spee% is the number o! pulses generated per second. It is measured in #B( or CBD and is one !eature o! a processor to be aware o! when buying a machine. Cenerally the per!ormance o! a processor is determined by the cloc% speed" the bandwidth and the si(e o! the data bus. A larger cloc% speed should in theory result in a !aster machine. 2lder machines have cloc% speeds in the region o! @<#B(" =<<#B(" @<<#B( 4ewer values /;<<#B(" 3;<<#B(" 3E<<#B(" =3<<#B( i.e. CB( 'he cloc% pulse is li%e the heart beat o! the processor.

#icroprocessors 0and motherboards 1 also have *uses. A bus is a set o! parallel connectors inside the computer along which electronic signal can !low. Auses transmit data" programs and control in!ormation between devices. Auses can be classi!ied as internal or e+ternal. Internal buses are !ound inside a component e.g there are buses inside the C&U connecting its various parts. $xternal buses connect di!!erent motherboard components and also e+ternal devices to the motherboard. *very port has a bus behind it. 'his is how peripherals communicate with the motherboard$C&U. 'here are also buses between RA# and the C&U> the hard dis% controller and RA#" etc. Auses can be parallel or serial and they are not necessarily point to point" they can !orm a networ% on the motherboard. 'he bus si(e should correspond to the word si(e so that bus si(es can be /: bit" =3 bit" :; bit or /3E bit in width.

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Auses are dedicated to one %ind o! tas%. #icroprocessors have an address bus , sends addresses to and !rom memory a data bus , sends data to and !orm memory a control bus , carries control in!ormation !rom the control unit to and !rom other devices

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In indirect addressing" the si(e o! the address becomes an entire word instead o! )ust a part o! a word. Aecause the address is stored in one slot in memory" its si(e range !rom < to word-si(e. I! it is //: bits it will now be 3/: GH :@"@=@