BANGLADESH UNIVERSITY OF ENGINEERING AND TECHNOLOGY DEPARTMENT OF ELECTRICAL AND ELECTRONIC ENGINEERING

Course: EEE 315 Microprocessor and Interfacing, Term: November 2013

Assignment on Almost Simple As Possible Computer (ASAP) Design

Objectives: The objectives of this assignment is 1. To enable students to acquire better knowledge of working principles of microprocessors and computers. 2. To provide a basic understanding of execution of different computer instructions at machine level. Design Problem: Here in this assignment, students have to submit a software design of an 8-bit computer that can perform the instructions as per the instruction set assigned to them (The list is attached below). It is up to the students to choose suitable simulation softwares (Circuit Maker or Proteus may be good choices) for this design purpose. Each student has to implement 16 instructions assigned according to your student number. Submission procedure: Students have to complete their submission process in two phases. In the first phase each student will submit a block diagram of the architecture showing all the blocks (with appropriate control signals) necessary to perform the assigned instruction set. Along with the block diagram, a table showing active signals and microinstructions for every T state of fetch and execution cycles for each instruction of the computer has also to be submitted. Students may have to face a face a vivavoce to explain their architecture. In the second phase of submission, students will submit their circuit level designs. They have to simulate and explain their designs on-site. ASAP-13 Specifications: The design to be submitted by the students must conform to the following technical specifications: 1. 8-bit microcomputer. 2. Common BUS architecture. 3. 64 kbytes of main memory (RAM) support. 4. A and B registers are accessible to programmers (Students may include an additional temporary register if it is required). 5. 8-bit opcode. 6. Provision for hexadecimal input (students have to include a hexadecimal key encoder) 7. Provision for hexadecimal output (binary to hexadecimal converter is to be included) 8. Provision for run in single instruction mode (For example see SAP-1). 9. The computer has to wait for input. It will continue running when a switch is pressed after setting the input. 10. Flag register includes zero, sign, parity, carry and overflow flags. 11. Assembler program converts assembly code to machine code.

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12. All ICs except timer, RAM and ROM are from 74XXX series. 13. Clock frequency 1kHz. 14. Provision for loading program from a ROM or from hexadecimal keypad to the

system memory (RAM) at the beginning of the simulation.

Deadlines: Phase-I: 1. First working day after midterm vacation. Delayed submissions will be penalized (5 marks per day). 2. Online submission via engrade. 3. The suitable date for viva-voce will be informed later. Phase-II: 1. First working day of the last week of the term. 2. On-site submission. Circuit level designs will not be accepted without block diagrams and/or microprogram. Evaluation Policy: 1. Timely submission of block diagram and microprogram: 2. Viva-voce I: 3. Timely submission of circuit level design: 4. Viva-voce II: Total: 5. Compactness and efficiency 10 marks 05 marks 10 marks 05 marks 30 marks 05 marks (Bonus)

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ASAP-13 Instruction Sets

Student ID: XX0 Opcode Instruction 00 ADD [address], B 01 CALL address 02 MOV [address], A 03 JNZ address 04 PUSH [address] 05 POP A 06 XCHG B, A 07 IN A 08 MOV B, [address] 09 RET 0A HLT 0B OUT B 0C AND A, B 0D OR B, [address] 0E CMP A, B 0F RCR A Student ID: XX1 Opcode Instruction 00 IN B 01 XOR [address], B 02 CALL address 03 TEST A, [Address] 04 MOV B, byte 05 HLT 06 MOV A, [address] 07 PUSH A 08 OUT A 09 RET 0A JZ address 0B POP [address] 0C SUB A, B 0D XCHG [address], B 0E RCL A 0F NOT B Student ID: XX2 Opcode Instruction 00 SHL B 01 MOV A, byte 02 NOT A 03 CALL address 04 IN [address] 05 POP [address] 06 MOV B, [Address] 07 RET 08 CMP B, [address] 09 OUT B 0A PUSH B 0B ADD A, B 0C JA address 0D HLT 0E SUB A, [address] 0F XCHG [address], A

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Student ID: XX3 Opcode Instruction 00 XCHG B, [address] 01 NEG A 02 SHR B 03 ADD [address], B 04 CALL address 05 DEC A 06 MOV A, [address] 07 HLT 08 IN [address] 09 OR A, B 0A PUSH B 0B POP A 0C OUT B 0D RET 0E TEST A, [address] 0F JZ address

Student ID: XX4 Opcode Instruction 00 MOV [address], B 01 MOV B, byte 02 RCL A 03 INC B 04 HLT 05 CALL address 06 CMP B, [address] 07 IN B 08 JLE address 09 RET 0A OUT A 0B PUSHF 0C POPF 0D XOR [address], A 0E SUB B, [address] 0F XCHG A, B

Student ID: XX5 Opcode Instruction 00 JA address 01 HLT 02 CMP 03 POP [address] 04 ADD B, byte 05 NOT B 06 CALL address 07 IN A 08 MOV [address], A 09 PUSH [address] 0A XCHG [address], B 0B MOV B, Byte 0C NEG A 0D SHL B 0E OUT A 0F RET

Student ID: XX6 Student ID: XX7 Opcode Instruction Opcode Instruction 00 MOV A, byte 00 TEST A, [address] 01 DEC A 01 OUT A 02 PUSH A 02 IN B 03 IN [address] 03 JE address 04 JBE address 04 SUB B, byte 05 CMP A, B 05 PUSH [address] 06 POP B 06 HLT 07 CALL address 07 INC A 08 XCHG [address], A 08 CALL address 09 RET 09 SHR B 0A MOV B, A 0A XCHG [address], B 0B HLT 0B POP A 0C RCR B 0C MOV A, [address] 0D OUT B 0D RET 0E XOR [address], B 0E OR [address], A 0F ADD A, [address] 0F NOT B Student ID: XX9 Instruction RET JGE address HLT IN A MOV B, A ADD [address], byte XCHG [address], B SUB A, [address] NOT B RCR A CALL address POP B CMP B, [address] OUT A MOV [address], A PUSH A

Student ID: XX8 Opcode Instruction 00 IN A 01 MOV [address], A 02 RET 03 XCHG [address], B 04 INC [address] 05 PUSH B 06 CMP A, B 07 MOV B, byte 08 JAE address 09 CALL address 0A SHR A 0B OUT B 0C POP [address] 0D AND A, byte 0E DEC [address] 0F HLT

Opcode 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F

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Note: Byte means immediate 1 byte data e.g., MOV B, 5H will insert 05 H in B register. [address] means the content of e.g., MOV B, [5H] means copy the content of RAM location 05H to B

ASAP-13 Instruction Details

Syntax
MOV A, byte MOV B, byte MOV A, [address] MOV [address], A MOV B, [address] MOV [address], B ADD A, byte ADD B, byte ADD A, [address] ADD [address], A ADD B, [address] ADD [address], B SUB A, byte SUB B, byte SUB A, [address] SUB [address], A SUB B, [address] SUB [address], B XCHG A, B XCHG A, [address] XCHG [address], A XCHG B, [address] XCHG [address], B INC A INC B INC [address] DEC A DEC B DEC [address] NEG A NEG B AND A, byte AND B, byte AND A, [address] AND [address], A AND B, [address] AND [address], B OR A, byte OR B, byte OR A, [address] OR [address], A OR B, [address] OR [address], B XOR A, byte XOR B, byte XOR A, [address]

Meaning
Moves immediate byte to A Moves immediate byte to B Moves content of address to A Moves content of A to address Moves content of address to B Moves content of B to address Adds A with immediate byte and stores the result in A Adds B with immediate byte and stores the result in B Adds the value of A with content of address and stores the result in A Adds content of address with the value of A and stores the result in address Adds the value of B with content of address and stores the result in B Adds content of address with the value of B and stores the result in address Subtracts immediate byte from A and stores the result in A Subtracts immediate byte from B and stores the result in B Subtracts content of address from the value of A and stores the result in A Subtracts value A from of address and stores the result in address Subtracts content of address from the value of B and stores the result in B Subtracts B from address and stores the result in address Exchanges the contents of A and B Exchanges the contents of A and address Exchanges the contents of A and address Exchanges the contents of B and address Exchanges the contents of B and address Increments the content of A by 1 Increments the content of B by 1 Increments the content of address by 1 Decrements the content of A by 1 Decrements the content of B by 1 Decrements the content of address by 1 Negate A Negate B ANDs A with immediate byte and stores the result in A ANDs B with immediate byte and stores the result in B ANDs the value of A with content of address and stores the result in A ANDs content of address with the value of A and stores the result in address ANDs the value of B with content of address and stores the result in B ANDs content of address with the value of B and stores the result in address ORs A with immediate byte and stores the result in A ORs B with immediate byte and stores the result in B ORs the value of A with content of address and stores the result in A ORs content of address with the value of A and stores the result in address ORs the value of B with content of address and stores the result in B ORs content of address with the value of B and stores the result in address XORs A with immediate byte and stores the result in A XORs B with immediate byte and stores the result in B XORs the value of A with content of address and stores the result in A

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XOR [address], A XOR B, [address] XOR [address], B CMP A, byte CMP B, byte CMP A, [address] CMP [address], A CMP B, [address] CMP [address], B TEST A, byte TEST B, byte TEST A, [address] TEST [address], A TEST B, [address] TEST [address], B JMP address JZ address JNZ address JG address JGE address JL address JLE address JE address JA address JAE address JB address JBE address PUSH A PUSH B PUSH [address] POP A POP B POP [address] PUSHF POPF CALL address RET IN A IN B IN [address] OUT A OUT B HLT RCL A RCL B RCR A RCR B SHL A SHL B SHR A SHR B

XORs content of address with the value of A and stores the result in address XORs the value of B with content of address and stores the result in B XORs content of address with the value of B and stores the result in address Compares (subtraction) A with immediate byte and updates flags Compares (subtraction) B with immediate byte and updates flags Compares (subtraction) the value of A with content of address and updates flags Compares (subtraction) content of address with the value of A and updates flags Compares (subtraction) the value of B with content of address and stores the result in B Compares (subtraction) content of address with the value of B and updates flags ANDs A with immediate byte and updates flags ANDs B with immediate byte and updates flags ANDs the value of A with content of address and updates flags ANDs content of address with the value of A and updates flags ANDs the value of B with content of address and updates flags ANDs content of address with the value of B and updates flags Jumps to address: unconditional Jumps if result of previous operation was zero Jumps if not zero Jumps if greater (A > B, A is the source operand, and B is the destination operand): signed Jumps if greater or equal: signed Jumps if less: signed Jumps if less or equal: signed Jumps if equal Jumps if above (A>B, A is the source operand, and B is the destination operand): unsigned Jumps if above or equal: unsigned Jumps if below: unsigned Jumps if below or equal: unsigned Pushes the content of A to stack Pushes the content of B to stack Pushes the content of address to stack Pops the content of A from stack Pops the content of B from stack Pops the content of address from stack Pushes the flag register to stack Pops the flag register from stack Calls a procedure from address Return from procedure Takes an input from the input port and puts it inside the A register Takes an input and puts it inside the A register Takes an input and puts it as the content of address Displays the content of A in output port Displays the content of B in output port Halts the computer Rotate A with carry to left by 1 Rotate B with carry to left by 1 Rotate A with carry to right by 1 Rotate B with carry to right by 1 Shift A to left by 1 Shift B to left by 1 Shift A to right by 1 Shift B to right by 1