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VHDL => Finite State Machines

2012 E. Molenkamp, University of Twente, the Netherlands.

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1989-2012 E. Molenkamp, University of Twente, the Netherlands, Finite State Machines

How To Model FSMs?

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Moore / Mealy
asynchronous synchronous

register outputs

Reset
synchronous asynchronous

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1989-2012 E. Molenkamp, University of Twente, the Netherlands, Finite State Machines

Asynchronous Mealy

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Combinational circuit F1 en F2

Icurrent

Ocurrent

Snext

Scurrent

Snext = F1 (Scurrent, Icurrent) Ocurrent = F2 (Scurrent, Icurrent)

2012 E. Molenkamp, University of Twente, the Netherlands.

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1989-2012 E. Molenkamp, University of Twente, the Netherlands, Finite State Machines

Asynchronous Moore

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Combinational

Icurrent

circuit F1'

Combinational

Snext

Scurrent

circuit F2'

Ocurrent

Snext = F1 (Scurrent, Icurrent) Ocurrent = F2 (Scurrent)

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1989-2012 E. Molenkamp, University of Twente, the Netherlands, Finite State Machines

Summary Asynchronous FSMs ....................................................

a
1

. . . . .

Moore

Mealy

State variable: r r = /a (r + b) c = /r

State variable: s s = /b (s + a) c=a+s

2012 E. Molenkamp, University of Twente, the Netherlands.

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1989-2012 E. Molenkamp, University of Twente, the Netherlands, Finite State Machines

Synchronous Mealy

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It

Combinational circuit F1 en F2

Ot

Register

St+1

St

St+1 = F1 (St, It) Ot = F2 (St, It)

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1989-2012 E. Molenkamp, University of Twente, the Netherlands, Finite State Machines

Synchronous Moore

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It

Combinational circuit F1'

Register

St+1

St

Combinational circuit F2'

Ot

St+1 = F1 (St, It) Ot = F2 (St)

2012 E. Molenkamp, University of Twente, the Netherlands.

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Synchronous Mealy (some) inputs may change (some) outputs directly.

1989-2012 E. Molenkamp, University of Twente, the Netherlands, Finite State Machines

Summary Synchronous FSMs ....................................................

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There is only a difference in Synchronous Moore and Synchronous Mealy Machines !

Synchronous Moore Inputs never changes outputs directly. Outputs can only change after an active edge of the clock.

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1989-2012 E. Molenkamp, University of Twente, the Netherlands, Finite State Machines

Synchronous FSM With. .Register Outputs ..................................................

In applications often some of the outputs of the FSM should be available soon after the active edge of the clock. Example: a Controller (a FSM) and a Data path. (Some) register enable output signals are part of the critical path.

. . . . .

Controller register enable output register enable input

Datapath

2012 E. Molenkamp, University of Twente, the Netherlands.

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1989-2012 E. Molenkamp, University of Twente, the Netherlands, Finite State Machines

Register Outputs /2

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It

Combinational circuit F1' en F3

Register

Ot+1

Ot

Register

St+1

St

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1989-2012 E. Molenkamp, University of Twente, the Netherlands, Finite State Machines

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Register Outputs /3
Advantage
output faster

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signals are early available in the clock period

Disadvantage
(often) more

more registers needed hardware needed? (maybe technology dependent, especially for programmable logic)

2012 E. Molenkamp, University of Twente, the Netherlands.

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1989-2012 E. Molenkamp, University of Twente, the Netherlands, Finite State Machines

11

FSM Alternatives; Moore ....................................................

Write a VHDL description for this FSM

. . . . .

Init q=1 r=0

A=-,B=1 Oper q=0 r=1 A=-, B=-

asynchronous reset clock signal is clk

1989-2012 E. Molenkamp, University of Twente, the Netherlands, Finite State Machines

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FSM VHDL Coding Styles ....................................................

One process only Handles both state transitions and outputs
Two processes A synchronous process for updating the state register A combinational process for conditionally deriving the next machine state and updating the outputs Three processes A synchronous process for updating the state register A combinational process for conditionally deriving the next machine state A combinational process for conditionally deriving the outputs

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2012 E. Molenkamp, University of Twente, the Netherlands.

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LIBRARY ieee; USE ieee.std_logic_1164.ALL; ENTITY moore1 IS PORT (clk : IN std_logic; reset : IN std_logic; a, b : IN std_logic; q, r : OUT std_logic); END moore1;

1989-2012 E. Molenkamp, University of Twente, the Netherlands, Finite State Machines

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Synchronous Moore - Single Process ....................................................

. -- next state . . CASE state IS WHEN idle => IF a='1' THEN state:=init; END IF; WHEN init => IF b='1' THEN state:=oper; END IF; WHEN oper => state:=idle; WHEN OTHERS => state := idle; END CASE; -- output CASE state IS ARCHITECTURE asyn_reset_sol1 OF moore1 IS WHEN idle => q<='1'; r<='1'; WHEN init => q<='1'; r<='0'; BEGIN WHEN oper => q<='0'; r<='1'; PROCESS(reset,clk) WHEN OTHERS => q<='-'; r<='-'; TYPE states IS (idle, init, oper); END CASE; VARIABLE state : states; END IF; BEGIN END PROCESS; IF reset='0' THEN END asyn_reset_sol1; state := idle; q<='1'; r<='1'; ELSIF clk'event and clk='1' THEN Questions:
How are the states coded? Is the WHEN OTHERS needed? How many registers are expected?

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1989-2012 E. Molenkamp, University of Twente, the Netherlands, Finite State Machines

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Synchronous Moore - Single Process (Cont.) ....................................................

Coding of the states by synthesis tools
binary gray one-hot ...

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coded (default for most synthesis tools)

It is the experience of many Xilinx users that one hot coding seems to work fine.

Is the enumeration order of the type states important ? A way to prevent deadlock is to extend the number of literals of the enumeration type to a power of two (binary coding is assumed). Most synthesis tool will prevent deadlock automatically. This way of coding results in register outputs.
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clk reset
A X CK CL D Q XQ

1989-2012 E. Molenkamp, University of Twente, the Netherlands, Finite State Machines

15

Synchronous Moore - Single Process (Cont.) ....................................................

. . . . .

IV1N0 a

FD1B0

A1 A2 B C X

AOA4I0

b
A1 CK CL A X D Q XQ A2 X CK D PR Q XQ

ND2N0

FD1C0
CK D PR Q XQ

IV1N0

FD1B0 r

FD1C0

Outputs have registers

2012 E. Molenkamp, University of Twente, the Netherlands.

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1989-2012 E. Molenkamp, University of Twente, the Netherlands, Finite State Machines

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Synchronous Moore - Single Process (Cont.) ....................................................

. . . . .

clk reset
A X CK CL D Q XQ A1 A2 B X CK D PR Q XQ

IV1N0 a

FD1B0

OAI1A0

FD1C0

A1 A2 B1 B2 X

IV1N0

AO2I0
A1 A2 X

ND2N0
CK CL A X D Q XQ

CK D PR

Q XQ

FD1C0
CK D PR Q XQ

IV1N0

FD1B0

FD1C0

One-hot encoding

2012 E. Molenkamp, University of Twente, the Netherlands.

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TYPE states IS (idle, init, oper); SIGNAL state : states;
PROCESS(reset,clk) BEGIN IF reset='0' THEN state <= idle; ELSIF clk'event and clk='1' THEN -- next state CASE state IS WHEN idle => IF a='1' THEN state<=init; END IF; WHEN init => IF b='1' THEN state<=oper; END IF; WHEN oper => state <= idle; WHEN OTHERS => state <= idle; END CASE; END IF; END PROCESS;

1989-2012 E. Molenkamp, University of Twente, the Netherlands, Finite State Machines

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Synchronous Moore - Two Processes ....................................................

output:PROCESS(state) BEGIN CASE state IS WHEN idle => q<='1'; r<='1'; WHEN init => q<='1'; r<='0'; WHEN oper => q<='0'; r<='1'; WHEN OTHERS => q<='-'; r<='-'; END CASE; END PROCESS;

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Mostly not registered outputs!

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1989-2012 E. Molenkamp, University of Twente, the Netherlands, Finite State Machines

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Synchronous Moore - Two Processes (Cont.) ....................................................

A1 A2 X

. . . . .

A N2T0

CK CL D

Q XQ

reset clk

FD1B 0
A1 CK Q XQ A2 X

r q

A1 A2

CL D

ND2N0

ND2N0 b
A B S X

FD1B 0

M X 2L0

Mostly not registered outputs!

2012 E. Molenkamp, University of Twente, the Netherlands.

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The

1989-2012 E. Molenkamp, University of Twente, the Netherlands, Finite State Machines

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Synchronous Moore - Two Processes (Cont.) ....................................................

Register outputs can be achieved using user defined coding of the states:

. . . . .

length of the vector is equal to the number of outputs.

Each output has its own bit in the state coding vector. Additional internal registers are needed if more states have equal output patterns.

Example: output q and r and all states have different outputs. => type of states is std_logic_vector(1 DOWNTO 0); q r idle 1 1 init 1 0 oper 0 1
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1989-2012 E. Molenkamp, University of Twente, the Netherlands, Finite State Machines

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10

Synchronous Moore - Two Processes (Cont.) ....................................................

CONSTANT idle : std_logic_vector (1 DOWNTO 0) := "11"; CONSTANT init : std_logic_vector (1 DOWNTO 0) := "10"; CONSTANT oper : std_logic_vector (1 DOWNTO 0) := "01"; SIGNAL state : std_logic_vector (1 DOWNTO 0); PROCESS(clk,reset) Concurrent statements BEGIN IF reset='1' THEN q <= state(1); state <= idle; r <= state(0); ELSIF clk'event AND clk='1' THEN CASE state IS WHEN idle => IF a='1' THEN state<=init; END IF; WHEN init => IF b='1' THEN state<=oper; END IF; WHEN oper => state<=idle; WHEN OTHERS => state <= idle; END CASE; END IF; END PROCESS; register outputs due to user defined coding of the states
1989-2012 E. Molenkamp, University of Twente, the Netherlands, Finite State Machines

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2012 E. Molenkamp, University of Twente, the Netherlands.

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A1

21

Synchronous Moore - Two Processes (Cont.) ....................................................

q b
A2 A3 X

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ND3N0

A1 A2 B1 B2 X

CK D PR

Q XQ

FD1C0
CK Q XQ

OA I 3N0 r clk reset

A X D PR

FD1C0

I V 1N0

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1989-2012 E. Molenkamp, University of Twente, the Netherlands, Finite State Machines

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Synchronous Moore; IF. .THEN ..................................................

State transaction using IF .. THEN .. ELSIF PROCESS BEGIN WAIT UNTIL clk='1'; IF reset='1' THEN state <= idle; ELSIF state= idle THEN IF a='1' THEN state<=init; END IF; ELSIF state= init THEN IF b='1' THEN state<=oper; END IF; ELSIF state=oper THEN state<=idle; ELSE state <= idle; END IF; END PROCESS; q <= state(1); r <= state(0); Notice that the IF THEN ELSIF structure is less readable! Most synthesis tools advice to use the CASE in stead of the IF THEN ELSE.

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2012 E. Molenkamp, University of Twente, the Netherlands.

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signal STATE : STATES := REQ_WAIT; begin SET_OUTPUT: process begin ... case STATE is when REQ_WAIT => In this example two registers are used. State ACK_SET is coded with 11. Enum_encoding can be used for (sub)types.

1989-2012 E. Molenkamp, University of Twente, the Netherlands, Finite State Machines

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State Encoding: Tool Independent Solution ....................................................

attribute ENUM_ENCODING : string; type STATES is (REQ_WAIT, ACK_SET, NREQ_WAIT, ACK_CLR); attribute ENUM_ENCODING of STATES: TYPE IS "00 11 01 10" ;

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The IEEE Std. 1076.6-1999 standardized the coding of the states.

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1989-2012 E. Molenkamp, University of Twente, the Netherlands, Finite State Machines

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12

State Encoding: Tool Independent Solution ....................................................

attribute ENUM_ENCODING : string; type STATES is (REQ_WAIT, ACK_SET, NREQ_WAIT, ACK_CLR); attribute ENUM_ENCODING of STATES: TYPE IS "0001 0100 1000 0010" ; signal STATE : STATES := REQ_WAIT; begin SET_OUTPUT: process begin ... case STATE is when REQ_WAIT =>

. . . . .

Note: - synplify use(d) the attribute syn_enum_encoding - Quartus use(d) the attribute syn_encoding

In this example four registers are used. State ACK_SET is coded with 0100.

2012 E. Molenkamp, University of Twente, the Netherlands.

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1989-2012 E. Molenkamp, University of Twente, the Netherlands, Finite State Machines

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State Encoding: Tool Independent Solution ....................................................

attribute FSM_STATE : string; attribute FSM_COMPLETE : string; type STATES is (REQ_WAIT, ACK_SET, NREQ_WAIT, ACK_CLR); signal STATE1, STATE2 : STATES := REQ_WAIT; attribute FSM_STATE of STATE1: SIGNAL IS "BINARY" ; attribute FSM_STATE of STATE2: SIGNAL IS "00 11 10 01" ; attribute FSM_COMPLETE of STATE1 : signal is TRUE;

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The IEEE Std. 1076.6-2004 added FSM_STATE Can be used for (sub)types, signals and variables Can be used similar as enum_encoding. But also binary, gray, one_hot, one_cold and auto Attribute FSM_COMPLETE then no deadlock in FSM

1989-2012 E. Molenkamp, University of Twente, the Netherlands, Finite State Machines

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13

Synchronous Reset / Synchronous Moore FSM ....................................................

BEGIN WAIT UNTIL clk='1'; IF reset='1' THEN state := idle; END IF; CASE state IS

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2012 E. Molenkamp, University of Twente, the Netherlands.

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A A1 A2 X A1 A2 A3 A4 A X X A1 A2 A3 X X

1989-2012 E. Molenkamp, University of Twente, the Netherlands, Finite State Machines

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Asynchronous Reset / Synchronous Moore FSM (Cont.) ....................................................

. . . . .

IV1N0

reset a

B C

AOA4I0

CK A1 A2 X D

Q XQ

ND4N0

NR3R0

IV1N0

FD1A0
CK D Q XQ

OR2T0 q

b clk
CK D EN Q XQ

CK A1 A2 X A X D EN

Q XQ

FD1A0

IV1N0

ND2N0

FD1H0
A X

FD1H0

IV1N0

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1989-2012 E. Molenkamp, University of Twente, the Netherlands, Finite State Machines

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14

Synchronous Mealy
Reset

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idle ab / qr 11 / 10 01 / 01 init

-0 / 00

Write a VHDL description for this FSM

-0 / 00

-1 / 10

oper

asynchronous reset clock signal is clk

2012 E. Molenkamp, University of Twente, the Netherlands.

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1989-2012 E. Molenkamp, University of Twente, the Netherlands, Finite State Machines

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Synchronous Mealy - Two Processes ....................................................

TYPE states IS (idle, init, oper); SIGNAL state : states; PROCESS(reset,clk) BEGIN IF reset='1' THEN state <= idle; ELSIF rising_edge(clk) THEN CASE state IS WHEN idle => IF b='1' THEN state<=init; END IF; WHEN init => IF b='1' THEN state<=oper; END IF; WHEN oper => state<=idle; WHEN OTHERS => state <= idle; END CASE; END IF; END PROCESS;

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1989-2012 E. Molenkamp, University of Twente, the Netherlands, Finite State Machines

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Synchronous Mealy - Two Processes (Cont.) ....................................................

PROCESS(state,a,b) BEGIN CASE state IS WHEN idle => CASE std_logic_vector'(a & b) IS WHEN "11" => q<='1'; r<='0'; WHEN "01" => q<='0'; r<='1'; WHEN OTHERS => q<='0'; r<='0'; END CASE; WHEN init => IF b='1' THEN q<='1'; r<='0'; ELSE q<='0'; r<='0'; END IF; WHEN oper => q<='1'; r<='1'; WHEN OTHERS => q<='0'; r<='0'; END CASE; END PROCESS;

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2012 E. Molenkamp, University of Twente, the Netherlands.

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b
A1 A2 X

1989-2012 E. Molenkamp, University of Twente, the Netherlands, Finite State Machines

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Synchronous Mealy - Two Processes (Cont.) ....................................................

. . . . .

ND2N0

A B S X

MX2L0 clk
CK CL D Q XQ A1 A2 X

CK CL D

Q XQ

FD1B0
A B S X

reset a

FD1B0

IV1N0

AN2T0
A1 A X A2 B C X

MX2T0 r

IV1N0

OAOI0

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1989-2012 E. Molenkamp, University of Twente, the Netherlands, Finite State Machines

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Synchronous Mealy - Three Processes ....................................................

TYPE states IS (idle, init, oper); SIGNAL inp_state, state : states; PROCESS(clk,reset) BEGIN IF reset='1' THEN state <= idle; ELSIF clk='1' AND clk'EVENT THEN state <= inp_state; END IF; END PROCESS; next_state:PROCESS(state, a, b) BEGIN CASE state IS WHEN idle => IF b='1' THEN inp_state<=init; ELSE inp_state<=idle; END IF; WHEN init => IF b='1' THEN inp_state<=oper; ELSE inp_state <= init; END IF; WHEN oper => inp_state<=idle; WHEN OTHERS => inp_state <= idle; END CASE; END PROCESS;
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2012 E. Molenkamp, University of Twente, the Netherlands.

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1989-2012 E. Molenkamp, University of Twente, the Netherlands, Finite State Machines

Synchronous Mealy - Three Processes (Cont.) ....................................................

output_function:PROCESS(state,a,b) BEGIN CASE state IS WHEN idle => CASE std_logic_vector'(a & b) IS WHEN "11" => q<='1'; r<='0'; WHEN "01" => q<='0'; r<='1'; WHEN OTHERS => q<='0'; r<='0'; END CASE; WHEN init => IF b='1' THEN q<='1'; r<='0'; ELSE q<='0'; r<='0'; END IF; WHEN oper => q<='1'; r<='1'; WHEN OTHERS => q<='0'; r<='0'; END CASE; END PROCESS;

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1989-2012 E. Molenkamp, University of Twente, the Netherlands, Finite State Machines

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17

Synchronous Mealy - Three Processes (Cont.) ....................................................

b
A1 A2 X

. . . . .

ND2N0

A B S X

MX2L0 clk
CK CL D Q XQ A1 A2 X

CK CL D

Q XQ

FD1B0
A B S X

reset a

FD1B0

IV1N0

AN2T0
A1 A X A2 B C X

MX2T0 r

IV1N0

OAOI0

2012 E. Molenkamp, University of Twente, the Netherlands.

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18