Redefining CMOS Logic Style for Subthreshold Operation

Sreehari Veeramachaneni
Centre for VLSI and Embedded System Technologies International Institute of Information Technology (IIIT) Hyderabad, India. srihari@research.iiit.ac.in
Abstract Sub-threshold design of CMOS logic circuits is important for ultra low-power operation. With continuous scaling of MOS devices to nanometer sizes however, conventional CMOS logic style may not function properly at 65nm and below due to a variety of leakage currents flowing. Thus alternative logic styles, such as, transmission-gate, have been proposed for sub-threshold operation in nanometer regime. In this work, a new CMOS logic style, that results in reduced leakage currents both in active and idle modes of operation leading to a better static and dynamic performance, is proposed. Simulations have been carried out in Cadence Spectre to verify the functionality of the gates using standard 65nm technology. Results indicate that static power reduction of up to 25% has been achieved. The utility of the new logic style is demonstrated with a 1-bit full-adder circuit.

M.B.Srinivas
Department Electronics and Communication Engg., Birla Institute of Technology and Science (BITS), Hyderabad Campus, Hyderabad, India srinivas@iiit.ac.in devices. In this paper, a novel sub-threshold CMOS logic style with balanced network is proposed. All the basic gates such as NAND, NOR, AND, OR, XOR, XNOR have been designed and analyzed for operation in the sub-threshold region. II. RELATED WORK

A. Transmission Gate Logic Style The effect of active leakage and transistor stacking on the gate functionality has been observed by Chandrakasan et.al [1, 3, 5-7, 10] during low-voltage operation when the gate drives are lowered to the point that, ON currents compete with the leakage currents. These effects are illustrated using tiny XOR gate in Fig.1 [1, 3, 5-7,10].

I.

INTRODUCTION

Continuous scaling down of MOS devices in to nano meter region demands new logic styles and circuit designs that provide leakage reduction without affecting the performance. As technology moves below 65nm, leakage current can affect the functionality of the device even during the active mode of operation. Existing techniques provide leakage reduction in idle mode of operation but can not be used in active mode in view of the effect on performance of the circuit and resulting delay [1-7,16- 17]. Most of the leakage reduction techniques focus on standby leakage, whereas active leakage has a significant contribution to total leakage impacting the functionality as the technology scales down to 45nm and below [1-7, 16-17]. Proper functionality of a cell and active leakage in subthreshold region are indicated by I ON I OFF ratio. I ON is defined as the drive current that decreases exponentially as supply voltage is lowered to sub-threshold regions. I OFF is defined as the idle current that flows even when the circuit is not active [15-16]. The primary reason that impacts the functionality of conventional CMOS gates under low voltage of operation is the degraded of ON to OFF currents ( I ON I OFF ) ratios due to its unbalanced number of parallel
Figure 1.

(a)

(b)

Tiny XOR (a) Schematic Diagram and Nodal Analysis (b) Simulation Results

An analysis of the drive currents and leakage currents for the input vector (A=1 and B=0) shows that since there are three OFF devices and one ON device, I ON I OFF is degraded. The simulation shown in Fig.1 (b) for A=1 and B=0 illustrates that Z output is only driven to 55 mV. This effect is further compounded if process variations are also considered in the analysis [1, 3, 5-7, 10]. A transmission gate-based XOR has been offered as a solution to overcome this problem [1, 3, 5-7, 10] since the number of parallel devices is minimized (or balanced) for minimum-voltage operation in this structure, thus reducing

978-1-4244-3732-0/09/$25.00 2009 IEEE

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the effect of leakage. It should however be remembered that the transmission-gate logic style has drawbacks such as limited drive capability, parallel leakage, sneak leakage path [1, 3, 5-7,10] etc and thus conventional CMOS logic style should be more preferable even for sub-threshold operation, which is examined below. B. CMOS Logic Style 2-Input NAND Gate: CMOS design of a conventional 2input NAND gate is given in Fig 2(a). For inputs A= 1 and B =1 both the PMOS transistors are OFF and stacked NMOS transistors are ON. This gives two OFF currents and one drive current, resulting in a degraded Ion/Ioff ratio. Moreover, transistor stacking of NMOS devices in NAND gate gives diminished drive current. This further degrades Ion/Ioff ratio as well as the functionality as shown in Fig 2(b). This figure also demonstrates that the voltage at which the 2-input NAND gate fails functionally is 0.12V. This effect becomes more significant in a 3-input NAND gate, where there are three parallel devices which are in OFF state and three transistors that are stacked and in ON state [1-8].

From the figure, its apparent that the idle (sub-threshold and gate) currents are balanced with drive currents at the output node. This is due to the symmetry of the proposed logic structure as shown in figure 3(a). As can be seen from Fig. 3 (b), the dynamic performance of this NAND gate is perfect even for sub-threshold operation. Other gates, such as NOR, AND, OR, XOR, etc.., may also be designed in a similar fashion. C. Simulation Step-up for Functional Verification:

(a)

(b)

(c)

(a)

(b)

Figure 2. CMOS NAND Gate (a) Schematic Diagram and Nodal Analysis (b) Simulation Results at 0.12V

Thus, to have better functionality for operation in subthreshold region, there is a need for new gate designs that follow CMOS logic style but with balanced number of transistors[12-14]. In this work, novel logic gates have been designed, considering tri-state inverter as a basic structure. Fig. 3(a) shows a new NAND gate structure with an illustration of currents at various nodes.

(d)

(e)

Figure 4. (a) Example circuit for verifying logic gate outputs (b)Conventional CMOS Gates (c) Proposed CMOS logic style (d) Butterfly plot of conventional CMOS with failing functional output levels (e) Butterfly plot of proposed CMOS logic style with functional output levels.

(a)

(b)

Figure 3. Proposed NAND Gate (a) Schematic Diagram and Nodal Analysis (b) Simulation Results at 0.12V

The shape of the voltage transfer characteristic (VTC) of a logic gate is important for signal regeneration down the logic path and is, thus, a key indicator of the gates functionality and its done by the butterfly plots shown in Fig. 4 [6-8,10]. The plot is obtained by envisioning two logic gates back-to-back [as shown in Fig. 4 (a)], which therefore corresponds to plotting the direct VTC of one superimposed on the inverse VTC of the other; intersection points then represent physically stable voltage levels. To

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verify the functionality, simulation have been carried out using the circuits shown in Fig. 4(b) for the conventional CMOS gate and Fig. 4(c) for the proposed balanced CMOS gates. From the simulation results in Figs. 4 (d) and (e), it can be seen that the proposed gate works very well and has a good butterfly curve whereas the conventional CMOS design fails for an input voltage of 0.12V [6-8,10]. D 1-Bit Full Adder Design In the following, the proposed gates have been used to design a 1-bit full adder circuit and compare its operation with that designed with conventional CMOS gates. Following are the Boolean equations for a 1-bit full adder circuit [15] and the schematic in Fig. 5 shows the currents flowing in a conventional CMOS circuit.
C o = A B + ( A + B )C i SU M = ABC i + C o ( A + B + C i) SU M = A B C i SU M = A B C i C o = ( A ( A B )) + ( C i ( A B )) (1) (2) (3) (4) (5)

Figure 6. 1-bit CMOS Full AdderCircuit : Simulation Results for (a) Sum and (b) Carry at 0.16V

(a)

(b)

Figure 7. 1-bit Full Adder with Proposed Logic Style ; Simulation Results for (a) Sum and (b) Carry at 0.16V

III.

SIMULATION RESULTS

Some inputs of the proposed gates are inverted and therefore inverters have been taken in to consideration while performing the simulations. Also, since the gates are all stacked [11-14], the ratio of the devices is taken in to account for optimal current drivability [11]. (a)
Figure 5.

(b) Tables I compares the power dissipated by the proposed gates with that of the standard CMOS gates in sub-threshold region. All the simulations have been carried out using TSMC 65nm technology library using Cadence Spectre. For a 2-input conventional CMOS gate, logical failure occurs at 0.12V [6-8] which is verified by the butterfly curves shown in Fig 4. The tables clearly depict that the proposed logic style works efficiently, even at the lower values at which the standard CMOS logic fails functionally while consuming up to 20% less power. Also, the proposed logic style, as shown clearly in Tables II consumes less power ( 25%) at higher voltages where the standard CMOS logic style is functional. The proposed designs consume less power in spite of having high transistor count only because the leakage power associated with these designs is less [11-14]. All the simulations are carried out at an operating frequency of 100 KHz

Current modeling (a) A=0, B=0 and C=0 (b) A=1, B=1 C=1

Leakage currents flowing for the input vector A=0, B=0 and C=0 is shown in Fig.5 (a). It can be observed that the output node at carry has two drive currents and six idle currents due to four gate leakages and two sub-threshold leakages. This results in a degraded Ion/Ioff ratio. The output node at sum has one drive current and 3 leakage currents leading to degraded functionality. Leakage currents for the input vector A=1, B=1 and C=1 in Fig. 5 (b) also behave in a similar unbalanced fashion leading to degraded performance [9]. The simulation results shown in figure 6 also illustrate the functional failure of the adder circuit for both Sum and Carry. The above equations for Sum and Carry have been used to design the 1-bit full adder circuit using the proposed logic style and it is clear from Fig. 7 that it has a correct logical behaviour in sub-threshold region.

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TABLE I.

A COMPARISON OF THE POWER DISSIPATED BY THE CONVENTIONAL AND PROPOSED GATES OPERATING VOLTAGE AT 0.12 V

V.
[1]

REFERENCE:
[1] Alice Wang, Benton H. Calhoun, Anantha P. Chandrakasan,Subthreshold Design for Ultra Low-Power Systems Springer, 2006. [2] R. M. Swanson and J. D. Meindl,Ion-implanted complementary MOS transistors in low-voltage circuits, IEEE J. of Solid-State Circuits, vol. SC-7, April 1972, pp.146-153. [3] Narendra, Siva G, Chandrakasan, Anantha (Eds.), Leakage in Nanometer CMOS Technologies Springer, 2005. [4] Amit Agarwal, Saibal Mukhopadhyay, Arijit Raychowdhury, Kaushik Roy, Chris H. Kim; Leakage Power Analysis and Reduction for Nanoscale Circuits, IEEE Micro, Vol. 26, Issue 2, pp. 68-80, March- April 2006. [5] A. Wang and A. Chandrakasan, A 180-mV Subthreshold FFT Processor Using a Minimum Energy Design Methodology, IEEE J. Solid-State Circuits, vol. 40, pp. 310-319, Jan., 2005. [6] Verma, N., J. Kwong, A. P. Chandrakasan, Nanometer MOSFET Variation in Minimum Energy Subthreshold Circuits, IEEE Transactions on Electron Devices, pp. 163-174, January 2008. [7] Kwong, J., A. P. Chandrakasan, Variation-Driven Device Sizing for Minimum Energy Sub-threshold Circuits, International Symposium on Low Power Electronics and Design (ISLPED), pp. 813, October 2006. [8] J. Lohstroh, E Seevinck, J de Groot., Worst-case Static Noise Margin Criteria for Logic Circuits and Their Mathematical Equivalence, IEEE J. Solid-State Circuits, vol. SC-18, no. 6, pp. 803-807,June 1983. [9] Yang S., W. Wolf, W. Wang, N. Vijaykrishnan, Y. Xie. January 2005. Accurate Stacking Effect Macro-modeling of Leakage Power in Sub- 100nm Circuits Proceedings of the Eighteenth International Conference on VLSI Design. pp. 165-170. Kolkata, India. [10] Kwong, J., Y. K. Ramadass, N. Verma, and A. Chandrakasan, "A 65nm Sub-Vt Microcontroller with Integrated SRAM and Switched Capacitor DC-DC Converter," IEEE Journal of Solid-State Circuits, vol. 44, no. 1, pp. 115-126, January 2009. [11] J. Keane, H. Eom, T. Kim, S. Sapatnekar, and C. Kim, "Stack Sizing for Optimal Current Drivability in Subthreshold Circuits", IEEE Trans. on VLSI Systems, May 2008. [12] A. Agarwal, S. Mukhopadhyay, A. Raychowdhury, K. Roy, and C. H. Kim, "Leakage Power Analysis and Reduction for Nanoscale Circuits", IEEE Micro, Vol. 26, Issue 2, pp. 68-80, March-April 2006. [13] Y. Ye, S. Borkar, and V. De, "A Technique for Standby Leakage Reduction in High-Performance Circuits," Symp. of VLSI Circuits, pp. 40-41, 1998. [14] S. Mukhopadhyay, C. Neau, T. Cakici, A. Agarwal, C. H. Kim, and K. Roy, "Gate Leakage Reduction for Scaled Devices Using Transistor Stacking", IEEE Trans. on VLSI Systems, Vol. 11, Issue 4, pp. 716-730, Aug. 2003. [15] Jan M. Rabaey, Anantha Chandrakasan, Borivoje Nikolic; Digital Integrated Circuits: A Design Perspective 2nd Ed. PrenticeHall, 2003. [15] Scott Hanson, Bo Zhai, Kerry Bernstein, David Blaauw, Andres Bryant, Leland Chang, Koushik Das, Wilfried Haensch, Edward Nowak, Dennis Sylvester, "Ultra-Low Voltage Minimum Energy CMOS," IBM Journal of Research and Development, Vol. 50, No. 4/5, July/September 2006, pg. 469-490 [16] Scott Hanson, Bo Zhai, Mingoo Seok, Brian Cline, Kevin Zhou, Meghna Singhal, Michael Minuth, Javin Olson, Leyla Nazhandali, Todd Austin, Dennis Sylvester, David Blaauw, Exploring Variability and Performance in a Sub-200 mV Processor, IEEE Journal of Solid-State Circuits (JSSC), Vol. 43, No. 4, April 2008, pgs. 881 891.

[2] Conventional (pW) NAND2 NOR2 AND2 OR2 XOR2 XNOR2 TABLE II. 90 96 104.2 107 118 121 OPERATING VOLTAGE AT 0.16V [7] Conventional (pW) NAND2 NOR2 AND2 OR2 XOR2 XNOR2 106.2 113.3 123 126 139 142 TABLE III. Proposed (pW) 84 84.2 86 86.4 89 87 OPERATING VOLTAGE AT 0.16V conventional (pW) 1-bit Full Adder TABLE IV. 340 proposed (pW) 220 OPERATING VOLTAGE AT 0.2V conventional (pW) 1-bit Full Adder 450 proposed (pW) 348 [13] [12] [11] [10] [9] [8] Proposed (pW) 74 74.6 78 77.4 81 82 [6] [5] [3] [4]

[14]

Tables III compares the power dissipated by the proposed 1bit adder with that of the standard CMOS design [15]. The tables clearly depict that the proposed logic style works efficiently, even at the lower values at which the standard CMOS logic fails functionally while consuming less power. IV. CONCLUSIONS

[15]

[16]

In this work, a new CMOS logic style for sub-threshold operation has been proposed. It has a balanced network of parallel devices resulting in higher I ON I OFF ratio leading to correct logical behavior with improved noise margin over conventional CMOS design. 1-bit full adder circuits designed using the proposed logic style also show excellent logical and power dissipation characteristics compared to the conventional CMOS design.

[17]

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