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REGISTRO DE

DESPLAZAMIENTO
EN BASE OCTAL
TRABAJO DE SISTEMAS ELECTRNICOS
INDUSTRIALES
INTEGRANTES:

- Ral Sanz Gmez(45725)


- Oscar Toledo Vsquez (48628).
- Jorge Astudillo Pineda (48783).

ndice
Introduccin y descripcin del trabajo
Introduccin
Descripcin de la estrategia y algoritmos desarrollados

Cdigo y explicacin de cada mdulo


Antirrebote
detec_pulso
pulso_tiempo
pulso_tiempo_tb
DUENDE
DUENDE_TB
reg8desp
reg8desp_tb
mux2to1
binTo7seg
dec1To2
balan2elem
REG_TOP
REG_TOP_TB
Asociacin de patillas de la FPGA con las seales del mdulo REG_TOP
REG_TOP UCF

INTRODUCCIN
Y
DESCRIPCIN
DEL TRABAJO

Introduccin
Este memoria es el trabajo de la asignatura Sistemas Electrnicos Digitales, cuyo enunciado es el
siguiente:
Disee un registro de desplazamiento octal, esto es, que inicialmente tenga a su salida 0000 0000 y
que cuando se introduzca un '1' con un pulsador pase a 0000 0001 0000 0010 y as
sucesivamente hasta llegar a 0000 0100, de donde pasar a 0001 0000. Cada vez que se pulse, se
introduce un '1' en el bit menos significativo y recorre las posiciones hasta volver a cero, pero no
introducir el '1' si el nmero resultante no pertenece a la base. Como entradas tendr una seal
de '1', y como salidas dos visualizadores en los que se mostrar el decimal de cada nibble.
A esto hay que aadir una mejora que hemos incluido: adems de los dos visualizadores, hemos
puesto como salida tambin los ocho Leds que dispone la placa Espartan 3E, de esta manera
podemos representar los bits en los Leds, de manera que cada Led encendido represente cada bit del
registro. De esta manera podemos ver y tener en cuenta el desplazamiento que ocurre en el registro.

Descripcin de la estrategia y algoritmos desarrollados


Para abordar el problema hemos decidido dividir el sistema en tres grupos funcionales:
1. Tratamiento de la seal de entrada: es la parte que filtra la seal de entrada y devuelve
una seal de duracin un ciclo de reloj interno (50MHz). Se compone de un filtro antirrebote
controlado por el mdulo que genera pulsos de un ciclo de reloj interno cada 10 ms, a
continuacin le sigue un mdulo de detector de pulso (detec_pulso).
2. Unidad procesadora DUENDE: es donde se encuentra el registro de 8 bits y donde se
hace el desplazamiento a izquierdas. Se compone de dos mdulos: el mdulo reg8desp
que almacena el registro y crea el desplazamiento, y el mdulo pulso_t1, que crea pulsos de
un ciclo de reloj interno cada 1 s, esto es para el periodo con el que se hace el
desplazamiento.
3. Tratamiento de la seal de salida: aqu se encuentran todos los mdulos necesarios para la
visualizacin del registro en los dos displays.
Estos tres grupos constituyen el mdulo REG_TOP, el cual es el objetivo del trabajo, y el que posee
tres entradas: pulsador (BTN), reset, y clk. Y como salidas: la salida de los segmentos del display
(segment), la salida para el control de visualizacin de los segmentos (DIGCTRL), 2 salidas para
conectar a los displays que no se van a usar (uno1 y uno2), y la salida a los LEDS.
A continuacin se muestra el esquema de este bloque REG_TOP, seguido del mdulo DUENDE.
Nota: los mdulos pulso_t1, pulso_2 y puslo_3, representan el componente pulso_tiempo (cuyo
cdigo y explicacin se encuentra ms adelante).

REG_TOP
Btn

detec_pulso

antirrebote

sin_reb

Btn

c_i

BT
f_i(3:0)

inA

mux2to1

clk_T

b_i

reset

binTo7seg
g_i

pulso
f_i(7:4)

bin

outZ

clk

segment

seg

inB

P_T

clk

pulso_2

a_i

reset

S(0)

e_i

2
I

dec1To2

uno1

S(1)

P_T

uno2

DUENDE

registro

reset
8

8
f_i

clk
reset
balance

pulso_3
P_T

clk
reset

d_i

clk_T

CLK

DIGCTRL

balan2elem

LEDS

DUENDE

P_T

carga
a

desp

P_T

CLK

clk

registro

reg8desp

pulso_t1

reset

clk

reset

reset

registro

CDIGO
Y
EXPLICACIN
DE CADA MDULO

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--------------------- ANTIRREBOTE ------------------------------actualizado


201401150743 (2014/01/15 07:43)
-----------------------------------------------------------------_____________
-|
|
-Btn ____|
|____ sin_reb
-|
____
|
-|
^
|
-|
___|
|
-clk_T____|
|
-|_____________|
-|
-|
-reset
---- Filtra la entrada para dar una salida uniforme de duracion
-- un ciclo de reloj clk_T.
-- Se activa cuando detecta un flanco de subida en la entrada Btn.
---------------------------------------------------------------------------------------------Detalles---------------------------------_
_
_
__
_
_____________________________
-BT ____| |__| |__| |_| |_| |_|
-_____________
_____________
-- clk_T _______|
|_____________|
|_______
-_________________________
--sin_reb ________|
|_____________________
--------------------------------------------------------------------- librerias
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
------------------------------------------------------------------entidad
entity antirrebote is
Port(
Btn : in std_logic;
clk_T : in std_logic;
reset : in std_logic;
sin_reb : out std_logic -- seal sin rebotes
);
end antirrebote;
architecture behavioral of antirrebote is
signal aux: std_logic :='0';
begin
sin_reb <= aux;
process (clk_T,Btn,reset)
begin
if reset = '1' then aux <= '0';
elsif clk_T = '1' and clk_T'event then
aux <= Btn;
end if;
end process;
end behavioral;

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--------------- DETECTOR DE FLANCOS DE SUBIDA ---------------------actualizado


201401131227 (2014/01/13 12:27)
--------------------------------------------------------------------_____________
-|
|
-BT ____|
|____ PULSO
-|
____
|
-|
^
|
-|
___|
|
-clk ____|
|
-|_____________|
--- Detecta flanco de subida de la entrada y manda un pulso de
-- un ciclo de reloj.
--------------------------------------------------------------------------------------------Detalles----------------------------------______________________
_____
-_____
|
_____
|_| and |
-- BT ______| reg |__BT_R1_|__| reg |_BT_R2__|\o____| & |_____PULSO
-__|flanc|
_____|flanc|
|/
|_____|
-| |_____|
|
|_____|
-|
|
-- clk __|______________|
---__
__
__
__
__
__
__
__
__
__
-- clk __| |__| |__| |__| |__| |__| |__| |__| |__| |__| |
-______________
_____________________
-BT ____|
|___________|
|______
-_____
_____
-- PULSO ________|
|_________________|
|_____________________
----------------------------------------------------------------------librerias
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
--------------------------------------------------------------------- entidad
entity detec_pulso is
port(

BT,clk: in std_logic;
pulso: out std_logic:='0');

end detec_pulso;
--------------------------------------------------------------------- arquitectura comportamental serie
architecture comportamental of detec_pulso is
signal BT_R1,BT_R2: std_logic; --son las salidas de los registros
begin
reg_D1: process(clk,BT)
begin

--proceso para el primer biestable tipo D

if (clk'event and clk='1') then


BT_R1<=BT;
end if;
end process;
reg_D2: process(clk,BT_R1)
begin
if(clk'event and clk='1') then
BT_R2<=BT_R1;
end if;
end process;
pulso<=BT_R1 and (not BT_R2); -- es la parte combinacional del detector
end comportamental;
--------------------------------------------------------------------

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--------------------- PULSO_TIEMPO ------------------------------actualizado 201401150834 (2014/01/15 08:34)


-------------------------------------------------------------------__________
-|
|
-Clk ____|>
|____ Pulso_tiempo
-|
|
-|__________|
-|
-Reset
--- Genera pulsos de periodo t a partir de un relo de 50MHz.
-----------------------------------------------------------------------------------------DETALLES------------------------------------_
_
_
_
_ / / _
_
_
_
_
_
_
-Clk _| |_| |_| |_| |_| |/ /_| |_| |_| |_| |_| |_| |_| |_
-_
/ /
_
-- Pulso_tiempo _| |______________/ /_____________________| |_______
-:
/ /
:
-:
:
-:................... t ..................:
---- para calcular la cuenta maxima que debe tener para un periodo
-- deseado, se hace la siguiente operacin:
--max = t/20ns
(para un reloj de 50MHz)
--- Algunos valores para clk de 50MHz:
-max
t
-50
1us
-500
10us
-5 000
100us
-50 000
1ms
-500 000
10ms
-5 000 000
100ms
-50 000 000
1s
--- para una entrada de reloj distinta:
max = t*fre_clk
--- NOTA: cuenta maxima = 2^26-1 = 67 108 863
--------------------------------------------------------------------------------------- NOTA DE SIMULACION --------------------------- Es mejor simularlo para una cuenta maxima de 50 (max:=50), es
-- decir, para obtener 1us en la salida para que la simulacion
-- sea mas rapida.
--------------------------------------------------------------------librerias
library ieee;
use ieee.std_logic_1164.all;
--use ieee.std_logic_arith.all;
--use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
-------------------------------------------------------------------entidad
entity pulso_tiempo is
generic (max: integer range 0 to 2**26-1 := 10);
port(
clk,reset: in std_logic;
p_t: out std_logic);
end pulso_tiempo;
------------------------------------------------------------------

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--arquitectura comporatametal serie divisor de frecuencia


architecture comportamental of pulso_tiempo is
signal cuenta: natural range 0 to 2**26-1 := 0; --registro para contar
-- 2^26 > 50 000 000
begin
P_contar:

process(clk,reset)
begin
if reset = '1' then
cuenta<=0;
p_t<='0';
elsif clk'event and clk='1' then
if cuenta >= max - 1 then
p_t<='1';
cuenta<=0;
else
p_t<='0';
cuenta<=cuenta + 1;
end if;
end if;
end process;
end comportamental;
-------------------------------------------------------------------

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------------------- pulso_tiempo_TB_UUT -------------------------actualizado 201401130955 (2014/01/13 09:55)


------------------------------------------------------------------------------------------------------------------------------------libreria
library ieee;
use ieee.std_logic_1164.all;
--use ieee.std_logic_arith.all;
--use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
--------------------------------------------------------------------entidad
entity pulso_tiempo_tb is
end pulso_tiempo_tb;
-------------------------------------------------------------------arquitectura
architecture behavior of pulso_tiempo_tb is
--declaracion de componentes a examinar
component pulso_tiempo is
port(
clk,reset: in std_logic;
p_t: out std_logic);
end component;
--seales que vamos a generar: inputs:
signal clk: std_logic :='0';
signal reset: std_logic :='0';
--seales que vamos a comprobar si estan bien: outputs:
signal p_t: std_logic;
begin
--instanciacion:
uut: pulso_tiempo port map(
clk=> clk,
reset=> reset,
P_t=> P_t);
P_RESET: process
begin
reset<='0';
wait for 33 ns;
reset<='1';
wait for 89 ns;
reset<='0';
assert false report "puesto el reset" severity note;
wait;-- espera para siempre
end process;
P_Clk: Process
begin
clk <= '1';
wait for 10 ns;
clk <= '0';
wait for 10 ns;
end process;
end behavior;

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--------------------- DUENDE -------------------------------------actualizado


201401151505 (2014/01/15 15:04)
------------------------------------------------------------------------------------------------------------------------------------library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
--------------------------------------------------------------------entidad
entity DUENDE is
PORT(
p_t,RESET,CLK: IN std_logic;
registro: inout std_logic_vector(7 downto 0)
);
end DUENDE;
architecture Behavioral of DUENDE is
COMPONENT reg8desp
PORT(
carga : IN std_logic;
desp : IN std_logic;
reset : IN std_logic;
clk : IN std_logic;
registro : INOUT std_logic_vector(7 downto 0)
);
END COMPONENT;
COMPONENT pulso_tiempo
generic (max: integer range 0 to 2**26-1 := 150);
port(
clk,reset: in std_logic;
p_t: out std_logic);
END COMPONENT;
for I_reg8desp: reg8desp use entity work.reg8desp(behav);
for I_pulso_t1: pulso_tiempo use entity work.pulso_tiempo(comportamental);
signal a:std_logic;
begin
I_reg8desp: reg8desp PORT MAP(
carga => p_t,
desp => a ,
reset => RESET ,
clk => clk,
registro => registro
);
I_pulso_t1: pulso_tiempo
generic map (max => 150)
PORT MAP(
clk => clk,
reset => reset,
p_t => a
);
end Behavioral;

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----------------- DUENDE_tb -------------------------------------actualizado


201401151018 (2014/01/15 10:18)
---------------------------------------------------------------LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
use ieee.numeric_std.all;
ENTITY duende_tb IS
END duende_tb;
ARCHITECTURE behavior OF duende_tb IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT duende
PORT(
p_t,RESET,CLK: IN std_logic;
registro: inout std_logic_vector(7 downto 0)
);
END COMPONENT;
signal p_t,reset,clk: std_logic := '0';
signal registro: std_logic_vector(7 downto 0);
BEGIN
uut: duende port map(
p_t=> p_t,
reset=> reset,
clk=> clk,
registro=> registro);
P_Clk: Process
begin
clk <= '1';
wait for 10 ns;
clk <= '0';
wait for 10 ns;
end process;
-- Stimulus process
P_CARGA: process
begin
p_t<='0';
wait for 320 ns;
p_t<='1';
wait for 40 ns;
p_t<='0';
wait for 600 ns;
p_t<='1';
wait for 40 ns;
p_t<='0';
wait for 1000 ns;
p_t<='1';
wait for 40 ns;
p_t<='0';
wait for 2000 ns;
p_t<='1';
wait for 40 ns;
p_t<='0';
wait for 4000 ns;
reset<= '1';
wait for 300 ns;
reset<= '0';
assert false
report "puesto el reset" severity note;
wait;-- espera para siempre
end process;
END;

Time
clk=1

p_t=0
registro[7:0]=00000000 0000+ 00000001
reset=0

1 us

2 us

3 us

00000010

4 us

5 us

00000011

6 us

00000110

7 us

8 us

9 us

00000000

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----------------------- REG8DESP ------------------------------actualizado


201401150917 (2014/01/15 09:17)
---------------------------------------------------------------_________
-|
|
-carga ____|
|
-|
|
-|
|
-desp ____|
COD
|____ registro
-|
|
-|
|
-clk ____| 8 A 3 |
-|
|
-|
|
-|_________|
-|
-|
-reset
--- Este modulo es un registro con desplazamiento a izquierda
-- con carga en el bit menos significativo.
------------------------------------------------------------------------------------ NOTA ------------------------------------ El registro se compone de 8 bits de manera que el
-- desplazamiento lo hace de forma octal. El desplazamiento
-- se efectua cuando la entrada 'desp' se activa a nivel alto
-- y haya habido un flanco de subida del reloj 'clock'.
--- Por tanto si se mantiene activada la entrada 'desp' el
-- desplazamiento se hara con cada ciclo de reloj.
--- Como consecuencia, si se desea un desplazamiento controlado,
-- el pulso de 'desp' debe durar el periodo del reloj 'clk'.
--------------------------------------------------------------library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
-----------------------------------------------------------------entidad
entity reg8desp is
port(

carga:

in std_logic; --entrada que carga '1' al bit


-- menos significativo
desp:
in std_logic;-- entrada que crea desplazamiento
reset: in std_logic;-- pone a 0000000 el registro
clk:
in std_logic;
registro: inout std_logic_vector (7 downto 0):="00000000");

end reg8desp;
----------------------------------------------------------------arquitectura
architecture behav of reg8desp is
begin
P_registro: Process (reset, clk)
begin
if reset = '1' then
registro <= (others => '0');
elsif clk'event and clk='1' then
if desp = '1' then
registro (2 downto 1) <= registro (1 downto 0);
registro (4) <= registro (2); -- aqui se salta el registro(3)
registro (6 downto 5) <= registro (5 downto 4);
--el registro 7 no recibe ningun valor
registro(0)<='0';
end if;
if carga='1'then
registro(0) <= '1';
end if;
end if;
end process;
end behav;
---------------------------------------------------------------

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--------------------- Test Bench reg8desp --------------------------actualizado


201301131854 (2013/01/13 18:54)
-----------------------------------------------------------------------------------------------------------------------------------------libreria
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
--------------------------------------------------------------------entidad
entity reg8desp_tb is
end reg8desp_tb;
-------------------------------------------------------------------arquitectura
architecture behavior of reg8desp_tb is
--declaracion de componentes a examinar
component reg8desp is
port(
carga: in std_logic; --entrada que carga '1' al bit
-- menos significativo
desp:
in std_logic;-- entrada que crea desplazamiento
reset: in std_logic;-- pone a 0000000 el registro
clk:
in std_logic;
registro: inout std_logic_vector (7 downto 0));
end component;
--seales que vamos a generar: inputs:
signal carga: std_logic :='0';
signal desp: std_logic :='0';
signal reset: std_logic :='0';
signal clk: std_logic :='0';
--seales que vamos a comprobar si estan bien: outputs:
signal registro: std_logic_vector (7 downto 0):="00000000";
begin
--instanciacion:
uut: reg8desp port map(
carga=> carga,
desp=> desp,
reset=> reset,
clk=> clk,
registro=> registro);
P_Clk: Process
begin
clk <= '1';
wait for 10 ns;
clk <= '0';
wait for 10 ns;
end process;
P_CLK2:Process
begin
desp
wait
desp
wait
end process;

<= '1';
for 50 ns;
<= '0';
for 50 ns;

P_CARGA: process
begin
carga<='0';
wait for 42 ns;
carga<='1';
wait for 20 ns;
carga<='0';
wait for 100 ns;
carga<='1';

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wait for 20 ns;


carga<='0';
wait for 250 ns;
carga<='1';
wait for 20 ns;
carga<='0';
wait for 500 ns;
carga<='1';
wait for 20 ns;
carga<='0';
wait for 1205 ns;
reset<= '1';
wait for 124 ns;
reset<= '0';
assert false report
"puesto el reset" severity note;
wait;-- espera para siempre
end process;

end behavior;

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----------------- Multiplexor 2 a 1 ----------------------actualizado


201401150832 (2014/01/15 08:32)
-- no comprobado su funcionamiento (compila bien)
----------------------------------------------------------______
-|
\
-inA_/n__| 0
\
-|
|
-| 1
|___/n__ outZ
-inb_/n__|
|
-|
/
-|______/
-|
-|
-selecS
---Este es un multiplexor de dos entradas de n bits
--y una salida de n bits con un selector de 1 bit.
-----------------------------------------------------------librerias
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
------------------------------------------------------------entidad
entity

mux2to1 is
generic(nbits: natural range 1 to 32 :=4);
port(

inA: in std_logic_vector (nbits - 1 downto 0);


inB: in std_logic_vector (nbits - 1 downto 0);
selecS: in std_logic;
outZ: out std_logic_vector (nbits - 1 downto 0));

end mux2to1;
------------------------------------------------------------arquitectura comportamental RTL
architecture behavioral of mux2to1 is
begin
outZ <= inA when selecS = '0' else
inB;
end behavioral;
------------------------------------------------------------arquitectura comportamental abstracta
architecture abstracta of mux2to1 is
begin
process(inA,inB,selecS)
begin
if selecS = '0' then outZ<=inA;
else outZ<=inB;
end if;
end process;
end abstracta;
-----------------------------------------------------------

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-----------------BINTO7SEG
-------------------------------- Decoder binario a hexa 7 segmentos -------------actualizado
201401131203 (2014/01/13 12:03)
----------------------------------------------------------__________
-| binario |
-bin_/4__|
a
|___/7__ seg
-| 7 segm |
-|__________|
--- Es un decoder que convierte de codigo binario a
-- hexadecimal para visualizarlo en un display de
-- 7 segmentos a nivel bajo
---entrada
salida
_______________
-- num. bin
a b c d e f g
|
___a__
|
-0
0000
0 0 0 0 0 0 1
|
|
|
|
-1
0001
1 0 0 1 1 1 1
| f|
|b
|
-2
0010
0 0 1 0 0 1 0
|
|
g |
|
-3
0011
0 0 0 0 1 1 0
|
-----|
-4
0100
1 0 0 1 1 0 0
|
|
|
|
-5
0101
0 1 0 0 1 0 0
| e|
|c
|
-6
0110
0 1 0 0 0 0 0
|
|___d__|
|
-7
0111
0 0 0 1 1 1 1
|_______________|
-8
1000
0 0 0 0 0 0 0
-9
1001
0 0 0 1 1 0 0
-A
1010
0 0 0 1 0 0 0
-B
1011
1 1 0 0 0 0 0
-C
1100
0 1 1 0 0 0 1
-D
1101
1 0 0 0 0 1 0
-E
1110
0 1 1 0 0 0 0
-F
1111
0 1 1 1 0 0 0
------------------------------------------------------------Librerias
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
----------------------------------------------------------- entidad
entity binTo7seg is
port (

bin: in std_logic_vector (3 downto 0);


seg: out std_logic_vector (6 downto 0));

end binTo7seg;
----------------------------------------------------------arquitectura comportamental RTL
architecture behavioral of binTo7seg is
begin
seg <= "0000001" when bin = "0000" else --0
"1001111" when bin = "0001" else
"0010010" when bin = "0010" else
"0000110" when bin = "0011" else
"1001100" when bin = "0100" else
"0100100" when bin = "0101" else
"0100000" when bin = "0110" else
"0001111" when bin = "0111" else
"0000000" when bin = "1000" else
"0001100" when bin = "1001" else
"0001000" when bin = "1010" else
"1100000" when bin = "1011" else
"0110001" when bin = "1100" else
"1000010" when bin = "1101" else
"0110000" when bin = "1110" else
"0111000"; --F
end behavioral;
-------------------------------------------------------

--1
--2
--3
--4
--5
--6
--7
--8
--9
--A
--B
--C
--D
--E

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--arquitectura comportamental abstracta


architecture abstracta of binTo7seg is
begin
process (bin)
begin
if bin = "0000" then seg<="0000001";
-- 0
elsif bin = "0001" then seg<="1001111"; --1
elsif bin = "0010" then seg<="0010010"; --2
elsif bin = "0011" then seg<="0000110"; --3
elsif bin = "0100" then seg<="1001100"; --4
elsif bin = "0101" then seg<="0100100"; --5
elsif bin = "0110" then seg<="0100000"; --6
elsif bin = "0111" then seg<="0001111"; --7
elsif bin = "1000" then seg<="0000000"; --8
elsif bin = "1001" then seg<="0001100"; --9
elsif bin = "1010" then seg<="0001000"; --A
elsif bin = "1011" then seg<="1100000"; --B
elsif bin = "1100" then seg<="0110001"; --C
elsif bin = "1101" then seg<="1000010"; --D
elsif bin = "1110" then seg<="0110000"; --E
else seg<="0111000";
end if;
end process;
end abstracta;
--------------------------------------------------------

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---------------Decoder 2 a 4
-------------------------------actualizado
201401150829 (2014/01/15 08:29)
-- no comprobado su funcionamiento (compila bien)
-----------------------------------------------------------------_________
-|
|
-|
|
-I ____|
DEC
|___/4__ S
-|
|
-E ___o| 2 a 4 |
-|
|
-|_________|
--- Decodificador 1 a 2 con una entrada de habilitacion a nivel
-- bajo.
----------------------------------------------------------------------------------------DETALLES------------------------------------- por defecto la salida esta en logica negada, para cambiarlo
-- hay que modificarlo en generic:
-logica := '0'
logica negada
-logica := '1'
logica positiva
---Tabla de verdad:
-_________________
-| E | I | S1 S0 |
-| --|-----|-------|
-| 0 | X | 0 0 |
-| 1 | 0 | 0 1 |
-| 1 | 1 | 1 0 |
-|___|_____|_______|
-------------------------------------------------------------librerias
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
-----------------------------------------------------------entidad
entity dec1to2 is
generic(logica: bit := '0');
port (

I: in std_logic;
E: in std_logic;
S: out std_logic_vector (1 downto 0));

end dec1to2;
-----------------------------------------------------------arquitectura comportamental RTL
architecture behavioral of dec1to2 is
signal S_prev: std_logic_vector (1 downto 0); -- es la seal previa
-- en logica positiva que podr ser modificada mas adelante si
-- la entrada "logica" esta a nivel bajo.
signal E_neg: std_logic;
begin
E_neg <= not E;
S_prev<="00" when E_neg = '0' else
"01" when I = '0' else
"10" ;
S <= not (S_prev) when logica='0' else
S_prev;
-- Aqui se asigna la seal en logica positiva o neg.
end behavioral;
----------------------------------------------------------

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--arquitectura comportamental abstracta


architecture abstracta of dec1to2 is
begin
process(I,E)
variable negE: std_logic;
variable prevS: std_logic_vector (1 downto 0);
begin
negE := not (E);
if negE = '0' then prevS:= "00";
elsif I='0' then prevS:="01";
else prevS:="10";
end if;
if logica='0' then S<=not (prevS); --seleccionamos logica del disp.
else S<= prevS;
end if;
end process;
end abstracta;
----------------------------------------------------------

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------------------- BALANCEADOR 2 ELEMENTOS ----------------------actualizado


201401150823 (2014/01/15 08:23)
-------------------------------------------------------------------_____________
-|
|
-|
|
-|
____
|
-clk_T ___|
^
|____ balance
-|
___|
|
-|
|
-|_____________|
--- Este es un comenente sencillo que lo unico que hace es
-- alternar dos estados logicos a la frecuencia del reloj.
-------------------------------------------------------------------------------------- DETALLES ---------------------------------------__
__
__
__
__
__
__
__
__
__
-- clk_T __| |__| |__| |__| |__| |__| |__| |__| |__| |__| |
-_____
_____
_____
_____
_____
--balance__|
|_____|
|_____|
|_____|
|_____|
|___
----------------------------------------------------------------------librerias
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
--------------------------------------------------------------------entidad
entity balan2elem is
port(
clk_T: in std_logic;
balance: out std_logic:='0');
end balan2elem;
--------------------------------------------------------------------arquitectura
architecture behav of balan2elem is
signal cuenta: natural range 0 to 1 :=0;
begin
process(clk_T)
begin
if clk_T = '1' and clk_T'event then
if cuenta = 0 then balance<='0';
cuenta<=cuenta +1 ;
else balance<='1'; cuenta<= 0;
end if;
end if;
end process;
end behav;
------------------------------------------------------------------

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------------------- REG_TOP ------------------------------------ actualizado 201401151050 (2014/01/15 10:50)


---------------------------------------------------------------library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
-------------------------------------------------------------------entidad
entity REG_TOP is
port(
BTN,RESET,CLK: in std_logic;
SEGMENT: OUT std_logic_vector(6 downto 0);
LEDS: OUT std_logic_vector(7 downto 0);
DIGCTRL: OUT std_logic_vector(1 downto 0);
uno1,uno2: out std_logic
);
end REG_TOP;
architecture Behavioral of REG_TOP is
COMPONENT DUENDE
PORT(
p_t : IN std_logic;
RESET : IN std_logic;
CLK : IN std_logic;
registro : INOUT std_logic_vector(7 downto 0));
END COMPONENT;
COMPONENT antirrebote
PORT(
Btn : IN std_logic;
clk_T : IN std_logic;
reset : IN std_logic;
sin_reb : OUT std_logic);
END COMPONENT;
COMPONENT balan2elem
PORT(
clk_T : IN std_logic;
balance : OUT std_logic );
END COMPONENT;
COMPONENT binTo7seg
PORT(
bin : IN std_logic_vector(3 downto 0);
seg : OUT std_logic_vector(6 downto 0));
END COMPONENT;
COMPONENT dec1to2
generic(logica: bit := '0');
port ( I: in std_logic;
E: in std_logic;
S: out std_logic_vector (1 downto 0));
END COMPONENT;
COMPONENT detec_pulso
PORT(
BT : IN std_logic;
clk : IN std_logic;
pulso : OUT std_logic);
END COMPONENT;
COMPONENT mux2to1
generic(nbits: natural range 1 to 32 :=4);
port(

inA: in std_logic_vector (nbits - 1 downto 0);


inB: in std_logic_vector (nbits - 1 downto 0);
selecS: in std_logic;
outZ: out std_logic_vector (nbits - 1 downto 0));

END COMPONENT;
COMPONENT pulso_tiempo
generic (max: integer range 0 to 2**26-1 := 150);
port(
clk,reset: in std_logic;
p_t: out std_logic);
END COMPONENT;
for
for
for
for

I_duende: duende use entity work.duende(behavioral);


I_antirrebote: antirrebote use entity work.antirrebote(behavioral);
I_balan2elem: balan2elem use entity work.balan2elem(behav);
I_binTo7seg: binTo7seg use entity work.binTo7seg(abstracta);

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for
for
for
for
for

I_dec1to2: dec1to2 use entity work.dec1to2(abstracta);


I_detec_pulso: detec_pulso use entity work.detec_pulso(comportamental);
I_mux2to1: mux2to1 use entity work.mux2to1(abstracta);
I_pulso_2: pulso_tiempo use entity work.pulso_tiempo(comportamental);
I_pulso_3: pulso_tiempo use entity work.pulso_tiempo(comportamental);

SIGNAL
SIGNAL
SIGNAL
signal

a_i,b_i,c_i,d_i,e_i: std_logic;
g_i: STD_LOGIC_VECTOR(3 DOWNTO 0);
f_i: STD_LOGIC_VECTOR(7 DOWNTO 0);
uno: std_logic:='1';

BEGIN
uno1<=uno;
uno2<=uno;
LEDS<= f_i;
I_DUENDE: DUENDE PORT MAP(
p_t => a_i ,
RESET => RESET ,
CLK => CLK ,
registro => f_i );
I_antirrebote: antirrebote PORT MAP(
Btn => BTN,
clk_T => b_i ,
reset => RESET,
sin_reb => c_i);
I_balan2elem: balan2elem PORT MAP(
clk_T => d_i,
balance => e_i);
I_binTo7seg: binTo7seg PORT MAP(
bin => g_i ,
seg => SEGMENT);
I_dec1to2: dec1to2 PORT MAP(
I => e_i ,
E => '0',
S (0)=> DIGCTRL(0),
S (1)=> DIGCTRL(1));
I_detec_pulso: detec_pulso PORT MAP(
BT => c_i ,
clk => CLK,
pulso => a_i);
I_mux2to1: mux2to1 PORT MAP(
inA => f_i( 3 downto 0),
inB => f_i( 7 downto 4),
selecS => e_i,
outZ => g_i);
I_pulso_2: pulso_tiempo
generic map (max => 500000)
PORT MAP(
clk => CLK,
reset => RESET ,
p_t => b_i);
I_pulso_3: pulso_tiempo
generic map (max => 500000)
PORT MAP(
clk => CLK ,
reset => RESET ,
p_t => d_i);
end Behavioral;

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------------------- REG_TOP_tb --------------------------------- actualizado 201401151111 (2014/01/15 11:11)


---------------------------------------------------------------LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
--USE ieee.std_logic_unsigned.all;
--USE ieee.numeric_std.ALL;
USE IEEE.NUMERIC_STD.ALL;
ENTITY REG_TOP_TB IS
END REG_TOP_TB;
ARCHITECTURE behavior OF REG_TOP_TB IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT REG_TOP
PORT(
BTN : IN std_logic;
RESET : IN std_logic;
CLK : IN std_logic;
SEGMENT : OUT std_logic_vector(6 downto 0);
LEDS : OUT std_logic_vector(7 downto 0);
uno1,uno2: out std_logic;
DIGCTRL : OUT std_logic_vector(1 downto 0)
);
END COMPONENT;
--Inputs
signal BTN : std_logic := '0';
signal RESET : std_logic := '0';
signal CLK : std_logic := '0';
--Outputs
signal SEGMENT : std_logic_vector(6 downto 0);
signal LEDS : std_logic_vector(7 downto 0);
signal DIGCTRL : std_logic_vector(1 downto 0);
signal uno1, uno2: std_logic;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: REG_TOP PORT MAP (
BTN => BTN,
RESET => RESET,
CLK => CLK,
SEGMENT => SEGMENT,
LEDS => LEDS,
DIGCTRL => DIGCTRL,
uno1=>uno1,
uno2=>uno2
);

P_Clk: Process
begin
clk <= '1';
wait for 10 ns;
clk <= '0';
wait for 10 ns;
end process;

-- Stimulus process
P_CARGA: process
begin
BTN<='0';
wait for 580 ns;
---------pulsacion--------BTN<='1';
wait for 1 ns;

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BTN<='0';
wait for 12 ns;
BTN<='1';
wait for 3 ns;
BTN<='0';
wait for 9 ns;
BTN<='1';
wait for 1 ns;
BTN<='0';
wait for 9 ns;
BTN<='1';
wait for 4 ns;
BTN<='0';
wait for 13 ns;
BTN<='1';
wait for 6 ns;
BTN<='0';
wait for 8 ns;
BTN<='1';
wait for 5 ns;
BTN<='0';
wait for 9 ns;
BTN<='1';
wait for 8 ns;
BTN<='0';
wait for 9 ns;
BTN<='1';
wait for 9 ns;
BTN<='0';
wait for 7 ns;
BTN<='1';
wait for 9 ns;
BTN<='0';
wait for 4 ns;
BTN<='1';
wait for 9 ns;
BTN<='0';
wait for 1 ns;
BTN<='1';
wait for 390 ns;
BTN<='0';
-----------------wait for 3500 ns;
---------pulsacion--------BTN<='1';
wait for 1 ns;
BTN<='0';
wait for 12 ns;
BTN<='1';
wait for 3 ns;
BTN<='0';
wait for 9 ns;
BTN<='1';
wait for 1 ns;
BTN<='0';
wait for 9 ns;
BTN<='1';
wait for 4 ns;
BTN<='0';
wait for 13 ns;
BTN<='1';
wait for 6 ns;
BTN<='0';
wait for 8 ns;
BTN<='1';
wait for 5 ns;
BTN<='0';
wait for 9 ns;
BTN<='1';
wait for 8 ns;
BTN<='0';
wait for 9 ns;

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BTN<='1';
wait for 9 ns;
BTN<='0';
wait for 7 ns;
BTN<='1';
wait for 9 ns;
BTN<='0';
wait for 4 ns;
BTN<='1';
wait for 9 ns;
BTN<='0';
wait for 1 ns;
BTN<='1';
wait for 390 ns;
BTN<='0';
-----------------wait for 1250 ns;
---------pulsacion--------BTN<='1';
wait for 1 ns;
BTN<='0';
wait for 12 ns;
BTN<='1';
wait for 3 ns;
BTN<='0';
wait for 9 ns;
BTN<='1';
wait for 1 ns;
BTN<='0';
wait for 9 ns;
BTN<='1';
wait for 4 ns;
BTN<='0';
wait for 13 ns;
BTN<='1';
wait for 6 ns;
BTN<='0';
wait for 8 ns;
BTN<='1';
wait for 5 ns;
BTN<='0';
wait for 9 ns;
BTN<='1';
wait for 8 ns;
BTN<='0';
wait for 9 ns;
BTN<='1';
wait for 9 ns;
BTN<='0';
wait for 7 ns;
BTN<='1';
wait for 9 ns;
BTN<='0';
wait for 4 ns;
BTN<='1';
wait for 9 ns;
BTN<='0';
wait for 1 ns;
BTN<='1';
wait for 390 ns;
BTN<='0';
-----------------wait for 1000 ns;
---------pulsacion--------BTN<='1';
wait for 1 ns;
BTN<='0';
wait for 12 ns;
BTN<='1';
wait for 3 ns;

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BTN<='0';
wait for 9 ns;
BTN<='1';
wait for 1 ns;
BTN<='0';
wait for 9 ns;
BTN<='1';
wait for 4 ns;
BTN<='0';
wait for 13 ns;
BTN<='1';
wait for 6 ns;
BTN<='0';
wait for 8 ns;
BTN<='1';
wait for 5 ns;
BTN<='0';
wait for 9 ns;
BTN<='1';
wait for 8 ns;
BTN<='0';
wait for 9 ns;
BTN<='1';
wait for 9 ns;
BTN<='0';
wait for 7 ns;
BTN<='1';
wait for 9 ns;
BTN<='0';
wait for 4 ns;
BTN<='1';
wait for 9 ns;
BTN<='0';
wait for 1 ns;
BTN<='1';
wait for 390 ns;
BTN<='0';
-----------------wait for 4000 ns;
---------pulsacion--------BTN<='1';
wait for 1 ns;
BTN<='0';
wait for 12 ns;
BTN<='1';
wait for 3 ns;
BTN<='0';
wait for 9 ns;
BTN<='1';
wait for 1 ns;
BTN<='0';
wait for 9 ns;
BTN<='1';
wait for 4 ns;
BTN<='0';
wait for 13 ns;
BTN<='1';
wait for 6 ns;
BTN<='0';
wait for 8 ns;
BTN<='1';
wait for 5 ns;
BTN<='0';
wait for 9 ns;
BTN<='1';
wait for 8 ns;
BTN<='0';
wait for 9 ns;
BTN<='1';
wait for 9 ns;
BTN<='0';
wait for 7 ns;

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BTN<='1';
wait for 9 ns;
BTN<='0';
wait for 4 ns;
BTN<='1';
wait for 9 ns;
BTN<='0';
wait for 1 ns;
BTN<='1';
wait for 390 ns;
BTN<='0';
-----------------wait for 8000 ns;
---------pulsacion--------BTN<='1';
wait for 1 ns;
BTN<='0';
wait for 12 ns;
BTN<='1';
wait for 3 ns;
BTN<='0';
wait for 9 ns;
BTN<='1';
wait for 1 ns;
BTN<='0';
wait for 9 ns;
BTN<='1';
wait for 4 ns;
BTN<='0';
wait for 13 ns;
BTN<='1';
wait for 6 ns;
BTN<='0';
wait for 8 ns;
BTN<='1';
wait for 5 ns;
BTN<='0';
wait for 9 ns;
BTN<='1';
wait for 8 ns;
BTN<='0';
wait for 9 ns;
BTN<='1';
wait for 9 ns;
BTN<='0';
wait for 7 ns;
BTN<='1';
wait for 9 ns;
BTN<='0';
wait for 4 ns;
BTN<='1';
wait for 9 ns;
BTN<='0';
wait for 1 ns;
BTN<='1';
wait for 390 ns;
BTN<='0';
-----------------wait for 10000 ns;
-----reset
reset<= '1';
wait for 200 ns;
reset<= '0';
assert false report
"puesto el reset" severity note;
wait;-- espera para siempre
end process;
END;

Time
btn

sin_reb
pulso
clk
leds[7:0]
000000+ 00000001
segment[6:0] 0000001
digctrl[1:0]
reset
uno1
uno2

10 us

00000010

00000011

0000+ 00000111

00010110

0011+ 00110101

01110010

Time
btn
sin_reb
pulso
clk
leds[7:0]
0111+ 01100100
segment[6:0]
digctrl[1:0]
reset
uno1
uno2

20 us

30 us

01010001

00100010
0010010

01000100
1001100

00010000

00000000
0000001
+

Time
btn

4300 ns

4400 ns

4500 ns

4600 ns

4700 ns

4800 ns

4900 ns

5 us

5100 ns

5200 ns

5300 ns

sin_reb
pulso
clk
leds[7:0]
00000010
00000011
segment[6:0] 0000+ 0010+ 0000+ 0010+ 0000+ 0010+ 0000+ 0010+ 0000+ 0000+ 0000+ 0000+ 0000+ 0000+ 0000+ 0000+ 0000+ 0000+ 0000+ 0000+ 0000+ 0000+ 0000+ 0000+ 0000+ 0000+ 0000+ 0000110
digctrl[1:0] 01
10
01
10
01
10
01
10
01
10
01
10
01
10
01
10
01
10
01
10
01
10
01
10
01
10
01
10
reset
uno1
uno2

Time
btn

4600 ns

sin_reb
pulso
clk
leds[7:0]
00000010
segment[6:0] 00+ 0010010
digctrl[1:0] 01 10
reset
uno1
uno2

4700 ns

0000001
01

00000011
0000110
10

0000001
01

4800 ns

0000110
10

0000001
01

4900 ns

0000110
10

0000001
01

0000110
10

5 us

0000001
01

0000110
10

5100 ns

0000001
01

0000110
10

0000001
01

Asociacin de patillas de la FPGA con las seales del mdulo REG_TOP


Seleccionamos el nivel superior REG_TOP.
Seleccionamos en la ventana abajo izquierda:
User Constraints I/O Pin Planning (Plan Ahead) Post Synthesis
Se abre el cuadro para comenzar a utilizar la aplicacin PlanAhead
Configuramos todos los puertos a LVCMOS33 ya que la tarjeta funciona 3,3 V.
Comenzamos a asignar los pines pinchando con el botn derecho sobre:
Place I/O Port in a I/O Bank (nos permite sealarlo grficamente)

Esto nos permite sealarlo grficamente en el cuadro de la derecha:

Una vez asignados todos los pines le damos a guardar y nos crear un fichero .ucf cuyo contenido
se puede editar.

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--------- REG_TOP_UCF --------------INST "CLK_BUFGP" LOC = BUFGMUX0;


NET "BTN" LOC = M13;
NET "BTN" IOSTANDARD = LVCMOS33;
NET "CLK" LOC = T9;
NET "CLK" IOSTANDARD = LVCMOS33;
NET "DIGCTRL[0]" LOC = D14;
NET "DIGCTRL[0]" IOSTANDARD = LVCMOS33;
NET "DIGCTRL[1]" LOC = G14;
NET "DIGCTRL[1]" IOSTANDARD = LVCMOS33;
NET "UNO1" LOC = F14;
NET "UNO1" IOSTANDARD = LVCMOS33;
NET "UNO2" LOC = E13;
NET "UNO2" IOSTANDARD = LVCMOS33;
NET "LEDS[0]" LOC = K12;
NET "LEDS[0]" IOSTANDARD = LVCMOS33;
NET "LEDS[1]" LOC = P14;
NET "LEDS[1]" IOSTANDARD = LVCMOS33;
NET "LEDS[2]" LOC = L12;
NET "LEDS[2]" IOSTANDARD = LVCMOS33;
NET "LEDS[3]" LOC = N14;
NET "LEDS[3]" IOSTANDARD = LVCMOS33;
NET "LEDS[4]" LOC = P13;
NET "LEDS[4]" IOSTANDARD = LVCMOS33;
NET "LEDS[5]" LOC = N12;
NET "LEDS[5]" IOSTANDARD = LVCMOS33;
NET "LEDS[6]" LOC = P12;
NET "LEDS[6]" IOSTANDARD = LVCMOS33;
NET "LEDS[7]" LOC = P11;
NET "LEDS[7]" IOSTANDARD = LVCMOS33;
NET "RESET" LOC = L14;
NET "RESET" IOSTANDARD = LVCMOS33;
NET "SEGMENT[0]" LOC = N16;
NET "SEGMENT[0]" IOSTANDARD = LVCMOS33;
NET "SEGMENT[1]" LOC = F13;
NET "SEGMENT[1]" IOSTANDARD = LVCMOS33;
NET "SEGMENT[2]" LOC = R16;
NET "SEGMENT[2]" IOSTANDARD = LVCMOS33;
NET "SEGMENT[3]" LOC = P15;
NET "SEGMENT[3]" IOSTANDARD = LVCMOS33;
NET "SEGMENT[4]" LOC = N15;
NET "SEGMENT[4]" IOSTANDARD = LVCMOS33;
NET "SEGMENT[5]" LOC = G13;
NET "SEGMENT[5]" IOSTANDARD = LVCMOS33;
NET "SEGMENT[6]" LOC = E14;
NET "SEGMENT[6]" IOSTANDARD = LVCMOS33;