INPUT-OUTPUT MODULES The computer will be of no use if it is not communicating with the external world.

A Computer must have a system to receive information from outside world and must be able to communicate results to external world. Thus, a computer consists of an I/O (input output) system. This system includes two basic components: (i) the I/O devices and (ii) I/O module, which not only connects an I/O device with the system bus, but plays a very crucial role in between. A device which is connected to an I/O module of computer is called a peripheral device. The input/output module (I/O module) is normally connected to the computer system on one end and one or more input/output devices on the other. An I/O module is needed because of: (a) Diversity of I/O devices makes it difficult to include all the peripheral device logic (i.e. its control commands, data format etc.) into CPU. (b) The I/O devices are usually slower than the memory and CPU. Therefore, it is not advisable to use them on high speed system bus directly for communication purpose. (c) The data format and word length used by the peripheral may be quite different than that of a CPU. Thus, we can say that: (i) An I/O module is a mediator between the processor and an I/O device/devices. (ii) It controls the data exchange between the external devices and main memory; or external devices and CPU registers. (iii) An I/O module provide an interface internal to the computer which connects it to CPU and main memory and an interface external to the computer connecting it to external device or peripheral. (iv) The I/O module should not only communicate the information from CPU to I/O device, but it should also coordinate these two. (v) In addition since there are speed differences between CPU and I/O devices, the I/O module should have facilities like buffer (storage area) and error detection mechanism. Functions of I/O Module: The major functions of an I/O module are: 1. Processor communication -- this involves the following tasks: exchange of data between processor and I/O module,

 Command decoding - I/O module accepts commands sent from the processor. E.g., the I/O module for a disk drive may accept the following commands from the processor: READ SECTOR, WRITE SECTOR, SEEK track, etc. status reporting The device must be able to report its status to the processor, e.g., disk drive busy, ready etc. Status reporting may also involve reporting various errors. Address recognition Each I/O device has a unique address and the I/O module must recognize this address. 2. Device communication The I/O module must be able to perform device communication such as status reporting. 3. Control & timing The I/O module must be able to co-ordinate the flow of data between the internal resources (such as processor, memory) and external devices. 4. Data buffering This is necessary as there is a speed mismatch between speed of data transfer between processor and memory and external devices. Data coming from the main memory are sent to an I/O module in a rapid burst. The data is buffered in the I/O module and then sent to the peripheral device at its rate. 5. Error detection The I/O module must also be able to detect errors and report them to the processor. These errors may be mechanical errors (such as paper jam in a printer), or changes in the bit pattern of transmitted data. A common way of detecting such errors is by using parity bits.

PROGRAMMED I/O: Using this technique, data transfer takes place under the direct control of the processor. The processor must continuously check an I/O device and hence it cannot do another task. This method is hence inefficient (slow).

Characteristics of Programmed I/O: 1. In programmed I/O, the I/O operations are completely controlled by the CPU 2. Used in real-time and embedded systems. 3. Used in CPUs which have a single input and a single output instruction. Each of these instructions selects one device. 4. The disadvantage of this technique is that the CPU spends most of its time waiting for the device to become ready.

INTERRUPT DRIVEN INPUT/OUTPUT The basic drawback of programmed I/O is that the speed of I/O devices is much slower in comparison to that of CPU, and because the CPU has to repeatedly check whether a device is free; or wait till the completion of I/O, therefore, the performance of CPU in programmed I/O goes down tremendously. What is the solution? What about CPU going back to do other useful work without waiting for the I/O device to complete or get freed up. On completion of I/O, the I/O device interrupts the CPU to tell it has finished the work.

Interrupt: The term interrupt is used for any event that causes temporary transfer of control of CPU from one program to the other which is causing the interrupt. Interrupts are primarily issued on: Initiation of Input/output operation (interrupt issued by I/O devices) Completion of an Input/output operation Occurrence of hardware or software errors. Interrupts can be generated by various sources internal or external to the CPU. In the interrupt driven I/O the processor issues a READ/WRITE instruction to the device and then continues doing its task. When the interface buffer is full, and it is ready to send data to the processor, the interface sends a signal to the processor informing it that data is ready. This signal is called as the interrupt signal. When the processor receives the interrupt signal, it knows that the data is ready; it suspends its current job and transfers data from buffer to its own registers. Disadvantages of Interruptdriven I/O technique: The processor must suspend its work and later resume it. If there are many devices, each can issue an interrupt and the processor must be able to attend each of these, based on some priority. The role of the processor in interrupt-driven I/O: When an I/O device is ready to send data, the following events occur: 1. The device issues an interrupt signal to the processor. 2. The processor finishes execution of the current instruction. It then responds to the interrupt signal. 3. The processor sends an acknowledgement signal to the device that sent the interrupt. The device then removes its interrupt signal. 4. The processor must save the state of the current task (i.e., the values of registers, the address of the next instruction to be executed, etc.). These are saved onto a stack. 5. The processor then attends to the device that issued to the interrupt signal. 6. When interrupt processing is over the saved registers are retrieved from the stack and the processor continues its previous task from the point where it was last stopped. When the processor detects an interrupt, it executes an interrupt-service routine. This routine polls each I/O device to determine which device caused the interrupt. This technique is called software poll.

DIRECT MEMORY ACCESS

Stands for "Direct Memory Access." DMA is a method of transferring data from the computer's RAM to another part of the computer without processing it using the CPU. While most data that is input or output from your computer is processed by the CPU, some data does not require processing, or can be processed by another device. In these situations, DMA can save processing time and is a more efficient way to move data from the computer's memory to other devices. For example, a sound card may need to access data stored in the computer's RAM, but since it can process the data itself, it may use DMA to bypass the CPU. Video cards that support DMA can also access the system memory and process graphics without needing the CPU. Ultra DMA hard drives use DMA to transfer data faster than previous hard drives that required the data to first be run through the CPU. In order for devices to use direct memory access, they must be assigned to a DMA channel. Each type of port on a computer has a set of DMA channels that can be assigned to each connected device. For example, a PCI controller and a hard drive controller each have their own set of DMA channels. This method eliminates the need for the continuous involvement of the processor in the I/O operations. The data transfer now takes place as follows:

1. When a read instruction is encountered, the processor sends the device address via the Device Address Bus (DAB). This is decoded by the I/O controller and the DMA interface of the appropriate device is selected. The processor also sends the address (in RAM) where the data is to be stored. The READ command is issued. 2. The processor continues with the next instruction in the program. It has no further role to play in data transfer. 3. The DMA status register is set to 1 to indicate the BUSY status. Data is read from the device and stored in the DMAs data register (buffer). 4. When data has been entered in the data register, the data ready flip-flop is set to 1 and an interrupt is sent to the processor. 5. The processor completes the current instruction. It then gives control of MAB and DB to the DMA interface. The DMA transfers data from its data registers to the memory address specified.

MODES OF OPERATION Burst mode An entire block of data is transferred in one contiguous sequence. Once the DMA controller is granted access to the system bus by the CPU, it transfers all bytes of data in the data block before releasing control of the system buses back to the CPU, but renders the CPU inactive for relatively long periods of time. The mode is also called "Block Transfer Mode". Cycle stealing mode The cycle stealing mode is used in systems in which the CPU should not be disabled for the length of time needed for burst transfer modes. In the cycle stealing mode, the DMA controller obtains access to the system bus the same way as in burst mode, using BR (Bus Request) and BG (Bus Grant) signals, which are the two signals controlling the interface between the CPU and the DMA controller. However, in cycle stealing mode, after one byte of data transfer, the control of the system bus is deasserted to the CPU via BG. It is then continually requested again via BR, transferring one byte of data per request, until the entire block of data has been transferred. By continually obtaining and releasing the control of the system bus, the DMA controller

essentially interleaves instruction and data transfers. The CPU processes an instruction, then the DMA controller transfers one data value, and so on. On the one hand, the data block is not transferred as quickly in cycle stealing mode as in burst mode, but on the other hand the CPU is not idled for as long as in burst mode. Cycle stealing mode is useful for controllers that monitor data in real time. Transparent mode The transparent mode takes the most time to transfer a block of data, yet it is also the most efficient mode in terms of overall system performance. The DMA controller only transfers data when the CPU is performing operations that do not use the system buses. It is the primary advantage of the transparent mode that the CPU never stops executing its programs and the DMA transfer is free in terms of time. The disadvantage of the transparent mode is that the hardware needs to determine when the CPU is not using the system buses, which can be complex.

DMA CONFIGURATION

Single Bus, Detached DMA controller Each transfer uses bus twice I/O to DMA then DMA to memory CPU is suspended twice

 Single Bus, Integrated DMA controller Controller may support >1 device Each transfer uses bus once DMA to memory CPU is suspended once

Bus supports all DMA enabled devices Each transfer uses bus once DMA to memory CPU is suspended once